{"push_id":753530151,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"625975d0a3f4115c2dc273e56e4e1f911e297bd9","before":"11a09ef0a5e83d8c40e564c6c12de6007c5175b6","commits":[{"sha":"625975d0a3f4115c2dc273e56e4e1f911e297bd9","author":{"email":"a6a97665bebbe7020828dae03f9b588f719350c6@google.com","name":"James Y Knight"},"message":"[Sparc] Implement i64 load/store support for 32-bit sparc.\n\nThe LDD/STD instructions can load/store a 64bit quantity from/to\nmemory to/from a consecutive even/odd pair of (32-bit) registers. They\nare part of SparcV8, and also present in SparcV9. (Although deprecated\nthere, as you can store 64bits in one register).\n\nAs recommended on llvmdev in the thread \"How to enable use of 64bit\nload/store for 32bit architecture\" from Apr 2015, I've modeled the\n64-bit load/store operations as working on a v2i32 type, rather than\nmaking i64 a legal type, but with few legal operations. The latter\ndoes not (currently) work, as there is much code in llvm which assumes\nthat if i64 is legal, operations like \"add\" will actually work on it.\n\nThe same assumption does not hold for v2i32 -- for vector types, it is\nworkable to support only load/store, and expand everything else.\n\nThis patch:\n- Adds a new register class, IntPair, for even/odd pairs of registers.\n\n- Modifies the list of reserved registers, the stack spilling code,\n  and register copying code to support the IntPair register class.\n\n- Adds support in AsmParser. (note that in asm text, you write the\n  name of the first register of the pair only. So the parser has to\n  morph the single register into the equivalent paired register).\n\n- Adds the new instructions themselves (LDD/STD/LDDA/STDA).\n\n- Hooks up the instructions and registers as a vector type v2i32. Adds\n  custom legalizer to transform i64 load/stores into v2i32 load/stores\n  and bitcasts, so that the new instructions can actually be\n  generated, and marks all operations other than load/store on v2i32\n  as needing to be expanded.\n\n- Copies the unfortunate SelectInlineAsm hack from ARMISelDAGToDAG.\n  This hack undoes the transformation of i64 operands into two\n  arbitrarily-allocated separate i32 registers in\n  SelectionDAGBuilder. and instead passes them in a single\n  IntPair. (Arbitrarily allocated registers are not useful, asm code\n  expects to be receiving a pair, which can be passed to ldd/std.)\n\nAlso adds a bunch of test cases covering all the bugs I've added along\nthe way.\n\nDifferential Revision: http://reviews.llvm.org/D8713","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project/commits/625975d0a3f4115c2dc273e56e4e1f911e297bd9"}]}