{"push_id":793066863,"size":16,"distinct_size":16,"ref":"refs/heads/cm-12.1","head":"3bd851e0023cf7360b444fd8458b7ae35180ac6d","before":"d04d9d67ab7e342d2d1425d8ed01cbde10dfe0d6","commits":[{"sha":"cacd1dc488bccda6e7210bb367e9d1e7713f6142","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"ARM: 7478/1: errata: extend workaround for erratum #720789\n\ncommit 5a783cbc48367cfc7b65afc75430953dfe60098f upstream.\n\nCommit cdf357f1 (\"ARM: 6299/1: errata: TLBIASIDIS and TLBIMVAIS\noperations can broadcast a faulty ASID\") replaced by-ASID TLB flushing\noperations with all-ASID variants to workaround A9 erratum #720789.\n\nThis patch extends the workaround to include the tlb_range operations,\nwhich were overlooked by the original patch.\n\nTested-by: Steve Capper <steve.capper@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\n\nConflicts:\n\tarch/arm/mm/tlb-v7.S","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/cacd1dc488bccda6e7210bb367e9d1e7713f6142"},{"sha":"955d25b57b410e98bc832d723cb9e7e41222f0c7","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"ARM: 7487/1: mm: avoid setting nG bit for user mappings that aren't present\n\ncommit 47f1204329237a0f8655f5a9f14a38ac81946ca1 upstream.\n\nSwap entries are encoding in ptes such that !pte_present(pte) and\npte_file(pte). The remaining bits of the descriptor are used to identify\nthe swapfile and offset within it to the swap entry.\n\nWhen writing such a pte for a user virtual address, set_pte_at\nunconditionally sets the nG bit, which (in the case of LPAE) will\ncorrupt the swapfile offset and lead to a BUG:\n\n[  140.494067] swap_free: Unused swap offset entry 000763b4\n[  140.509989] BUG: Bad page map in process rs:main Q:Reg  pte:0ec76800 pmd:8f92e003\n\nThis patch fixes the problem by only setting the nG bit for user\nmappings that are actually present.\n\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/955d25b57b410e98bc832d723cb9e7e41222f0c7"},{"sha":"e34da61b76ad4efd28c5c3db85e4efd8e8a7fe42","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"ARM: 7489/1: errata: fix workaround for erratum #720789 on UP systems\n\ncommit 730a8128cd8978467eb1cf546b11014acb57d433 upstream.\n\nCommit 5a783cbc4836 (\"ARM: 7478/1: errata: extend workaround for erratum\n #720789\") added workarounds for erratum #720789 to the range TLB\ninvalidation functions with the observation that the erratum only\naffects SMP platforms. However, when running an SMP_ON_UP kernel on a\nuniprocessor platform we must take care to preserve the ASID as the\nworkaround is not required.\n\nThis patch ensures that we don't set the ASID to 0 when flushing the TLB\non such a system, preserving the original behaviour with the workaround\ndisabled.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/e34da61b76ad4efd28c5c3db85e4efd8e8a7fe42"},{"sha":"5ead701134d5384ed3576d5bb85ced0dc963bb25","author":{"email":"f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","name":"Russell King"},"message":"ARM: Fix ioremap() of address zero\n\ncommit a849088aa1552b1a28eea3daff599ee22a734ae3 upstream.\n\nMurali Nalajala reports a regression that ioremapping address zero\nresults in an oops dump:\n\nUnable to handle kernel paging request at virtual address fa200000\npgd = d4f80000\n[fa200000] *pgd=00000000\nInternal error: Oops: 5 [#1] PREEMPT SMP ARM\nModules linked in:\nCPU: 0    Tainted: G        W (3.4.0-g3b5f728-00009-g638207a #13)\nPC is at msm_pm_config_rst_vector_before_pc+0x8/0x30\nLR is at msm_pm_boot_config_before_pc+0x18/0x20\npc : [<c0078f84>]    lr : [<c007903c>]    psr: a0000093\nsp : c0837ef0  ip : cfe00000  fp : 0000000d\nr10: da7efc17  r9 : 225c4278  r8 : 00000006\nr7 : 0003c000  r6 : c085c824  r5 : 00000001  r4 : fa101000\nr3 : fa200000  r2 : c095080c  r1 : 002250fc  r0 : 00000000\nFlags: NzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM Segment kernel\nControl: 10c5387d  Table: 25180059  DAC: 00000015\n[<c0078f84>] (msm_pm_config_rst_vector_before_pc+0x8/0x30) from [<c007903c>] (msm_pm_boot_config_before_pc+0x18/0x20)\n[<c007903c>] (msm_pm_boot_config_before_pc+0x18/0x20) from [<c007a55c>] (msm_pm_power_collapse+0x410/0xb04)\n[<c007a55c>] (msm_pm_power_collapse+0x410/0xb04) from [<c007b17c>] (arch_idle+0x294/0x3e0)\n[<c007b17c>] (arch_idle+0x294/0x3e0) from [<c000eed8>] (default_idle+0x18/0x2c)\n[<c000eed8>] (default_idle+0x18/0x2c) from [<c000f254>] (cpu_idle+0x90/0xe4)\n[<c000f254>] (cpu_idle+0x90/0xe4) from [<c057231c>] (rest_init+0x88/0xa0)\n[<c057231c>] (rest_init+0x88/0xa0) from [<c07ff890>] (start_kernel+0x3a8/0x40c)\nCode: c0704256 e12fff1e e59f2020 e5923000 (e5930000)\n\nThis is caused by the 'reserved' entries which we insert (see\n19b52abe3c5d7 - ARM: 7438/1: fill possible PMD empty section gaps)\nwhich get matched for physical address zero.\n\nResolve this by marking these reserved entries with a different flag.\n\nTested-by: Murali Nalajala <mnalajal@codeaurora.org>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/5ead701134d5384ed3576d5bb85ced0dc963bb25"},{"sha":"44bccf1ca0e2390c78f1099e9afdc49f7d9994c6","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"ARM: Use TTBR1 instead of reserved context ID\n\nOn ARMv7 CPUs that cache first level page table entries (like the\nCortex-A15), using a reserved ASID while changing the TTBR or flushing\nthe TLB is unsafe.\n\nThis is because the CPU may cache the first level entry as the result of\na speculative memory access while the reserved ASID is assigned. After\nthe process owning the page tables dies, the memory will be reallocated\nand may be written with junk values which can be interpreted as global,\nvalid PTEs by the processor. This will result in the TLB being populated\nwith bogus global entries.\n\nThis patch avoids the use of a reserved context ID in the v7 switch_mm\nand ASID rollover code by temporarily using the swapper_pg_dir pointed\nat by TTBR1, which contains only global entries that are not tagged\nwith ASIDs.\n\nReviewed-by: Frank Rowand <frank.rowand@am.sony.com>\nTested-by: Marc Zyngier <Marc.Zyngier@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\n[catalin.marinas@arm.com: add LPAE support]\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\n\nConflicts:\n\tarch/arm/mm/context.c\n\tarch/arm/mm/proc-v7-2level.S","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/44bccf1ca0e2390c78f1099e9afdc49f7d9994c6"},{"sha":"c3a6020d611e3c5dfe871e280af89812f732b824","author":{"email":"15ce75b290ebaf27c3f9fd73ab848685ed3d8261@arm.com","name":"Catalin Marinas"},"message":"ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs\n\nSince the ASIDs must be unique to an mm across all the CPUs in a system,\nthe __new_context() function needs to broadcast a context reset event to\nall the CPUs during ASID allocation if a roll-over occurred. Such IPIs\ncannot be issued with interrupts disabled and ARM had to define\n__ARCH_WANT_INTERRUPTS_ON_CTXSW.\n\nThis patch changes the check_context() function to\ncheck_and_switch_context() called from switch_mm(). In case of\nASID-capable CPUs (ARMv6 onwards), if a new ASID is needed and the\ninterrupts are disabled, it defers the __new_context() and\ncpu_switch_mm() calls to the post-lock switch hook where the interrupts\nare enabled. Setting the reserved TTBR0 was also moved to\ncheck_and_switch_context() from cpu_v7_switch_mm().\n\nReviewed-by: Will Deacon <will.deacon@arm.com>\nTested-by: Will Deacon <will.deacon@arm.com>\nReviewed-by: Frank Rowand <frank.rowand@am.sony.com>\nTested-by: Marc Zyngier <Marc.Zyngier@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\n\nConflicts:\n\tarch/arm/include/asm/thread_info.h","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/c3a6020d611e3c5dfe871e280af89812f732b824"},{"sha":"e3ede06f4eafbd13fabaa3fabdf9432b4bccd44f","author":{"email":"15ce75b290ebaf27c3f9fd73ab848685ed3d8261@arm.com","name":"Catalin Marinas"},"message":"ARM: Remove current_mm per-cpu variable\n\nThe current_mm variable was used to store the new mm between the\nswitch_mm() and switch_to() calls where an IPI to reset the context\ncould have set the wrong mm. Since the interrupts are disabled during\ncontext switch, there is no need for this variable, current->active_mm\nalready points to the current mm when interrupts are re-enabled.\n\nReviewed-by: Will Deacon <will.deacon@arm.com>\nTested-by: Will Deacon <will.deacon@arm.com>\nReviewed-by: Frank Rowand <frank.rowand@am.sony.com>\nTested-by: Marc Zyngier <Marc.Zyngier@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/e3ede06f4eafbd13fabaa3fabdf9432b4bccd44f"},{"sha":"482e09fe059f5d882e36336c5c066835cada4ee8","author":{"email":"a105fd58f578dea0be108941d4c59d15396e1855@verge.net.au","name":"Simon Horman"},"message":"ARM: 7541/1: Add ARM ERRATA 775420 workaround\n\ncommit 7253b85cc62d6ff84143d96fe6cd54f73736f4d7 upstream.\n\narm: Add ARM ERRATA 775420 workaround\n\nWorkaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum.\nIn case a date cache maintenance operation aborts with MMU exception, it\nmight cause the processor to deadlock. This workaround puts DSB before\nexecuting ISB if an abort may occur on cache maintenance.\n\nBased on work by Kouei Abe and feedback from Catalin Marinas.\n\nSigned-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>\n[ horms@verge.net.au: Changed to implementation\n  suggested by catalin.marinas@arm.com ]\nAcked-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Simon Horman <horms@verge.net.au>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\n\nConflicts:\n\tarch/arm/Kconfig","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/482e09fe059f5d882e36336c5c066835cada4ee8"},{"sha":"c6674b8c2ff656fd129dc0fdb6e623bf2c7c4ea1","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"ARM: mm: use pteval_t to represent page protection values\n\ncommit 864aa04cd02979c2c755cb28b5f4fe56039171c0 upstream.\n\nWhen updating the page protection map after calculating the user_pgprot\nvalue, the base protection map is temporarily stored in an unsigned long\ntype, causing truncation of the protection bits when LPAE is enabled.\nThis effectively means that calls to mprotect() will corrupt the upper\npage attributes, clearing the XN bit unconditionally.\n\nThis patch uses pteval_t to store the intermediate protection values,\npreserving the upper bits for 64-bit descriptors.\n\nAcked-by: Nicolas Pitre <nico@linaro.org>\nAcked-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/c6674b8c2ff656fd129dc0fdb6e623bf2c7c4ea1"},{"sha":"3905e7af05719eb1329e4f3f80963793d6d6ca5b","author":{"email":"f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","name":"Russell King"},"message":"ARM: DMA: Fix struct page iterator in dma_cache_maint() to work with sparsemem\n\ncommit 15653371c67c3fbe359ae37b720639dd4c7b42c5 upstream.\n\nSubhash Jadavani reported this partial backtrace:\n  Now consider this call stack from MMC block driver (this is on the ARMv7\n  based board):\n\n  [<c001b50c>] (v7_dma_inv_range+0x30/0x48) from [<c0017b8c>] (dma_cache_maint_page+0x1c4/0x24c)\n  [<c0017b8c>] (dma_cache_maint_page+0x1c4/0x24c) from [<c0017c28>] (___dma_page_cpu_to_dev+0x14/0x1c)\n  [<c0017c28>] (___dma_page_cpu_to_dev+0x14/0x1c) from [<c0017ff8>] (dma_map_sg+0x3c/0x114)\n\nThis is caused by incrementing the struct page pointer, and running off\nthe end of the sparsemem page array.  Fix this by incrementing by pfn\ninstead, and convert the pfn to a struct page.\n\nSuggested-by: James Bottomley <JBottomley@Parallels.com>\nTested-by: Subhash Jadavani <subhashj@codeaurora.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\n\nConflicts:\n\tarch/arm/mm/dma-mapping.c","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/3905e7af05719eb1329e4f3f80963793d6d6ca5b"},{"sha":"ea537767f46af46634d39cc0957f1dd0ee8b6127","author":{"email":"f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","name":"Russell King"},"message":"ARM: fix scheduling while atomic warning in alignment handling code\n\ncommit b255188f90e2bade1bd11a986dd1ca4861869f4d upstream.\n\nPaolo Pisati reports that IPv6 triggers this warning:\n\nBUG: scheduling while atomic: swapper/0/0/0x40000100\nModules linked in:\n[<c001b1c4>] (unwind_backtrace+0x0/0xf0) from [<c0503c5c>] (__schedule_bug+0x48/0x5c)\n[<c0503c5c>] (__schedule_bug+0x48/0x5c) from [<c0508608>] (__schedule+0x700/0x740)\n[<c0508608>] (__schedule+0x700/0x740) from [<c007007c>] (__cond_resched+0x24/0x34)\n[<c007007c>] (__cond_resched+0x24/0x34) from [<c05086dc>] (_cond_resched+0x3c/0x44)\n[<c05086dc>] (_cond_resched+0x3c/0x44) from [<c0021f6c>] (do_alignment+0x178/0x78c)\n[<c0021f6c>] (do_alignment+0x178/0x78c) from [<c00083e0>] (do_DataAbort+0x34/0x98)\n[<c00083e0>] (do_DataAbort+0x34/0x98) from [<c0509a60>] (__dabt_svc+0x40/0x60)\nException stack(0xc0763d70 to 0xc0763db8)\n3d60:                                     e97e805e e97e806e 2c000000 11000000\n3d80: ea86bb00 0000002c 00000011 e97e807e c076d2a8 e97e805e e97e806e 0000002c\n3da0: 3d000000 c0763dbc c04b98fc c02a8490 00000113 ffffffff\n[<c0509a60>] (__dabt_svc+0x40/0x60) from [<c02a8490>] (__csum_ipv6_magic+0x8/0xc8)\n\nFix this by using probe_kernel_address() stead of __get_user().\n\nReported-by: Paolo Pisati <p.pisati@gmail.com>\nTested-by: Paolo Pisati <p.pisati@gmail.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/ea537767f46af46634d39cc0957f1dd0ee8b6127"},{"sha":"cf5da291015820739875e546cd9dfa207ea7b01f","author":{"email":"f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","name":"Russell King"},"message":"ARM: Do 15e0d9e37c (ARM: pm: let platforms select cpu_suspend support) properly\n\ncommit b6c7aabd923a17af993c5a5d5d7995f0b27c000a upstream.\n\nLet's do the changes properly and fix the same problem everywhere, not\njust for one case.\n\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/cf5da291015820739875e546cd9dfa207ea7b01f"},{"sha":"bdae798154d7d62fee89b46e54bb620b5d611235","author":{"email":"4408a162970529a8d1d12342dbcbfd02c5ebf034@grapecom.com","name":"Illia Ragozin"},"message":"ARM: 7696/1: Fix kexec by setting outer_cache.inv_all for Feroceon\n\ncommit cd272d1ea71583170e95dde02c76166c7f9017e6 upstream.\n\nOn Feroceon the L2 cache becomes non-coherent with the CPU\nwhen the L1 caches are disabled. Thus the L2 needs to be invalidated\nafter both L1 caches are disabled.\n\nOn kexec before the starting the code for relocation the kernel,\nthe L1 caches are disabled in cpu_froc_fin (cpu_v7_proc_fin for Feroceon),\nbut after L2 cache is never invalidated, because inv_all is not set\nin cache-feroceon-l2.c.\nSo kernel relocation and decompression may has (and usually has) errors.\nSetting the function enables L2 invalidation and fixes the issue.\n\nSigned-off-by: Illia Ragozin <illia.ragozin@grapecom.com>\nAcked-by: Jason Cooper <jason@lakedaemon.net>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/bdae798154d7d62fee89b46e54bb620b5d611235"},{"sha":"c82aaa605b70842c0b546d3bd5a29f1141f500ed","author":{"email":"1a2f18c7887fc8d384193bb926e616097dea5b69@google.com","name":"JP Abgrall"},"message":"ARM: fault: assume no context when IRQs are disabled during data abort.\n\nBail out early if IRQs are disabled in do_page_fault or else\n  [14415.157266] BUG: sleeping function called from invalid context at arch/arm/mm/fault.c:301\n\nRussell King's idea from\n  http://comments.gmane.org/gmane.linux.ports.arm.omap/59256\n\nSigned-off-by: JP Abgrall <jpa@google.com>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/c82aaa605b70842c0b546d3bd5a29f1141f500ed"},{"sha":"54faddc84027afef3c590c1eda6532f9fe04cd9e","author":{"email":"634e8284b8d4d81897365a89590b52c490e71045@gmail.com","name":"Simon Baatz"},"message":"ARM: 7755/1: handle user space mapped pages in flush_kernel_dcache_page\n\ncommit 1bc39742aab09248169ef9d3727c9def3528b3f3 upstream.\n\nCommit f8b63c1 made flush_kernel_dcache_page a no-op assuming that\nthe pages it needs to handle are kernel mapped only.  However, for\nexample when doing direct I/O, pages with user space mappings may\noccur.\n\nThus, continue to do lazy flushing if there are no user space\nmappings.  Otherwise, flush the kernel cache lines directly.\n\nSigned-off-by: Simon Baatz <gmbnomis@gmail.com>\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/54faddc84027afef3c590c1eda6532f9fe04cd9e"},{"sha":"3bd851e0023cf7360b444fd8458b7ae35180ac6d","author":{"email":"634e8284b8d4d81897365a89590b52c490e71045@gmail.com","name":"Simon Baatz"},"message":"ARM: 7772/1: Fix missing flush_kernel_dcache_page() for noMMU\n\ncommit 63384fd0b1509acf522a8a8fcede09087eedb7df upstream.\n\nCommit 1bc3974 (ARM: 7755/1: handle user space mapped pages in\nflush_kernel_dcache_page) moved the implementation of\nflush_kernel_dcache_page() into mm/flush.c but did not implement it\non noMMU ARM.\n\nSigned-off-by: Simon Baatz <gmbnomis@gmail.com>\nAcked-by: Kevin Hilman <khilman@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/Mrcl1450/android_kernel_sony_msm8960t/commits/3bd851e0023cf7360b444fd8458b7ae35180ac6d"}]}