{"push_id":733780533,"size":7,"distinct_size":0,"ref":"refs/heads/master","head":"68fb4349e2f34ca0b79add810f0fe005cb56060a","before":"0146686c15c73f456623c47c5a0d8ae56f3fecd8","commits":[{"sha":"3061044e68f2729e0e23a0f6ac6b7ffb1cf95958","author":{"email":"3ebd7b7705322dea264eed4d56852da7cab2707b@138bc75d-0d04-0410-961f-82ee72b054a4","name":"rguenth"},"message":"2015-07-22  Richard Biener  <rguenther@suse.de>\n\n\t* genmatch.c (parser::parse_result): Properly handle\n\tmatch with result operands and conditions.\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226060 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":false,"url":"https://api.github.com/repos/gcc-mirror/gcc/commits/3061044e68f2729e0e23a0f6ac6b7ffb1cf95958"},{"sha":"bf3bbdf857a9a63b0f0bd9c5078b040b91576fd4","author":{"email":"adef43b8ad6cedc50fe01268e8c98a81625e1261@138bc75d-0d04-0410-961f-82ee72b054a4","name":"cbaylis"},"message":"2015-07-22  Charles Baylis  <charles.baylis@linaro.org>\n\n\t* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): Fix\n\ttypo in attribute.\n\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226061 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":false,"url":"https://api.github.com/repos/gcc-mirror/gcc/commits/bf3bbdf857a9a63b0f0bd9c5078b040b91576fd4"},{"sha":"ace499f698b48e5f2b23338c5a19776da46ab21d","author":{"email":"3ebd7b7705322dea264eed4d56852da7cab2707b@138bc75d-0d04-0410-961f-82ee72b054a4","name":"rguenth"},"message":"2015-07-22  Richard Biener  <rguenther@suse.de>\n\n\tPR tree-optimization/66952\n\t* tree-ssa-ifcombine.c (pass_tree_ifcombine::execute): For\n\tblocks we end up executing unconditionally reset all SSA\n\tinfo such as range and alignment.\n\t* tree-ssanames.h (reset_flow_sensitive_info): Declare.\n\t* tree-ssanames.c (reset_flow_sensitive_info): New function.\n\n\t* gcc.dg/torture/pr66952.c: New testcase.\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226062 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":false,"url":"https://api.github.com/repos/gcc-mirror/gcc/commits/ace499f698b48e5f2b23338c5a19776da46ab21d"},{"sha":"a46441d0f1b0eaab7d6c47277a819f209b53169f","author":{"email":"691496484cfb0da0184c1396328b8f907a34aa88@138bc75d-0d04-0410-961f-82ee72b054a4","name":"cltang"},"message":"2015-07-22  Chung-Lin Tang  <cltang@codesourcery.com>\n\n\tlibgcc/\n\t* config/nios2/linux-atomic.c (<asm/unistd.h>): Remove #include.\n\t(EFAULT,EBUSY,ENOSYS): Delete unused #defines.\n\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226063 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":false,"url":"https://api.github.com/repos/gcc-mirror/gcc/commits/a46441d0f1b0eaab7d6c47277a819f209b53169f"},{"sha":"18be45aa2ac43a6bbc9225fbcd3a35b9338a088b","author":{"email":"2f8b91e58710b6517650cbc5b5a1f913a635f84c@138bc75d-0d04-0410-961f-82ee72b054a4","name":"jiwang"},"message":"[AArch64] PR target/63521 Define REG_ALLOC_ORDER\n\n2015-07-22  Jiong Wang  <jiong.wang@arm.com>\n \ngcc/\n  PR target/63521\n  * config/aarch64/aarch64.h (REG_ALLOC_ORDER): Define.\n  (HONOR_REG_ALLOC_ORDER): Define.\n\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226064 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":false,"url":"https://api.github.com/repos/gcc-mirror/gcc/commits/18be45aa2ac43a6bbc9225fbcd3a35b9338a088b"},{"sha":"606d0d6e6004f841d225cd7ae8dcd5ac033b6f94","author":{"email":"416a2ca57712547f02940344125c5542fe5e134e@138bc75d-0d04-0410-961f-82ee72b054a4","name":"rts"},"message":"Add -march=interaptiv.\n\ngcc/\n\t* config/mips/mips-cpus.def (interaptiv): Define.\n\t* config/mips/mips-tables.opt: Regenerate.\n\t* config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map -march=interaptiv to\n\t-mips32r2.\n\t(BASE_DRIVER_SELF_SPECS): Likewise but map to -mdsp.\n\t* doc/invoke.texi (-march=@var{arch}): Add interaptiv.\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226065 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":false,"url":"https://api.github.com/repos/gcc-mirror/gcc/commits/606d0d6e6004f841d225cd7ae8dcd5ac033b6f94"},{"sha":"68fb4349e2f34ca0b79add810f0fe005cb56060a","author":{"email":"416a2ca57712547f02940344125c5542fe5e134e@138bc75d-0d04-0410-961f-82ee72b054a4","name":"rts"},"message":"Add scheduling for M51xx core family.\n\ngcc/\n\t* config/mips/m5100.md: New file.\n\t* config/mips/mips-cpus.def (m5100, m5101): Define.\n\t* config/mips/mips-tables.opt: Regenerate.\n\t* config/mips/mips.c (mips_rtx_cost_data): Add costs for m5100.\n\t* config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map -march=m5100 and\n\t-march=m5101 to -mips32r5.\n\t(MIPS_ARCH_FLOAT_SPEC): Map -m5101 to -msoft-float.\n\t(MIPS_ISA_NAN2008_SPEC): Map -march=m51* to -mnan=2008 if\n\t!-msoft-float.\n\t* config/mips/mips.md: Include m5100.md.\n\t(processor): Add m5100.\n\t* doc/invoke.texi (-march=@var{arch}): Add m5100, m5101.\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226066 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":false,"url":"https://api.github.com/repos/gcc-mirror/gcc/commits/68fb4349e2f34ca0b79add810f0fe005cb56060a"}]}