{"push_id":684035937,"size":1,"distinct_size":1,"ref":"refs/heads/svn_head","head":"ddd2bb7d4ac85fa247dfe4cc6b8d2aa19e905de1","before":"80ed5a254e07d65aedabbd6d85552a9bcf7270b9","commits":[{"sha":"ddd2bb7d4ac85fa247dfe4cc6b8d2aa19e905de1","author":{"email":"2a9a8d55438fbd6e3e289d70da8a330d0129db8c@ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f","name":"sbruno"},"message":"Change EM_MULTIQUEUE to a real kernconf entry and enable support for\nup to 2 rx/tx queues for the 82574.\n\nProgram the 82574 to enable 5 msix vectors, assign 1 to each rx queue,\n1 to each tx queue and 1 to the link handler.\n\nInspired by DragonFlyBSD, enable some RSS logic for handling tx queue\nhandling/processing.\n\nMove multiqueue handler functions so that they line up better in a diff\nreview to if_igb.c\n\nAlways enqueue tx work to be done in em_mq_start, if unable to acquire\nthe TX lock, then this will be processed in the background later by the\ntaskqueue.  Remove mbuf argument from em_start_mq_locked() as the work\nis always enqueued.  (stolen from igb)\n\nSetup TARC, TXDCTL and RXDCTL registers for better performance and stability\nin multiqueue and singlequeue implementations. Handle Intel errata  3 and\ngeneric multiqueue behavior with the initialization of TARC(0) and TARC(1)\n\nBind interrupt threads to cpus in order.  (stolen from igb)\n\nAdd 2 new DDB functions, one to display the queue(s) and their settings and\none to reset the adapter.  Primarily used for debugging.\n\nIn the multiqueue configuration, bump RXD and TXD ring size to max for the\nadapter (4096).  Setup an RDTR of 64 and an RADV of 128 in multiqueue configuration\nto cut down on the number of interrupts.  RADV was arbitrarily set to 2x RDTR\nand can be adjusted as needed.\n\nCleanup the display in top a bit to make it clearer where the taskqueue threads\nare running and what they should be doing.\n\nEnsure that both queues are processed by em_local_timer() by writing them both\nto the IMS register to generate soft interrupts.\n\nEnsure that an soft interrupt is generated when em_msix_link() is run so that\nany races between assertion of the link/status interrupt and a rx/tx interrupt\nare handled.\n\nDocument existing tuneables: hw.em.eee_setting, hw.em.msix, hw.em.smart_pwr_down, hw.em.sbp\n\nDocument use of hw.em.num_queues and the new kernel option EM_MULTIQUEUE\n\nThanks to Intel for their continued support of FreeBSD.\n\nReviewed by:\terj jfv hiren gnn wblock\nObtained from:\tIntel Corporation\nMFC after:\t2 weeks\nRelnotes:\tYes\nSponsored by:\tLimelight Networks\nDifferential Revision:\thttps://reviews.freebsd.org/D1994\n\n\ngit-svn-id: svn+ssh://svn.freebsd.org/base/head@283959 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f","distinct":true,"url":"https://api.github.com/repos/freebsd/freebsd/commits/ddd2bb7d4ac85fa247dfe4cc6b8d2aa19e905de1"}]}