{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/fpga-zynq/issues/6","labels_url":"https://api.github.com/repos/ucb-bar/fpga-zynq/issues/6/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/fpga-zynq/issues/6/comments","events_url":"https://api.github.com/repos/ucb-bar/fpga-zynq/issues/6/events","html_url":"https://github.com/ucb-bar/fpga-zynq/issues/6","id":105996248,"number":6,"title":"How to increase BTB entries for normal operation on FPGA ","user":{"login":"max250","id":8307740,"avatar_url":"https://avatars.githubusercontent.com/u/8307740?v=3","gravatar_id":"","url":"https://api.github.com/users/max250","html_url":"https://github.com/max250","followers_url":"https://api.github.com/users/max250/followers","following_url":"https://api.github.com/users/max250/following{/other_user}","gists_url":"https://api.github.com/users/max250/gists{/gist_id}","starred_url":"https://api.github.com/users/max250/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/max250/subscriptions","organizations_url":"https://api.github.com/users/max250/orgs","repos_url":"https://api.github.com/users/max250/repos","events_url":"https://api.github.com/users/max250/events{/privacy}","received_events_url":"https://api.github.com/users/max250/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":1,"created_at":"2015-09-11T11:55:14Z","updated_at":"2015-09-11T16:18:36Z","closed_at":null,"body":"Hi. I have a question about increasing BTB entries.\r\nI want to increase the BTB entries of rocket-chip from 62 to 254 (considering 2 RAS entries).\r\nFor this configuation, I change the value of a parameter, NBTBEntries, written in rocket-chip/src/main/scala/PublicConfigs.scala.\r\n\r\nAnd then, I generate verilog codes & a bitstream for zc706 FPGA.\r\nI'm trying to run lua benchmark using a lua interpreter on zc706 FPGA, but it shows me a error message, illegal instruction. This lua interpreter is compiled for riscv ISA, and normally running on the original rocket image for zc706 FPGA.\r\n\r\nIs there something more I did't know to change BTB entry size?"},"comment":{"url":"https://api.github.com/repos/ucb-bar/fpga-zynq/issues/comments/139589712","html_url":"https://github.com/ucb-bar/fpga-zynq/issues/6#issuecomment-139589712","issue_url":"https://api.github.com/repos/ucb-bar/fpga-zynq/issues/6","id":139589712,"user":{"login":"sbeamer","id":112733,"avatar_url":"https://avatars.githubusercontent.com/u/112733?v=3","gravatar_id":"","url":"https://api.github.com/users/sbeamer","html_url":"https://github.com/sbeamer","followers_url":"https://api.github.com/users/sbeamer/followers","following_url":"https://api.github.com/users/sbeamer/following{/other_user}","gists_url":"https://api.github.com/users/sbeamer/gists{/gist_id}","starred_url":"https://api.github.com/users/sbeamer/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sbeamer/subscriptions","organizations_url":"https://api.github.com/users/sbeamer/orgs","repos_url":"https://api.github.com/users/sbeamer/repos","events_url":"https://api.github.com/users/sbeamer/events{/privacy}","received_events_url":"https://api.github.com/users/sbeamer/received_events","type":"User","site_admin":false},"created_at":"2015-09-11T16:18:36Z","updated_at":"2015-09-11T16:18:36Z","body":"Does Vivado successfully place and route the design with that many BTB entries? If it doesn't make timing, it will issue a critical warning but still produce a bitstream. In our experience, the BTB entries are extremely resource intensive when mapped to an FPGA.\r\n\r\nDo you experience the same problem when generating your own bitstream but not changing the number of BTB entries?\r\n\r\nDo you experience the same problem when you decrease the number of BTB entries?"}}