{"push_id":588021642,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"c209ce713caf3ceb050e52860346281e1f931188","before":"6a51b5cd186d4cbdaff1dd86e7f0f4c0ad08243e","commits":[{"sha":"c209ce713caf3ceb050e52860346281e1f931188","author":{"email":"26c7ba98543a670b2b55dd4dcc201fee7464635c@gmail.com","name":"Jeff Bush"},"message":"rtl: testbench cleanup\n\n- Specify refresh interval for assertion as parameter to sim_sdram instead of\nhardcoding.\n- Remove MEM_SIZE parameter to sim_sdram. This is derived from the number of\nrows and columns\n- The memory size for the Verilator testbench (4MB) was actually too small\nfor the randomized tests\n- Use 'logic' instead of 'reg' and 'wire' in sim_sdram","distinct":true,"url":"https://api.github.com/repos/jbush001/NyuziProcessor/commits/c209ce713caf3ceb050e52860346281e1f931188"}]}