{"action":"created","issue":{"url":"https://api.github.com/repos/project64/project64/issues/157","labels_url":"https://api.github.com/repos/project64/project64/issues/157/labels{/name}","comments_url":"https://api.github.com/repos/project64/project64/issues/157/comments","events_url":"https://api.github.com/repos/project64/project64/issues/157/events","html_url":"https://github.com/project64/project64/issues/157","id":59187220,"number":157,"title":"VI half-field timing and initialization","user":{"login":"cxd4","id":1396303,"avatar_url":"https://avatars.githubusercontent.com/u/1396303?v=3","gravatar_id":"","url":"https://api.github.com/users/cxd4","html_url":"https://github.com/cxd4","followers_url":"https://api.github.com/users/cxd4/followers","following_url":"https://api.github.com/users/cxd4/following{/other_user}","gists_url":"https://api.github.com/users/cxd4/gists{/gist_id}","starred_url":"https://api.github.com/users/cxd4/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/cxd4/subscriptions","organizations_url":"https://api.github.com/users/cxd4/orgs","repos_url":"https://api.github.com/users/cxd4/repos","events_url":"https://api.github.com/users/cxd4/events{/privacy}","received_events_url":"https://api.github.com/users/cxd4/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"milestone":null,"comments":1,"created_at":"2015-02-27T04:15:32Z","updated_at":"2015-02-28T23:24:00Z","closed_at":"2015-02-28T23:24:00Z","body":"With a pixel-accurate plugin, interlaced video blitting works now with games running in 640x480 interlaced.  In some cases, there remains a particular problem with a game such as _Star Wars:  Rogue Squadron_.  If you have Counter Factor set to 1 then the problem is not really visible.  It is a much more visible problem with the default setting of CF=2, where interlaced DAC randomly fails and succeeds every other few frames.\r\n\r\nThe problem was that when I committed a fix for this (which zilmar adopted as the variable name `m_FieldSerration` within his class), I did not force the resetting of the serration status to 0 when the next interrupt is initialized.\r\n\r\nBasically the code is correct for the most part:\r\n```c\r\nvoid CMipsMemoryVM::UpdateFieldSerration (unsigned int interlaced)\r\n{\r\n\tm_FieldSerration ^= 1;\r\n\tm_FieldSerration &= interlaced;\r\n}\r\n```\r\nHowever, this could cause m_FieldSerration to start at 1 instead of 0, when it maybe should be 0 instead of 1, depending on the CPU timing and at what stage the VI interval is at when the current video interrupt began drawing the first scanline of the frame.\r\n\r\nI will look at it later to see how to equate this fix to a pj64 version."},"comment":{"url":"https://api.github.com/repos/project64/project64/issues/comments/76556670","html_url":"https://github.com/project64/project64/issues/157#issuecomment-76556670","issue_url":"https://api.github.com/repos/project64/project64/issues/157","id":76556670,"user":{"login":"cxd4","id":1396303,"avatar_url":"https://avatars.githubusercontent.com/u/1396303?v=3","gravatar_id":"","url":"https://api.github.com/users/cxd4","html_url":"https://github.com/cxd4","followers_url":"https://api.github.com/users/cxd4/followers","following_url":"https://api.github.com/users/cxd4/following{/other_user}","gists_url":"https://api.github.com/users/cxd4/gists{/gist_id}","starred_url":"https://api.github.com/users/cxd4/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/cxd4/subscriptions","organizations_url":"https://api.github.com/users/cxd4/orgs","repos_url":"https://api.github.com/users/cxd4/repos","events_url":"https://api.github.com/users/cxd4/events{/privacy}","received_events_url":"https://api.github.com/users/cxd4/received_events","type":"User","site_admin":false},"created_at":"2015-02-28T23:24:00Z","updated_at":"2015-02-28T23:24:00Z","body":"Never mind.  I thought I was getting to clear the LSB per some stage of groups of vertical interrupts, but really that was getting done on ROM initialization which was enough.\r\n\r\nThe implementation is about optimal from non-cycle-accurate standpoint.  Any issues past that need to be filed as pull requests for counter factor or VI Refresh Rate."}}