{"action":"created","issue":{"url":"https://api.github.com/repos/libopencm3/libopencm3/issues/493","labels_url":"https://api.github.com/repos/libopencm3/libopencm3/issues/493/labels{/name}","comments_url":"https://api.github.com/repos/libopencm3/libopencm3/issues/493/comments","events_url":"https://api.github.com/repos/libopencm3/libopencm3/issues/493/events","html_url":"https://github.com/libopencm3/libopencm3/issues/493","id":97579401,"number":493,"title":"STM32F3 ADC: wrong operation on ADC_SR flags","user":{"login":"fenugrec","id":10098613,"avatar_url":"https://avatars.githubusercontent.com/u/10098613?v=3","gravatar_id":"","url":"https://api.github.com/users/fenugrec","html_url":"https://github.com/fenugrec","followers_url":"https://api.github.com/users/fenugrec/followers","following_url":"https://api.github.com/users/fenugrec/following{/other_user}","gists_url":"https://api.github.com/users/fenugrec/gists{/gist_id}","starred_url":"https://api.github.com/users/fenugrec/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/fenugrec/subscriptions","organizations_url":"https://api.github.com/users/fenugrec/orgs","repos_url":"https://api.github.com/users/fenugrec/repos","events_url":"https://api.github.com/users/fenugrec/events{/privacy}","received_events_url":"https://api.github.com/users/fenugrec/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":1,"created_at":"2015-07-27T23:38:03Z","updated_at":"2015-07-28T09:43:43Z","closed_at":null,"body":"A few functions in lib/stm32/f3/adc.c  :\r\n- adc_clear_overrun_flag()\r\n- adc_eoc_after_each()\r\n- adc_eoc_after_group()\r\n\r\ndo not use the ADC_SR register properly : to clear a given flag, a 1 must be written to the appropriate bit. The current code does a read-modify-write operation (useless) and attempts to write 0 to the specified bit (no effect) !"},"comment":{"url":"https://api.github.com/repos/libopencm3/libopencm3/issues/comments/125524485","html_url":"https://github.com/libopencm3/libopencm3/issues/493#issuecomment-125524485","issue_url":"https://api.github.com/repos/libopencm3/libopencm3/issues/493","id":125524485,"user":{"login":"karlp","id":127907,"avatar_url":"https://avatars.githubusercontent.com/u/127907?v=3","gravatar_id":"","url":"https://api.github.com/users/karlp","html_url":"https://github.com/karlp","followers_url":"https://api.github.com/users/karlp/followers","following_url":"https://api.github.com/users/karlp/following{/other_user}","gists_url":"https://api.github.com/users/karlp/gists{/gist_id}","starred_url":"https://api.github.com/users/karlp/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/karlp/subscriptions","organizations_url":"https://api.github.com/users/karlp/orgs","repos_url":"https://api.github.com/users/karlp/repos","events_url":"https://api.github.com/users/karlp/events{/privacy}","received_events_url":"https://api.github.com/users/karlp/received_events","type":"User","site_admin":false},"created_at":"2015-07-28T09:43:43Z","updated_at":"2015-07-28T09:43:43Z","body":"Yup.  but it's not the ADC_SR, it's ADC_ISR :)  Also, this file is only appropriate for the f30x and f31x devices.  The f37x devices have the other adc peripheral, with an d_SR register, and rc_w0 bits, instead of r_w1 bits."}}