{"push_id":588019559,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"cc53ef7f6c381ca1ce56355b2fd992462e832ec4","before":"9596442d462afa1e89c05b2280f1e26f5507bdd2","commits":[{"sha":"2f46b697ef93a4a6524333803b4bb9e943436997","author":{"email":"3c8a3ecf20b096461059fbb8ae001c096f4fbdc5@gmail.com","name":"Lucas Russo"},"message":"modules/genrams/*: add option to force inferred FIFOs\n\nAdd generic option to force the FIFOs modules to use\nthe inferred version. This is sub-optimal as we could\njust use the inferred_(a)sync_fifo module, but the module\ninstantiation remains the same with this approach.","distinct":true,"url":"https://api.github.com/repos/lerwys/general-cores/commits/2f46b697ef93a4a6524333803b4bb9e943436997"},{"sha":"cc53ef7f6c381ca1ce56355b2fd992462e832ec4","author":{"email":"3c8a3ecf20b096461059fbb8ae001c096f4fbdc5@gmail.com","name":"Lucas Russo"},"message":"modules/genrams/*: change to appease Vivado 2014.4\n\n1: Vivado 2014.4 seems to have a buggy READ (L: inout LINE;\nVALUE: out BIT; GOOD: out BOOLEAN) procedure. Instead,\nwe can use the procedure READ (L: inout LINE; VALUE: out BIT)\nwhich does the correct thing.\n\n2: Vivado 2014.4 does not support the same RAM inference\ncode style.\n\n3: Vivado 2014.4 seems to have a problem returning \"large\"\nRAM variables to DPRAM modules, as we did before. Now,\nwe check if the file before calling the memory load function.","distinct":true,"url":"https://api.github.com/repos/lerwys/general-cores/commits/cc53ef7f6c381ca1ce56355b2fd992462e832ec4"}]}