{"push_id":584028110,"size":12,"distinct_size":12,"ref":"refs/heads/cm-12.0","head":"18406859692387d7f682a1382ae8b2673015b952","before":"6c2ad8a22f26329af1f630d3b7263a08a2507ca8","commits":[{"sha":"92e884630bd186242dc308cb0298ffc30eeaaf50","author":{"email":"1e3ed3bf048787d5836c6bf2eaa8f3a7c1b27ef4@mcafee.com","name":"David McCullough"},"message":"arm/crypto: Add optimized AES and SHA1 routines\n\nAdd assembler versions of AES and SHA1 for ARM platforms.  This has provided\nup to a 50% improvement in IPsec/TCP throughout for tunnels using AES128/SHA1.\n\nPlatform   CPU SPeed    Endian   Before (bps)   After (bps)   Improvement\n\nIXP425      533 MHz      big     11217042        15566294        ~38%\nKS8695      166 MHz     little    3828549         5795373        ~51%\n\nSigned-off-by: David McCullough <ucdevel@gmail.com>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/92e884630bd186242dc308cb0298ffc30eeaaf50"},{"sha":"78f79323b95aab4a41a0bc93940379e089a1aed2","author":{"email":"00bf0f20509cb3bd3255c624dba0f295e3c4128e@linaro.org","name":"Dave Martin"},"message":"ARM: 7626/1: arm/crypto: Make asm SHA-1 and AES code Thumb-2 compatible\n\nThis patch fixes aes-armv4.S and sha1-armv4-large.S to work\nnatively in Thumb.  This allows ARM/Thumb interworking workarounds\nto be removed.\n\nI also take the opportunity to convert some explicit assembler\ndirectives for exported functions to the standard\nENTRY()/ENDPROC().\n\nFor the code itself:\n\n  * In sha1_block_data_order, use of TEQ with sp is deprecated in\n    ARMv7 and not supported in Thumb.  For the branches back to\n    .L_00_15 and .L_40_59, the TEQ is converted to a CMP, under the\n    assumption that clobbering the C flag here will not cause\n    incorrect behaviour.\n\n    For the first branch back to .L_20_39_or_60_79 the C flag is\n    important, so sp is moved temporarily into another register so\n    that TEQ can be used for the comparison.\n\n  * In the AES code, most forms of register-indexed addressing with\n    shifts and rotates are not permitted for loads and stores in\n    Thumb, so the address calculation is done using a separate\n    instruction for the Thumb case.\n\nThe resulting code is unlikely to be optimally scheduled, but it\nshould not have a large impact given the overall size of the code.\nI haven't run any benchmarks.\n\nSigned-off-by: Dave Martin <dave.martin@linaro.org>\nTested-by: David McCullough <ucdevel@gmail.com> (ARM only)\nAcked-by: David McCullough <ucdevel@gmail.com>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/78f79323b95aab4a41a0bc93940379e089a1aed2"},{"sha":"4beaa1bbab19cd57916fea029533f70737f526d1","author":{"email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@gmail.com","name":"Ard Biesheuvel"},"message":"ARM: 7723/1: crypto: sha1-armv4-large.S: fix SP handling\n\nMake the SHA1 asm code ABI conformant by making sure all stack\naccesses occur above the stack pointer.\n\nOrigin:\nhttp://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nCc: stable@vger.kernel.org\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/4beaa1bbab19cd57916fea029533f70737f526d1"},{"sha":"d76d647d48fdfc98461dca340eae9972b79b2d38","author":{"email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org","name":"Ard Biesheuvel"},"message":"ARM: 7837/3: fix Thumb-2 bug in AES assembler code\n\nPatch 638591c enabled building the AES assembler code in Thumb2 mode.\nHowever, this code used arithmetic involving PC rather than adr{l}\ninstructions to generate PC-relative references to the lookup tables,\nand this needs to take into account the different PC offset when\nrunning in Thumb mode.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nCc: stable@vger.kernel.org\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/d76d647d48fdfc98461dca340eae9972b79b2d38"},{"sha":"23ec2292f8b54b6fd08f8ddc0142f4e3ae164bf1","author":{"email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org","name":"Ard Biesheuvel"},"message":"ARM: move AES typedefs and function prototypes to separate header\n\nPut the struct definitions for AES keys and the asm function prototypes in a\nseparate header and export the asm functions from the module.\nThis allows other drivers to use them directly.\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/23ec2292f8b54b6fd08f8ddc0142f4e3ae164bf1"},{"sha":"cdb5af882530a59eef74538cc458c4487d6ffd4d","author":{"email":"66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org","name":"Ard Biesheuvel"},"message":"ARM: add support for bit sliced AES using NEON instructions\n\nBit sliced AES gives around 45% speedup on Cortex-A15 for encryption\nand around 25% for decryption. This implementation of the AES algorithm\ndoes not rely on any lookup tables so it is believed to be invulnerable\nto cache timing attacks.\n\nThis algorithm processes up to 8 blocks in parallel in constant time. This\nmeans that it is not usable by chaining modes that are strictly sequential\nin nature, such as CBC encryption. CBC decryption, however, can benefit from\nthis implementation and runs about 25% faster. The other chaining modes\nimplemented in this module, XTS and CTR, can execute fully in parallel in\nboth directions.\n\nThe core code has been adopted from the OpenSSL project (in collaboration\nwith the original author, on cc). For ease of maintenance, this version is\nidentical to the upstream OpenSSL code, i.e., all modifications that were\nrequired to make it suitable for inclusion into the kernel have been made\nupstream. The original can be found here:\n\n    http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=6f6a6130\n\nNote to integrators:\nWhile this implementation is significantly faster than the existing table\nbased ones (generic or ARM asm), especially in CTR mode, the effects on\npower efficiency are unclear as of yet. This code does fundamentally more\nwork, by calculating values that the table based code obtains by a simple\nlookup; only by doing all of that work in a SIMD fashion, it manages to\nperform better.\n\nCc: Andy Polyakov <appro@openssl.org>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/cdb5af882530a59eef74538cc458c4487d6ffd4d"},{"sha":"addbfb1e430bc7437f661500b409bb41d5f3d429","author":{"email":"f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","name":"Russell King"},"message":"CRYPTO: Fix more AES build errors\n\nBuilding a multi-arch kernel results in:\n\narch/arm/crypto/built-in.o: In function `aesbs_xts_decrypt':\nsha1_glue.c:(.text+0x15c8): undefined reference to `bsaes_xts_decrypt'\narch/arm/crypto/built-in.o: In function `aesbs_xts_encrypt':\nsha1_glue.c:(.text+0x1664): undefined reference to `bsaes_xts_encrypt'\narch/arm/crypto/built-in.o: In function `aesbs_ctr_encrypt':\nsha1_glue.c:(.text+0x184c): undefined reference to `bsaes_ctr32_encrypt_blocks'\narch/arm/crypto/built-in.o: In function `aesbs_cbc_decrypt':\nsha1_glue.c:(.text+0x19b4): undefined reference to `bsaes_cbc_encrypt'\n\nThis code is already runtime-conditional on NEON being supported, so\nthere's no point compiling it out depending on the minimum build\narchitecture.\n\nAcked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/addbfb1e430bc7437f661500b409bb41d5f3d429"},{"sha":"1fd4a8cb19b328c3745df5d05126897ee4f0eca9","author":{"email":"52f8f9962b7f38d8269c63c0859d68147c8d10f0@redhat.com","name":"Mikulas Patocka"},"message":"crypto: arm-aes - fix encryption of unaligned data\n\nFix the same alignment bug as in arm64 - we need to pass residue\nunprocessed bytes as the last argument to blkcipher_walk_done.\n\nSigned-off-by: Mikulas Patocka <mpatocka@redhat.com>\nCc: stable@vger.kernel.org\t# 3.13+\nAcked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/1fd4a8cb19b328c3745df5d05126897ee4f0eca9"},{"sha":"b66cb99862783baaff4fc6526bdd03cda03a35f6","author":{"email":"1f0aa498f7c1bee2bd6061b97aca51d7b122cec0@iki.fi","name":"Jussi Kivilinna"},"message":"ARM: 8118/1: crypto: sha1/make use of common SHA-1 structures\n\nCommon SHA-1 structures are defined in <crypto/sha.h> for code sharing.\n\nThis patch changes SHA-1/ARM glue code to use these structures.\n\nAcked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/b66cb99862783baaff4fc6526bdd03cda03a35f6"},{"sha":"7bf9b7526dc4ddac292d916dd4eabef4442f7e9b","author":{"email":"1f0aa498f7c1bee2bd6061b97aca51d7b122cec0@iki.fi","name":"Jussi Kivilinna"},"message":"ARM: 8119/1: crypto: sha1: add ARM NEON implementation\n\nThis patch adds ARM NEON assembly implementation of SHA-1 algorithm.\n\ntcrypt benchmark results on Cortex-A8, sha1-arm-asm vs sha1-neon-asm:\n\nblock-size      bytes/update    old-vs-new\n16              16              1.04x\n64              16              1.02x\n64              64              1.05x\n256             16              1.03x\n256             64              1.04x\n256             256             1.30x\n1024            16              1.03x\n1024            256             1.36x\n1024            1024            1.52x\n2048            16              1.03x\n2048            256             1.39x\n2048            1024            1.55x\n2048            2048            1.59x\n4096            16              1.03x\n4096            256             1.40x\n4096            1024            1.57x\n4096            4096            1.62x\n8192            16              1.03x\n8192            256             1.40x\n8192            1024            1.58x\n8192            4096            1.63x\n8192            8192            1.63x\n\nChange-Id: I43f856e247de8ee60dd723626195dad825d1be66\nAcked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nTested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/7bf9b7526dc4ddac292d916dd4eabef4442f7e9b"},{"sha":"3116c05bd944800d24e5096170d07f160b2b2a06","author":{"email":"1f0aa498f7c1bee2bd6061b97aca51d7b122cec0@iki.fi","name":"Jussi Kivilinna"},"message":"ARM: 8120/1: crypto: sha512: add ARM NEON implementation\n\nThis patch adds ARM NEON assembly implementation of SHA-512 and SHA-384\nalgorithms.\n\ntcrypt benchmark results on Cortex-A8, sha512-generic vs sha512-neon-asm:\n\nblock-size      bytes/update    old-vs-new\n16              16              2.99x\n64              16              2.67x\n64              64              3.00x\n256             16              2.64x\n256             64              3.06x\n256             256             3.33x\n1024            16              2.53x\n1024            256             3.39x\n1024            1024            3.52x\n2048            16              2.50x\n2048            256             3.41x\n2048            1024            3.54x\n2048            2048            3.57x\n4096            16              2.49x\n4096            256             3.42x\n4096            1024            3.56x\n4096            4096            3.59x\n8192            16              2.48x\n8192            256             3.42x\n8192            1024            3.56x\n8192            4096            3.60x\n8192            8192            3.60x\n\nChange-Id: I8471b7baf6ca8973759c0d0cf993ba772b3edcb5\nAcked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nTested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/3116c05bd944800d24e5096170d07f160b2b2a06"},{"sha":"18406859692387d7f682a1382ae8b2673015b952","author":{"email":"d9e8e6ad6b3a58a1daaf4bda30a965bfdbe2359d@gmail.com","name":"xperiafan13-rom"},"message":"Enable many features","distinct":true,"url":"https://api.github.com/repos/Condor-Kernel/android_kernel_motorola_msm8610/commits/18406859692387d7f682a1382ae8b2673015b952"}]}