{"action":"opened","issue":{"url":"https://api.github.com/repos/cliffordwolf/yosys/issues/96","labels_url":"https://api.github.com/repos/cliffordwolf/yosys/issues/96/labels{/name}","comments_url":"https://api.github.com/repos/cliffordwolf/yosys/issues/96/comments","events_url":"https://api.github.com/repos/cliffordwolf/yosys/issues/96/events","html_url":"https://github.com/cliffordwolf/yosys/issues/96","id":113119064,"number":96,"title":"another fuzzing segfault","user":{"login":"jeremysalwen","id":450638,"avatar_url":"https://avatars.githubusercontent.com/u/450638?v=3","gravatar_id":"","url":"https://api.github.com/users/jeremysalwen","html_url":"https://github.com/jeremysalwen","followers_url":"https://api.github.com/users/jeremysalwen/followers","following_url":"https://api.github.com/users/jeremysalwen/following{/other_user}","gists_url":"https://api.github.com/users/jeremysalwen/gists{/gist_id}","starred_url":"https://api.github.com/users/jeremysalwen/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jeremysalwen/subscriptions","organizations_url":"https://api.github.com/users/jeremysalwen/orgs","repos_url":"https://api.github.com/users/jeremysalwen/repos","events_url":"https://api.github.com/users/jeremysalwen/events{/privacy}","received_events_url":"https://api.github.com/users/jeremysalwen/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":0,"created_at":"2015-10-23T23:58:55Z","updated_at":"2015-10-23T23:58:55Z","closed_at":null,"body":"yosys -S\r\n\r\n```\r\nmodule a(b);integer\r\ninout b;reg c;assign&0=0;assign 0=0;always\r\ni=0;always\r\nif(8)b=_;always\r\nif(8)b=M&0;endmodule\r\n```\r\n\r\n```\r\n Yosys 0.5+327 (git sha1 b2544cf, afl-clang 3.5.0-10 -fPIC -Os)\r\n\r\n\r\n-- Parsing `/tmp/min.v' using frontend `verilog' --\r\n\r\n1. Executing Verilog-2005 frontend.\r\nParsing Verilog input from `/tmp/min.v' to AST representation.\r\nGenerating RTLIL representation for module `\\a'.\r\nWarning: Ignoring assignment to constant bits at /tmp/min.v:2:\r\n    old assignment: 1'0 = 1'0\r\n    new assignment: { } = { }.\r\nWarning: Ignoring assignment to constant bits at /tmp/min.v:2:\r\n    old assignment: 0 = 0\r\n    new assignment: { } = { }.\r\nWarning: Identifier `\\i' is implicitly declared at /tmp/min.v:3.\r\nWarning: Identifier `\\_' is implicitly declared at /tmp/min.v:4.\r\nWarning: Identifier `\\M' is implicitly declared at /tmp/min.v:5.\r\nSuccessfully finished Verilog frontend.\r\n\r\n-- Running command `synth' --\r\n\r\n2. Executing SYNTH pass.\r\n\r\n2.1. Executing HIERARCHY pass (managing design hierarchy).\r\n\r\n2.2. Executing PROC pass (convert processes to netlists).\r\n\r\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\r\nFound and cleaned up 1 empty switch in `\\a.$proc$/tmp/min.v:4$3'.\r\nFound and cleaned up 1 empty switch in `\\a.$proc$/tmp/min.v:3$2'.\r\nCleaned up 2 empty switches.\r\n\r\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\r\nRemoved a total of 0 dead cases.\r\n\r\n2.2.3. Executing PROC_INIT pass (extract init attributes).\r\n\r\n2.2.4. Executing PROC_ARST pass (detect async resets in processes).\r\n\r\n2.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).\r\nCreating decoders for process `\\a.$proc$/tmp/min.v:4$3'.\r\n  creating decoder for signal `$2\\b[31:0]'.\r\n  creating decoder for signal `$3\\b[31:0]'.\r\nCreating decoders for process `\\a.$proc$/tmp/min.v:3$2'.\r\n  creating decoder for signal `$0\\b[31:0]'.\r\n  creating decoder for signal `$1\\b[31:0]'.\r\nCreating decoders for process `\\a.$proc$/tmp/min.v:2$1'.\r\n  creating decoder for signal `$0\\i[0:0]'.\r\n\r\n2.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).\r\nNo latch inferred for signal `\\a.\\b' from process `\\a.$proc$/tmp/min.v:4$3'.\r\nNo latch inferred for signal `\\a.\\b' from process `\\a.$proc$/tmp/min.v:3$2'.\r\nNo latch inferred for signal `\\a.\\i' from process `\\a.$proc$/tmp/min.v:2$1'.\r\n\r\n2.2.7. Executing PROC_DFF pass (convert process syncs to FFs).\r\n\r\n2.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).\r\nRemoving empty process `a.$proc$/tmp/min.v:4$3'.\r\nRemoving empty process `a.$proc$/tmp/min.v:3$2'.\r\nRemoving empty process `a.$proc$/tmp/min.v:2$1'.\r\nCleaned up 0 empty switches.\r\n\r\n2.3. Executing OPT_CLEAN pass (remove unused cells and wires).\r\nFinding unused cells or wires in module \\a..\r\n  removing unused non-port wire \\i.\r\n  removing unused non-port wire \\c.\r\n  removed 2 unused temporary wires.\r\n\r\n2.4. Executing CHECK pass (checking for obvious problems).\r\nchecking module a..\r\nWarning: Wire a.\\M is used but has no driver.\r\nfound and reported 1 problems.\r\n\r\n2.5. Executing OPT pass (performing simple optimizations).\r\n\r\n2.5.1. Executing OPT_CONST pass (perform const folding).\r\n\r\n2.5.2. Executing OPT_SHARE pass (detect identical cells).\r\nFinding identical cells in module `\\a'.\r\nRemoved a total of 0 cells.\r\n\r\n2.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\r\nRunning muxtree optimizier on module \\a..\r\n  Creating internal representation of mux trees.\r\n  No muxes found in this module.\r\nRemoved 0 multiplexer ports.\r\n\r\n2.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\r\n  Optimizing cells in module \\a.\r\nPerformed a total of 0 changes.\r\n\r\n2.5.5. Executing OPT_SHARE pass (detect identical cells).\r\nFinding identical cells in module `\\a'.\r\nRemoved a total of 0 cells.\r\n\r\n2.5.6. Executing OPT_RMDFF pass (remove dff with constant values).\r\nReplaced 0 DFF cells.\r\n\r\n2.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).\r\nFinding unused cells or wires in module \\a..\r\n\r\n2.5.8. Executing OPT_CONST pass (perform const folding).\r\n\r\n2.5.9. Finished OPT passes. (There is nothing left to do.)\r\n\r\n2.6. Executing WREDUCE pass (reducing word size of cells).\r\nRemoved top 31 bits (of 32) from port B of cell a.$and$/tmp/min.v:5$4 ($and).\r\n\r\nProgram received signal SIGSEGV, Segmentation fault.\r\n(anonymous namespace)::WreduceWorker::run_cell (this=0x7fffffffc630, cell=0x203f500)\r\n    at passes/opt/wreduce.cc:208\r\nwarning: Source file is more recent than executable.\r\n208\t\r\n(gdb) \r\n```"}}