{"push_id":894033300,"size":59,"distinct_size":59,"ref":"refs/heads/master","head":"fcb0893d8819bd6e1aecb360c49d5476b3b2ac24","before":"e89ea49c12448ba0f7909013048ca1ae7e8dd98d","commits":[{"sha":"180d5cb8e1b2fb4d9fdba85669c972de4cf6b734","author":{"email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com","name":"Sanjay Patel"},"message":"[x86] add missing maxnum/minnum tests for 256-bit vectors\n\nAlso, switch to x86-64 because once we can lower these to something\nmore reasonable, there will be less noise in the checks. And add\nAVX runs because those will be different than SSE.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254879 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/180d5cb8e1b2fb4d9fdba85669c972de4cf6b734"},{"sha":"51b079cd28aacf110bf1b53c89bca4a2b23c4d22","author":{"email":"71eab3ed3d51db0f4cf11b125aa0a655cfc1b887@gmail.com","name":"Dan Gohman"},"message":"[WebAssembly] Add some more ideas to README.txt.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254880 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/51b079cd28aacf110bf1b53c89bca4a2b23c4d22"},{"sha":"d749dbb6ecc72c57a30c3d996d6b176bc4db18e3","author":{"email":"71eab3ed3d51db0f4cf11b125aa0a655cfc1b887@gmail.com","name":"Dan Gohman"},"message":"[WebAssembly] Tighten up some testcase regular expressions.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254881 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/d749dbb6ecc72c57a30c3d996d6b176bc4db18e3"},{"sha":"4693393907a37825c48332f7dad147cb2764441a","author":{"email":"71eab3ed3d51db0f4cf11b125aa0a655cfc1b887@gmail.com","name":"Dan Gohman"},"message":"[WebAssembly] Enable folding of offsets into global variable addresses.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254882 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/4693393907a37825c48332f7dad147cb2764441a"},{"sha":"577f887f754894edf6d8093ddca72ff69f0659ec","author":{"email":"71eab3ed3d51db0f4cf11b125aa0a655cfc1b887@gmail.com","name":"Dan Gohman"},"message":"[WebAssembly] Make tableswitch's 'default' operand explicit. NFC.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254883 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/577f887f754894edf6d8093ddca72ff69f0659ec"},{"sha":"001f3417071d4d6b08cc0dcd1dc03f5f90fe7623","author":{"email":"71eab3ed3d51db0f4cf11b125aa0a655cfc1b887@gmail.com","name":"Dan Gohman"},"message":"[WebAssembly] Factor out a TypeToString function, since we need it in multiple places.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254884 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/001f3417071d4d6b08cc0dcd1dc03f5f90fe7623"},{"sha":"1ecc6c0df2f39cc3c79ebc4f23f77be7e009f9df","author":{"email":"74486463aa8344ad78208a26153a7177f8db5983@gmail.com","name":"Lang Hames"},"message":"[Orc] Rename IndirectStubsManagerBase to IndirectStubsManager.\n\nNo functional change.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254885 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/1ecc6c0df2f39cc3c79ebc4f23f77be7e009f9df"},{"sha":"3b8cbdadafcf6879c1e6544ee8dd8182e6cd4133","author":{"email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk","name":"Simon Pilgrim"},"message":"[X86][AVX] Tidied up BROADCASTPD/BROADCASTPS tests\n\nRegenerate tests using update_llc_test_checks.py\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254886 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/3b8cbdadafcf6879c1e6544ee8dd8182e6cd4133"},{"sha":"41e546b231af7f317b84d2b342125cea73a1bb46","author":{"email":"49a7359091b5b1c9431acbd80a988796c3892a23@college.harvard.edu","name":"Keno Fischer"},"message":"[Verifier] Fix !dbg validation if Scope is the Subprogram\n\nSummary:\nWe are inserting both Scope and SP into the Seen map and check whether\nit was already there in which case we skip the validation (the idea\nbeing that we already checked this Subprogram before). However,\nif (Scope == SP) as MDNodes, then inserting the Scope, will trigger\nthe Seen check causing us to incorrectly not validate this !dbg\nattachment. Fix this by not performing the SP Seen check if Scope == SP\n\nReviewers: pcc, dexonsmith, dblaikie\n\nSubscribers: dblaikie, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D14697\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254887 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/41e546b231af7f317b84d2b342125cea73a1bb46"},{"sha":"0511c3bfdd84c473ea36ae52feacd6f40d1422d0","author":{"email":"1cd424918902c1dbc16c61ea09f30b31f6c2f0e9@freebsd.org","name":"Davide Italiano"},"message":"[llvm-objdump/MachoDump] Make code much more concise.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254888 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/0511c3bfdd84c473ea36ae52feacd6f40d1422d0"},{"sha":"260f72a26498347915e351d16b642a679abf64a9","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"Add uint8_t size to LegalizeAction enum so we can use the enum type directly and remove some casts. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254893 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/260f72a26498347915e351d16b642a679abf64a9"},{"sha":"1632a3b15247d3710382f81dc1ba6b4debf7c531","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"Add uint8_t size to LegalizeTypeAction enum and use the enum type directly to remove some typecasts. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254895 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/1632a3b15247d3710382f81dc1ba6b4debf7c531"},{"sha":"01654c4941dcf2447b293500ef34ca9c299ee8f0","author":{"email":"ceadf621e01489dc9705a269a331fb3c9fbbaef3@imgtec.com","name":"Zlatko Buljan"},"message":"[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions\nDifferential Revision: http://reviews.llvm.org/D9824\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254897 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/01654c4941dcf2447b293500ef34ca9c299ee8f0"},{"sha":"0239b7553bd7dc0071475e9bf63effa983690666","author":{"email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk","name":"Simon Pilgrim"},"message":"[X86][AVX] Added tests to load+broadcast non-zero'th vector elements\n\nBaseline for an upcoming patch for PR23022\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254898 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/0239b7553bd7dc0071475e9bf63effa983690666"},{"sha":"8205637a28004f0cb652634f13a154006e187c12","author":{"email":"f0ffa6f967f90214e3dddd44a9618a10ee27acfa@arm.com","name":"Bradley Smith"},"message":"[ARM] Flag vcvt{t,b} with an f16 type specifier as part of the FP16 extension\n\nAdditionally correct the Cortex-R7 definition to allow the FP16 feature.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254900 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/8205637a28004f0cb652634f13a154006e187c12"},{"sha":"5c239f408dd6152787aac57f38ab16e5e1d0c94f","author":{"email":"2763dbfa3952a1271604c203a0b2076cfe967411@intel.com","name":"Marina Yatsina"},"message":"[X86]  Adding support for FWORD type for MS inline asm\n\nAdding support for FWORD type for MS inline asm.\n\nDifferential Revision: http://reviews.llvm.org/D15268\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254904 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/5c239f408dd6152787aac57f38ab16e5e1d0c94f"},{"sha":"fbb911506eb0aeca8a269d0fa80ac279d932b44f","author":{"email":"bcb35893aada1f4978d895e8692c1754411c1863@intel.com","name":"Asaf Badouh"},"message":"[avx512] rename gcc intrinsics to be align with gcc format\nrename the gcc intrinsics suffix : _mask ->_round\n\nDifferential Revision: http://reviews.llvm.org/D15285\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254905 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/fbb911506eb0aeca8a269d0fa80ac279d932b44f"},{"sha":"35ecd26675997eeb0954dfb0edffb4ce85cf20f1","author":{"email":"6b31706989f3cf9466bfddbf48eab0c43e646ba8@gmail.com","name":"Rafael Espindola"},"message":"Change how the linker handles the old llvm.global_ctors.\n\nNow instead of changing it to the new format and then linking, it just\nhandles the old format while copying it over.\n\nThe main differences are:\n\n* There is no rauw in the source module.\n* An old format input is always upgraded.\n\nThe first item helps with having a sane API that passes in a GV list to\nthe linker.\n\nThe second one is a small step in deprecating the old format.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254907 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/35ecd26675997eeb0954dfb0edffb4ce85cf20f1"},{"sha":"eea645e49f194c23d90a465967cee1561cc997ea","author":{"email":"bce72489011e5753569f2110bd524579066fa193@intel.com","name":"Igor Breger"},"message":"AVX-512: implement kunpck intrinsics.\n\nDifferential Revision: http://reviews.llvm.org/D14821\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254908 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/eea645e49f194c23d90a465967cee1561cc997ea"},{"sha":"b06ff9b1e1a0e4e9b3a135efd2803424db3a2abf","author":{"email":"92f0075cc843baaa8e5be141782d35ca2fb90d2d@intel.com","name":"Elena Demikhovsky"},"message":"AVX-512: Fixed masked load / store instruction selection for KNL.\n\nPatterns were missing for KNL target for <8 x i32>, <8 x float> masked load/store.\n\nThis intrinsic comes with all legal types:\n<8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 align, <8 x i1> %mask, <8 x float> %passThru),\nbut still requires lowering, because VMASKMOVPS, VMASKMOVDQU32 work with 512-bit vectors only.\n\nAll data operands should be widened to 512-bit vector.\nThe mask operand should be widened to v16i1 with zeroes.\n\nDifferential Revision: http://reviews.llvm.org/D15265\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254909 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/saxena84/llvm/commits/b06ff9b1e1a0e4e9b3a135efd2803424db3a2abf"}]}