{"push_id":732910873,"size":9,"distinct_size":9,"ref":"refs/heads/master","head":"b61ed3550beb662b2a28e966878c4e717062e8f9","before":"f82758a8762ffb1df8fafed5769dfbbd63cc216e","commits":[{"sha":"d66bc210ae483fee09580cf6fd72e246782e00b6","author":{"email":"0fd15d95d647a38d004d7ac9a3d0587bb1c98551@intel.com","name":"li feng"},"message":"Cyan: Tune charger current limit in performance states table.\n\nCharger performance states table defines charger current limit for each\np state. Modify charger current control values for SANYO battery used\nin Cyan.\n\nBUG=None\nBRANCH=None\nTEST=System is charging battery, in shell window, issue command\n\"echo 0 > /sys/class/thermal/cooling_device4/cur_state\",\n\"echo 1 > /sys/class/thermal/cooling_device4/cur_state\",\n\"echo 2 > /sys/class/thermal/cooling_device4/cur_state\",\n\"echo 3 > /sys/class/thermal/cooling_device4/cur_state\", or\n\"echo 4 > /sys/class/thermal/cooling_device4/cur_state\", will see EC\nconsole show different charging current value.\n\nChange-Id: Ie9bc78822a73de6bed338bfbcc5e9045653689dc\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 3a6162151d1f9c756a13d2afc17f6b9c18608efc\nOriginal-Change-Id: I71e8247d057e4728eedcd5e8a275b64428290d09\nOriginal-Signed-off-by: li feng <li1.feng@intel.com>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/285605\nOriginal-Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>\nOriginal-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>\nOriginal-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>\nOriginal-Tested-by: Divya Jyothi <divya.jyothi@intel.com>\nReviewed-on: http://review.coreboot.org/11004\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/d66bc210ae483fee09580cf6fd72e246782e00b6"},{"sha":"a3d36bd9693b78bc6ec2a30bef3413fa038d1a04","author":{"email":"af0622ab041e8b0f8e5819838dcc93898196e71f@chromium.org","name":"Aaron Durbin"},"message":"skylake: read out and report full width of gen_pmcon registers\n\nGEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and\nsave the full 32 bits for completeness.\n\nBUG=chrome-os-partner:42847\nBRANCH=None\nTEST=Built and booted. Noted output on terminal.\n\nChange-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0\nOriginal-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb\nOriginal-Signed-off-by: Aaron Durbin <adurbin@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/286270\nOriginal-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>\nReviewed-on: http://review.coreboot.org/11006\nReviewed-by: Aaron Durbin <adurbin@chromium.org>\nTested-by: build bot (Jenkins)\nReviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/a3d36bd9693b78bc6ec2a30bef3413fa038d1a04"},{"sha":"e94c40b254a5019e7e25be4d2399ad31f30dd271","author":{"email":"af0622ab041e8b0f8e5819838dcc93898196e71f@chromium.org","name":"Aaron Durbin"},"message":"skylake: take into account deep s3 in power failure check\n\nIf a resume from S3 is occuring one needs to take into account\ndeep S3 in order to check the proper power failure bits.\nWhen deep S3 is enabled the suspend well will be turned off.\nTherefore don't look for that bit when determining a power\nfailure.\n\nBUG=chrome-os-partner:42847\nBRANCH=None\nTEST=Suspend and resumed with deep s3 enabled and disabled.\n\nChange-Id: I2b3372a40b3d8295ee881a283b31ca7704e6764a\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: a3ba22be37d8700f4e8a4a0f5c05fb9290cfc9b2\nOriginal-Change-Id: I890f71a7cbea65f1db942fe2229a220cf0e721b0\nOriginal-Signed-off-by: Aaron Durbin <adurbin@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/286271\nOriginal-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>\nReviewed-on: http://review.coreboot.org/11007\nReviewed-by: Aaron Durbin <adurbin@chromium.org>\nTested-by: build bot (Jenkins)\nReviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/e94c40b254a5019e7e25be4d2399ad31f30dd271"},{"sha":"b993d2f1477a8e3d7c7f9c4b4e2f05773b4d098f","author":{"email":"5db40003354dc1c142019712d90bc051b3fe1c17@intel.com","name":"Lee Leahy"},"message":"Kunimitsu: Remove address from copyright notice\n\nRemove the address from the copyright notices.\n\nBRANCH=none\nBUG=None\nTEST=Build and run on Kunimitsu\n\nChange-Id: Ibe8196841d9e76c9ee3a3dbae802ecc63dc7904c\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: cc12d2658324a375d02748098f0a2f4b5d1b5615\nOriginal-Change-Id: I81a71e4ad9b8a66ad0e9a93cbeb512d90eb35906\nOriginal-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/286266\nOriginal-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>\nOriginal-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>\nOriginal-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>\nReviewed-on: http://review.coreboot.org/11008\nReviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>\nTested-by: build bot (Jenkins)","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/b993d2f1477a8e3d7c7f9c4b4e2f05773b4d098f"},{"sha":"26dd3582c843864bb1b0432a8206f8ef96b4195a","author":{"email":"5db40003354dc1c142019712d90bc051b3fe1c17@intel.com","name":"Lee Leahy"},"message":"Kunimitsu: Add comment and separate routines\n\nDocument the lid open state and separate the routines with a single\nblank line.\n\nBRANCH=none\nBUG=None\nTEST=Build and run on Kunimitsu\n\nChange-Id: I244f20c03bc7530ad8d140fba41dd97c12c079e1\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 57313253fdef3f2d3f0e16b8ab8aa91202d45b16\nOriginal-Change-Id: I7b3bd9cf16e915d214eb2de0017a8d91a934b112\nOriginal-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/286267\nOriginal-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>\nOriginal-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>\nOriginal-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>\nReviewed-on: http://review.coreboot.org/11009\nReviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>\nTested-by: build bot (Jenkins)\nReviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/26dd3582c843864bb1b0432a8206f8ef96b4195a"},{"sha":"d68c35dab4708566c760faa183eddf67bf5e2854","author":{"email":"b16ba5271bad7f77bd5da8cf4d82af7c28ca9c13@intel.com","name":"Hannah Williams"},"message":"intel/cyan: Fix crossystem \"wpsw_cur\" status\n\nThe GPIO mapping was incorrect for wpsw_cur.\nThe GPIOs for East community were in two ranges:\n 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and\n12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26]\n\nThe discontinuity was not accounted for, hence the error.\nThe original offset was 0x16 whereas it should be 0x13\n\nBUG=chrome-os-partner:42798\nBRANCH=None\nTEST=Run crossystem and test wpsw_cur entry. If screw is present,\nit should be 1 and if not present, it should be 0\n\nChange-Id: I2faea1fe1415c9d4cb23444d03c7c9d47c87e8e5\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 30ac96f606a5618e9ef12bac3f50fac433141acd\nOriginal-Change-Id: I166a7c3e15a990b507ae3c13e15ab56bee7fb917\nOriginal-Signed-off-by: Hannah Williams <hannah.williams@intel.com>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/286534\nOriginal-Reviewed-by: Shawn N <shawnn@chromium.org>\nReviewed-on: http://review.coreboot.org/11010\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/d68c35dab4708566c760faa183eddf67bf5e2854"},{"sha":"76d16715ec067abcadecbbd79b51e2711b8ec57c","author":{"email":"af0622ab041e8b0f8e5819838dcc93898196e71f@chromium.org","name":"Aaron Durbin"},"message":"skylake: add global reset cause registers to power state\n\nLog the global reset causes in the power state structure.\nWhile working in there pack the struct and use width-specific\ntypes as this struct crosses the romstate <-> ramstage boundary.\nLastly, remove hsio version as it wasn't being written or read.\n\nAfter global reset induced:\nPM1_STS:   0000\nPM1_EN:    0000\nPM1_CNT:   00000000\nTCO_STS:   0000 0000\nGPE0_STS:  00000000 00000000 00000000 00000000\nGPE0_EN:   00000000 00000000 00000000 00000000\nGEN_PMCON: d8010200 00003808\nGBLRST_CAUSE: 00000000 00040004\nPrevious Sleep State: S0\n\nBUG=None\nBRANCH=None\nTEST=Induced global reset on glados using ETR3 register and write\n     to cf9.\n\nChange-Id: I97b93de336e74c0e02199241376e74340612f0a7\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: bbc8f1d62131c0381e9d401f3281ee7a17fc2a47\nOriginal-Change-Id: I1a8e5d07c6c0e09c163effe27491d8f198823617\nOriginal-Signed-off-by: Aaron Durbin <adurbin@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/286640\nOriginal-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>\nReviewed-on: http://review.coreboot.org/11011\nReviewed-by: Aaron Durbin <adurbin@chromium.org>\nTested-by: build bot (Jenkins)\nReviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/76d16715ec067abcadecbbd79b51e2711b8ec57c"},{"sha":"f4e9eb9aba875768cbd80241e3770659bdafd643","author":{"email":"dc5f01fee5a925b1884aa0fe53687fdf8ecdfb09@intel.com","name":"Jagadish Krishnamoorthy"},"message":"mec: Correct the access mode for short payloads\n\nIf the Host Command payload is less than 4 bytes\nand is word aligned then the payload was not transferred at all.\nEC reads the old packet and CRC mismatch occurs.\n\nIn this issue, the HC command packet\nconsisting of EC_CMD_REBOOT_EC as command and EC_REBOOT_COLD\nas payload encountered the same problem as above.\nHence select byte access mode for shorter payloads.\n\nBRANCH=None\nBUG=chrome-os-partner:42396\nTEST=System should boot after\nchromeos-firmwareupdate\n\nChange-Id: I22bdb739108d31b592c20247be69c198d617d359\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 8a43d2636b1bbfbac0384e1ea5e8853a7bd87a7f\nOriginal-Change-Id: I5572093436f4f4a0fc337efa943753ab4642d8e4\nOriginal-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>\nOriginal-Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/286537\nOriginal-Reviewed-by: Shawn N <shawnn@chromium.org>\nReviewed-on: http://review.coreboot.org/11012\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/f4e9eb9aba875768cbd80241e3770659bdafd643"},{"sha":"b61ed3550beb662b2a28e966878c4e717062e8f9","author":{"email":"b16ba5271bad7f77bd5da8cf4d82af7c28ca9c13@intel.com","name":"Hannah Williams"},"message":"google/cyan: Configure EC_IN_RW signal as gpio input\n\nBUG=chrome-os-partner:42881\nBRANCH=None\nTEST=Using ctrl-d in recovery mode to switch to dev mode works.\n\nChange-Id: Iefbd11d435c4beb570875d4835a085b194d1d1e8\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: be172409792a224855b1d31621f23d1969d319b9\nOriginal-Signed-off-by: Hannah Williams <hannah.williams@intel.com>\nOriginal-Change-Id: Icf57dfc4cc258aa2cba341f40d285f8c843aace5\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/286612\nOriginal-Commit-Queue: Hannah Williams <hannah.williams@intel.com>\nOriginal-Tested-by: Hannah Williams <hannah.williams@intel.com>\nOriginal-Reviewed-by: Shawn N <shawnn@chromium.org>\nReviewed-on: http://review.coreboot.org/11013\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/b61ed3550beb662b2a28e966878c4e717062e8f9"}]}