{"push_id":577774203,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"d6c2ff3b6f833733cf5acc7d7de8b4993161c6ad","before":"7a770a216d8b61db1e39d38615b9ab1d34c1f23d","commits":[{"sha":"d6c2ff3b6f833733cf5acc7d7de8b4993161c6ad","author":{"email":"f0ffa6f967f90214e3dddd44a9618a10ee27acfa@arm.com","name":"Bradley Smith"},"message":"[ARM] Add missing M/R class CPUs\n\nAdd some of the missing M and R class Cortex CPUs, namely:\n\nCortex-M0+ (called Cortex-M0plus for GCC compatibility)\nCortex-M1\nSC000\nSC300\nCortex-R5","distinct":true,"url":"https://api.github.com/repos/chapuni/llvm-project/commits/d6c2ff3b6f833733cf5acc7d7de8b4993161c6ad"}]}