{"push_id":672047654,"size":19,"distinct_size":19,"ref":"refs/heads/master","head":"27e1259a69c49ee2dd53385f4ca4ca14b822191d","before":"9e549d36e989b14423279fb991b71728a2a4ae7c","commits":[{"sha":"9354452c39fef1ab2491da5989e6944d8bb2e16a","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Move VAX helpers to a new file\n\nKeep the IEEE and VAX floating point emulation separate.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/9354452c39fef1ab2491da5989e6944d8bb2e16a"},{"sha":"3da653fa05579579b0ba55a02ffa2aa3d466f01b","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Rename floating-point subroutines\n\n... to match the instructions, which have no leading \"f\".\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/3da653fa05579579b0ba55a02ffa2aa3d466f01b"},{"sha":"9d5a626b2c3fa98761b35b5e2ac86f7adb231002","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Forget installed round mode after MT_FPCR\n\nWhen we use QUAL_RM_D, we copy fpcr_dyn_round to float_status.\nWhen we install a new FPCR value, we update fpcr_dyn_round.\nReset the status of the cache so that we re-copy for the next\nfp insn that requires dynamic rounding.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/9d5a626b2c3fa98761b35b5e2ac86f7adb231002"},{"sha":"ba9c5de5f2d33d468a07a8794121472ea031a0b5","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Set PC correctly for floating-point exceptions\n\nPC should be one past the faulting insn.  Add better commentary\nfor the machine-check exception path.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/ba9c5de5f2d33d468a07a8794121472ea031a0b5"},{"sha":"f3d3aad4a920a4436a9f5397d7a2963aefe141a9","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Tidy FPCR representation\n\nStore the fpcr as the hardware represents it.  Convert the softfpu\nrepresentation of exceptions into the fpcr representation.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/f3d3aad4a920a4436a9f5397d7a2963aefe141a9"},{"sha":"471d4930470aee38dffe6fc4890ede3d8eaf23c4","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Set fpcr_exc_status even for disabled exceptions\n\nThe qualifiers can suppress the raising of exceptions, but real\nhardware still records that the exceptions occurred.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/471d4930470aee38dffe6fc4890ede3d8eaf23c4"},{"sha":"f6b6b7b8a775f97edab43eb672d5991f534c2e61","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Set EXC_M_SWC for exceptions from /S insns\n\nPreviously forgotten, the kernel needs the software completion bit to\nknow that it needs to emulate software completion qualified insns.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/f6b6b7b8a775f97edab43eb672d5991f534c2e61"},{"sha":"c24a8a0b6dad5a33d84f5fb846edb28c43312c71","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Raise IOV from CVTTQ\n\nFloating-point overflow is a different bit from integer overflow.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/c24a8a0b6dad5a33d84f5fb846edb28c43312c71"},{"sha":"7f2e40020cfc827f7e59670f8c400b0b9a704481","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Fix cvttq vs large integers\n\nThe range +- 2**63 - 2**64 was returning the wrong truncated\nresult.  We also incorrectly signaled overflow for -2**63.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/7f2e40020cfc827f7e59670f8c400b0b9a704481"},{"sha":"7b4dde839e86ca6c254d4e3cd28260e9d668afb5","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Fix cvttq vs inf\n\nWe should raise INV for infinities as well, not OVR+INE.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/7b4dde839e86ca6c254d4e3cd28260e9d668afb5"},{"sha":"4d1628e832dfc6ec02b0d196f6cc250aaa7bf3b3","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Fix integer overflow checking insns\n\nWe need to write the result to the destination register before\nraising any exception.  Thus inline the code for each insn, and\ncheck for any exception after we're done.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/4d1628e832dfc6ec02b0d196f6cc250aaa7bf3b3"},{"sha":"2517def6f82bec9eba9333a37f85a6f368ba52ee","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Implement WH64EN\n\nBackward compatible cache insn introduced for EV7.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/2517def6f82bec9eba9333a37f85a6f368ba52ee"},{"sha":"ed0851380c8ed181ddd6ed3542b14fcb0bca6700","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Disallow literal operand to 1C.30 to 1C.37\n\nBefore 64f45e49 we used to have literal checks for 4 of these 8 opcodes.\nConfirmed that real hardware doesn't allow them.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/ed0851380c8ed181ddd6ed3542b14fcb0bca6700"},{"sha":"b99e80694cc635aa6ed5a3716e89645a8afa261c","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Raise EXC_M_INV properly for fp inputs\n\nIgnore DNZ if software completion isn't used.  Raise INV for\ndenormals in system mode so the OS completion handler sees them.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/b99e80694cc635aa6ed5a3716e89645a8afa261c"},{"sha":"4ed069ab5334a495b49d0704795524fa34e8dbfc","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Suppress underflow from CVTTQ if DNZ\n\nI.e. respect flush_inputs_to_zero.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/4ed069ab5334a495b49d0704795524fa34e8dbfc"},{"sha":"57a808b6d7f52a62111f6070933dfca6cd88a0fd","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Raise IOV from CVTQL\n\nEven if an exception isn't taken, the status flags need updating\nand the result should be written to the destination.  Move the body\nof cvtql out of line, since we now always need a call.\n\nReported-by: Al Viro <viro@ZenIV.linux.org.uk>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/57a808b6d7f52a62111f6070933dfca6cd88a0fd"},{"sha":"8d8d324e3424bf891d41e9c7758dcc09cf3c38b9","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Rewrite helper_zapnot\n\nThis form produces significantly smaller code on x86_64.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/8d8d324e3424bf891d41e9c7758dcc09cf3c38b9"},{"sha":"32ad48abd74a997220b841e4e913edeb267aa362","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Add vector implementation for CMPBGE\n\nWhile conditionalized on SSE2, it's a \"portable\" gcc generic vector\nimplementation, which could be enabled on other hosts.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/32ad48abd74a997220b841e4e913edeb267aa362"},{"sha":"27e1259a69c49ee2dd53385f4ca4ca14b822191d","author":{"email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org","name":"Peter Maydell"},"message":"Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20150521' into staging\n\nRewrite fp exceptions\n\n# gpg: Signature made Thu May 21 18:35:52 2015 BST using RSA key ID 4DD0279B\n# gpg: Good signature from \"Richard Henderson <rth7680@gmail.com>\"\n# gpg:                 aka \"Richard Henderson <rth@redhat.com>\"\n# gpg:                 aka \"Richard Henderson <rth@twiddle.net>\"\n\n* remotes/rth/tags/pull-axp-20150521:\n  target-alpha: Add vector implementation for CMPBGE\n  target-alpha: Rewrite helper_zapnot\n  target-alpha: Raise IOV from CVTQL\n  target-alpha: Suppress underflow from CVTTQ if DNZ\n  target-alpha: Raise EXC_M_INV properly for fp inputs\n  target-alpha: Disallow literal operand to 1C.30 to 1C.37\n  target-alpha: Implement WH64EN\n  target-alpha: Fix integer overflow checking insns\n  target-alpha: Fix cvttq vs inf\n  target-alpha: Fix cvttq vs large integers\n  target-alpha: Raise IOV from CVTTQ\n  target-alpha: Set EXC_M_SWC for exceptions from /S insns\n  target-alpha: Set fpcr_exc_status even for disabled exceptions\n  target-alpha: Tidy FPCR representation\n  target-alpha: Set PC correctly for floating-point exceptions\n  target-alpha: Forget installed round mode after MT_FPCR\n  target-alpha: Rename floating-point subroutines\n  target-alpha: Move VAX helpers to a new file\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/qemu/qemu/commits/27e1259a69c49ee2dd53385f4ca4ca14b822191d"}]}