{"push_id":708066118,"size":2,"distinct_size":2,"ref":"refs/heads/socfpga-3.10-ltsi-rt","head":"272f5cbe8cadd7723bc3512d67f44e70e2339d9d","before":"1bc90b32e7d1fe054d3b94af5885169abe307705","commits":[{"sha":"2233b277e8fbd2608a67b4f4b05b52dbd57ca5de","author":{"email":"a48724738fc762a7f206428dfcaf7ede2fd84d0f@opensource.altera.com","name":"Dinh Nguyen"},"message":"FogBugz #294156: Enable watchdog on Arria10\n\nEnable watchdog timer on Arria10. On the A10, only watchdog1 is able to\ntrigger a reset reliably.\n\nAlso, there is a dependency on the bootloader to enable the boot_clk\nsource to be from the cb_intosc_hs_clk/2, versus from EOSC1. This\ncorresponds to the (SWCTRLBTCLKEN | SWCTRLBTCLKSEL) bits enabled\nin the clock manager.\n\nSigned-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>","distinct":true,"url":"https://api.github.com/repos/altera-opensource/linux-socfpga/commits/2233b277e8fbd2608a67b4f4b05b52dbd57ca5de"},{"sha":"272f5cbe8cadd7723bc3512d67f44e70e2339d9d","author":{"email":"9ab5f52a1ca0bcf4f70d6d9008e02f6134b5b8f2@sntech.de","name":"Heiko Stübner"},"message":"watchdog: dw_wdt: use clk_prepare_enable and clk_disable_unprepare\n\nThis is necessary to make the driver work with platforms using the\ncommon clock framework.\n\nSigned-off-by: Heiko Stuebner <heiko@sntech.de>\nReviewed-by: Guenter Roeck <linux@roeck-us.net>\nSigned-off-by: Wim Van Sebroeck <wim@iguana.be>\n\nConflicts:\n\tdrivers/watchdog/dw_wdt.c","distinct":true,"url":"https://api.github.com/repos/altera-opensource/linux-socfpga/commits/272f5cbe8cadd7723bc3512d67f44e70e2339d9d"}]}