{"push_id":738948727,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"8e2e33527641f1e72eaaeb15daa87f0f9160e42e","before":"2deaa2924e52f1e07102b395302e8a72d92d716c","commits":[{"sha":"8e2e33527641f1e72eaaeb15daa87f0f9160e42e","author":{"email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk","name":"Simon Pilgrim"},"message":"[InstCombine][X86][SSE] Replace sign/zero extension intrinsics with native IR\n\nNow that we are generating sane codegen for vector sext/zext nodes on SSE targets, this patch uses instcombine to replace the SSE41/AVX2 pmovsx and pmovzx intrinsics with the equivalent native IR code.\n\nDifferential Revision: http://reviews.llvm.org/D11503\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243303 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/8e2e33527641f1e72eaaeb15daa87f0f9160e42e"}]}