{"push_id":795434655,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"fde86a6ee8fb09f64dc7d5a235c628163e317a55","before":"ab7954ba251e19d9b369210a90cc888936a5f6fd","commits":[{"sha":"fde86a6ee8fb09f64dc7d5a235c628163e317a55","author":{"email":"92f0075cc843baaa8e5be141782d35ca2fb90d2d@intel.com","name":"Elena Demikhovsky"},"message":"AVX-512: shufflevector for i1 vectors <2 x i1> .. <64 x i1>\nAVX-512 does not provide an instruction that shuffles mask register. So I do the following way:\n\nmask-2-simd , shuffle simd , simd-2-mask\n\nDifferential Revision: http://reviews.llvm.org/D12727\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247876 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/fde86a6ee8fb09f64dc7d5a235c628163e317a55"}]}