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Furthermore, the cmpxchg64 code\nuses the \"memory\" constraint in the clobber list rather than identifying\nthe region of memory that is actually modified.\n\nThis patch replaces the ARMv6+ cmpxchg64 code with macros that expand to\nthe atomic64_ and local64_ variants, casting the pointer parameter to\nthe appropriate container type.\n\nCc: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/pattyboi/Rhinstone-a11/commits/08584b76d51b643ba4e68b3be1a4c674cce4a837"},{"sha":"9a50fb1ffc98ccb732c52697e2182dac8c8063ae","author":{"email":"e18650f68a5edf74f23c7e26bf0145a9d6fcf512@gmail.com","name":"Jaccon Bastiaansen"},"message":"ARM: 7720/1: ARM v6/v7 cmpxchg64 shouldn't clear upper 32 bits of the old/new value\n\nThe implementation of cmpxchg64() for the ARM v6 and v7 architecture\ncasts parameter 2 and 3 (the old and new 64bit values) to an unsigned\nlong before calling the atomic_cmpxchg64() function. This clears\nthe top 32 bits of the old and new values, resulting in the wrong\nvalues being compare-exchanged. Luckily, this only appears to be used\nfor 64-bit sched_clock, which we don't (yet) have on ARM.\n\nThis bug was introduced by commit 3e0f5a15f500 (\"ARM: 7404/1: cmpxchg64:\nuse atomic64 and local64 routines for cmpxchg64\").\n\nCc: <stable@vger.kernel.org>\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/pattyboi/Rhinstone-a11/commits/9a50fb1ffc98ccb732c52697e2182dac8c8063ae"},{"sha":"276d2858b5126dbc56628178f2b5de9aedf40681","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"ARM: 7852/1: cmpxchg: implement barrier-less cmpxchg64_local\n\nOur cmpxchg64 macros are wrappers around atomic64_cmpxchg. Whilst this is\ngreat for code re-use, there is a case for barrier-less cmpxchg where it\nis known to be safe (for example cmpxchg64_local and cmpxchg-based\nlockrefs).\n\nThis patch introduces a 64-bit cmpxchg implementation specifically\nfor the cmpxchg64_* macros, so that it can be later used by the lockref\ncode.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/pattyboi/Rhinstone-a11/commits/276d2858b5126dbc56628178f2b5de9aedf40681"},{"sha":"4688bee1b63531660620c1048c426ccef4d0b5a0","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"ARM: 7853/1: cmpxchg: implement cmpxchg64_relaxed\n\nThis patch introduces cmpxchg64_relaxed for arm, which performs a 64-bit\ncmpxchg operation without barrier semantics. cmpxchg64_local is updated\nto use the new operation.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/pattyboi/Rhinstone-a11/commits/4688bee1b63531660620c1048c426ccef4d0b5a0"},{"sha":"b9b1a44280642357beed8754ba6f9f211ea24df4","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"ARM: 7984/1: prefetch: add prefetchw invocations for barriered atomics\nAfter a bunch of benchmarking on the interaction between dmb and pldw,\nit turns out that issuing the pldw *after* the dmb instruction can\ngive modest performance gains (~3% atomic_add_return improvement on a\ndual A15).\n\nThis patch adds prefetchw invocations to our barriered atomic operations\nincluding cmpxchg, test_and_xxx and futexes.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/pattyboi/Rhinstone-a11/commits/b9b1a44280642357beed8754ba6f9f211ea24df4"},{"sha":"24b801b66077734048ad55e9c5735e87a9fe58fc","author":{"email":"10ad854332e763177fdf56644e47c43fe37a6f74@gmail.com","name":"googyanas"},"message":"asm-generic: io: don't perform swab during {in,out} string functions\n\nThe {in,out}s{b,w,l} functions are designed to operate on a stream of\nbytes and therefore should not perform any byte-swapping, regardless of\nthe CPU byte order.\n\nThis patch fixes the generic IO header so that {in,out}s{b,w,l} call the\n__raw_{read,write} functions directly rather than going via the\nendian-correcting accessors.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nCc: Mike Frysinger <vapier@gentoo.org>\nAcked-by: Arnd Bergmann <arnd@arndb.de>\nAcked-by: Ben Herrenschmidt <benh@kernel.crashing.org>\nSigned-off-by: Andrew Morton <akpm@linux-foundation.org>\nSigned-off-by: Linus Torvalds <torvalds@linux-foundation.org>","distinct":true,"url":"https://api.github.com/repos/pattyboi/Rhinstone-a11/commits/24b801b66077734048ad55e9c5735e87a9fe58fc"}]}