{"push_id":652980021,"size":4,"distinct_size":4,"ref":"refs/heads/master","head":"b171c97ee9c912df26cf0bdb8d8740a580f92955","before":"192ceb28fc50d06855871778d2d89c83f13db18b","commits":[{"sha":"2cffa543399faa91b10bbfd45c72c10173cd5beb","author":{"email":"7d9b45024251f89538e6ba62ef6a93d67d35034b@gmail.com","name":"GuneetAtwal"},"message":"  ARM: LoUIS cache maintenance API\nARM v7 architecture introduced the concept of cache levels and related\n coherency requirements. New processors like A7 and A15 embed an\n L2 unified cache controller that becomes part of the cache level\n hierarchy. Some operations in the kernel like cpu_suspend and __cpu_disable\n does not require a flush of the entire cache hierarchy to DRAM but just the\n cache levels belonging to the Level of Unification Inner Shareable (LoUIS),\n which in most of ARM v7 systems correspond to L1.\n The current cache flushing API used in cpu_suspend and __cpu_disable,\n flush_cache_all(), ends up flushing the whole cache hierarchy since for\n v7 it cleans and invalidates all cache levels up to Level of Coherency\n (LoC) which cripples system performance when used in hot paths like hotplug\n and cpuidle.\n\n Therefore a new kernel cache maintenance API must be added to the\n cpu_cache_fns structure of pointers to cope with latest ARM system requirements.\n This patch adds flush_cache_louis() to the ARM kernel cache maintenance API.\n\n This function cleans and invalidates all data cache levels up to the\n level of unification inner shareable (LoUIS) and invalidates the instruction\n cache.\n\n The cpu_cache_fns struct reflects this change by adding a new function pointer\n that is initialized by arch specific assembly files.\n\n By default, all existing ARM archs do not instantiate any cache LoUIS function\n pointer, and flush_dcache_louis just falls back to flush_kern_all.\n\n Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>\n Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>\n\nInitial adaptation for msm8974","distinct":true,"url":"https://api.github.com/repos/xperiafan13-rom/FenomenalMOD/commits/2cffa543399faa91b10bbfd45c72c10173cd5beb"},{"sha":"01435821157c56630d4073ac17c0c89fa04fd0b8","author":{"email":"c2efc80ba27cf31d4676f82b7232757b76911f7a@gmail.com","name":"Jianpeng Ma"},"message":"fs/block-dev.c:fix performance regression in O_DIRECT writes to md block devices\n\nFor regular file, write operaion used blk_plug function.But for block\nfile,write operation did not use blk_plug.\nThis patch is also for write-cache mode for block-device.\n\nSigned-off-by: Jianpeng Ma <majianpeng@gmail.com>\nReviewed-by: NeilBrown <neilb@suse.de>\nSigned-off-by: Jens Axboe <axboe@kernel.dk>","distinct":true,"url":"https://api.github.com/repos/xperiafan13-rom/FenomenalMOD/commits/01435821157c56630d4073ac17c0c89fa04fd0b8"},{"sha":"388221b683b121ebf7097b1dab8628270e4bffbd","author":{"email":"5db23874f34e45d59c69d81cd72d048d558566d7@gmail.com","name":"anarkia1976"},"message":"sched/debug: disable sched debug sysrq by default - increase performance","distinct":true,"url":"https://api.github.com/repos/xperiafan13-rom/FenomenalMOD/commits/388221b683b121ebf7097b1dab8628270e4bffbd"},{"sha":"b171c97ee9c912df26cf0bdb8d8740a580f92955","author":{"email":"4d3d37778d1543f3d64273df85edd01de7073081@gmail.com","name":"xperiafan13-rom"},"message":"Revert Intelli writeback","distinct":true,"url":"https://api.github.com/repos/xperiafan13-rom/FenomenalMOD/commits/b171c97ee9c912df26cf0bdb8d8740a580f92955"}]}