{"push_id":590524943,"size":4,"distinct_size":1,"ref":"refs/heads/hjl/mpx/wip","head":"ba30225b4d2a197357e02fa4da6e70e9abed36d3","before":"ddcb3b9b8f5c6a87bd993d1003cfde88bdb90f9b","commits":[{"sha":"24ebbbbb0ec7e8982fe02677735c46d8dc1489ec","author":{"email":"e6b730070cb8ff71eb70dcaf29e26324d883b33b@gmail.com","name":"H.J. Lu"},"message":"Import x86-64-ABI revision 242","distinct":false,"url":"https://api.github.com/repos/hjl-tools/x86-psABI/commits/24ebbbbb0ec7e8982fe02677735c46d8dc1489ec"},{"sha":"3629d4851439cf89f87b41f81abb0b1cfebad4cf","author":{"email":"e6b730070cb8ff71eb70dcaf29e26324d883b33b@gmail.com","name":"H.J. Lu"},"message":"Import x86-64-ABI revision 243","distinct":false,"url":"https://api.github.com/repos/hjl-tools/x86-psABI/commits/3629d4851439cf89f87b41f81abb0b1cfebad4cf"},{"sha":"2d7212f514109d37bff175bb3fc27c82bfd389e2","author":{"email":"e6b730070cb8ff71eb70dcaf29e26324d883b33b@gmail.com","name":"H.J. Lu"},"message":"Add .gitignore","distinct":false,"url":"https://api.github.com/repos/hjl-tools/x86-psABI/commits/2d7212f514109d37bff175bb3fc27c82bfd389e2"},{"sha":"ba30225b4d2a197357e02fa4da6e70e9abed36d3","author":{"email":"e6b730070cb8ff71eb70dcaf29e26324d883b33b@gmail.com","name":"H.J. Lu"},"message":"Updated for Intel MPX\n\nIntel MPX:\n\nhttps://software.intel.com/en-us/articles/introduction-to-intel-memory-protection-extensions\n\nintroduces 4 bound registers, which will be used for parameter passing\nin x86-64.  Bound registers are cleared by branch instructions.  Branch\ninstructions with BND prefix will keep bound register contents. This leads\nto 2 requirements to 64-bit MPX run-time:\n\n1. Dynamic linker (ld.so) should save and restore bound registers during\nsymbol lookup.\n2. Change the current 16-byte PLT0:\n\n  ff 35 08 00 00 00\tpushq  GOT+8(%rip)\n  ff 25 00 10 00\tjmpq  *GOT+16(%rip)\n  0f 1f 40 00\t\tnopl   0x0(%rax)\n\nand 16-byte PLT1:\n\n  ff 25 00 00 00 00    \tjmpq   *name@GOTPCREL(%rip)\n  68 00 00 00 00       \tpushq  $index\n  e9 00 00 00 00       \tjmpq   PLT0\n\nwhich clear bound registers, to preserve bound registers.\n\nWe use 2 new relocations:\n\nto mark branch instructions with BND prefix.\n\nWhen linker sees any R_X86_64_PC32_BND or R_X86_64_PLT32_BND relocations,\nit switches to a different PLT0:\n\n  ff 35 08 00 00 00\tpushq  GOT+8(%rip)\n  f2 ff 25 00 10 00\tbnd jmpq *GOT+16(%rip)\n  0f 1f 00\t\tnopl   (%rax)\n\nto preserve bound registers for symbol lookup and it also creates an\nexternal PLT section, .pl.bnd.  Linker will create a BND PLT1 entry\nin .plt:\n\n  68 00 00 00 00       \tpushq  $index\n  f2 e9 00 00 00 00     bnd jmpq PLT0\n  0f 1f 44 00 00        nopl 0(%rax,%rax,1)\n\nand a 8-byte BND PLT entry in .plt.bnd:\n\n  f2 ff 25 00 00 00 00  bnd jmpq *name@GOTPCREL(%rip)\n  90\t\t\tnop\n\nOtherwise, linker will create a legacy PLT1 entry in .plt:\n\n  68 00 00 00 00       \tpushq  $index\n  e9 00 00 00 00        jmpq PLT0\n  66 0f 1f 44 00 00     nopw 0(%rax,%rax,1)\n\nand a 8-byte legacy PLT in .plt.bnd:\n\n  ff 25 00 00 00 00     jmpq  *name@GOTPCREL(%rip)\n  66 90                 xchg  %ax,%ax\n\nThe initial value of the GOT entry for \"name\" will be set to the the\n\"pushq\" instruction in the corresponding entry in .plt.  Linker will\nresolve reference of symbol \"name\" to the entry in the second PLT,\n.plt.bnd.\n\nPrelink stores the offset of pushq of PLT1 (plt_base + 0x10) in GOT[1]\nand GOT[1] is stored in GOT[3].  We can undo prelink in GOT by computing\nthe corresponding the pushq offset with\n\nGOT[1] + (GOT offset - &GOT[3]) * 2\n\nSince for each entry in .plt except for PLT0 we create a 8-byte entry in\n.plt.bnd, there is extra 8-byte per PLT symbol.\n\nWe also investigated the 16-byte entry for .plt.bnd.  We compared the\n8-byte entry vs the the 16-byte entry for .plt.bnd on Sandy Bridge.\nThere are no performance differences in SPEC CPU 2000/2006 as well as\nmicro benchmarks.\n\nPros:\n\tNo change to undo prelink in dynamic linker.\n\tOnly 8-byte memory overhead for each PLT symbol.\nCons:\n\tExtra .plt.bnd section is needed.\n\tExtra 8 byte for legacy branches to PLT.\n\tGDB is unware of the new layout of .plt and .plt.bnd.","distinct":true,"url":"https://api.github.com/repos/hjl-tools/x86-psABI/commits/ba30225b4d2a197357e02fa4da6e70e9abed36d3"}]}