{"push_id":643438275,"size":8,"distinct_size":8,"ref":"refs/heads/master","head":"53282f1b696bd0d2674a0bd7b51e63040dd79fde","before":"8c20353c26b1d1163c901a82c1472de91c690a07","commits":[{"sha":"2ca0405d3d785e808b3350c45a4ecfdfcfb3c1cf","author":{"email":"9b25fdae9c4ac3050b1630b78c6479ec8c735907@google.com","name":"Chaoren Lin"},"message":"Fix build.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@235653 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/lldb/commits/2ca0405d3d785e808b3350c45a4ecfdfcfb3c1cf"},{"sha":"61cc715cf2e521fd0b6857ce5e7f2234ee3fef6f","author":{"email":"ccac2bfac288d9a152e61e5cc31e0235e83ee810@gmail.com","name":"Bruce Mitchener"},"message":"Start to share SWIG interface files between languages.\n\nSummary:\nMove scripts/Python/interface to scripts/interface so that we\ncan start making iterative improvements towards sharing the\ninterface files between multiple languages (each of which would\nhave their own directory as now).\n\nTest Plan: Build and see.\n\nReviewers: zturner, emaste, clayborg\n\nReviewed By: clayborg\n\nSubscribers: mjsabby, lldb-commits\n\nDifferential Revision: http://reviews.llvm.org/D9212\n\ngit-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@235676 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/lldb/commits/61cc715cf2e521fd0b6857ce5e7f2234ee3fef6f"},{"sha":"cae69b026a9f3b333f43ef9b1a46d6d0a2d74788","author":{"email":"5c85aece3c422b6ae8df14eb32aad1d580b7408e@gmail.com","name":"Ilia K"},"message":"Fix CMICmnMIOutOfBandRecord to accept stream-records (MI)\n\nPreviously the CMICmnMIOutOfBandRecord class worked only with async-records.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@235709 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/lldb/commits/cae69b026a9f3b333f43ef9b1a46d6d0a2d74788"},{"sha":"c7debb4c586c333c46b513d02be59944961b8cf8","author":{"email":"5c85aece3c422b6ae8df14eb32aad1d580b7408e@gmail.com","name":"Ilia K"},"message":"Fix CMICmnLLDBDebuggerHandleEvents::GetProcessStdout/GetProcessStderr to use stream-record (MI)\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@235711 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/lldb/commits/c7debb4c586c333c46b513d02be59944961b8cf8"},{"sha":"2d51b0ee6c6b4b34863d745b86963d5af9e55dee","author":{"email":"5c85aece3c422b6ae8df14eb32aad1d580b7408e@gmail.com","name":"Ilia K"},"message":"Use self.fail() in MiGdbSetShowTestCase.test_lldbmi_gdb_set_target_async_off (MI)\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@235712 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/lldb/commits/2d51b0ee6c6b4b34863d745b86963d5af9e55dee"},{"sha":"883a9d68f7be3e54cbe54d8fb3c8aa54aec0f1d3","author":{"email":"6a6e81840130faf487a180a0dbc979c5180b645e@google.com","name":"Tamas Berghammer"},"message":"Fix write register context for arm \"add<c> <Rd>, sp, #imm\"\n\nDifferential revision: http://reviews.llvm.org/D9213\n\ngit-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@235713 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/lldb/commits/883a9d68f7be3e54cbe54d8fb3c8aa54aec0f1d3"},{"sha":"d98d25d91ce8d4514bb49e4bb8317492146f3811","author":{"email":"6a6e81840130faf487a180a0dbc979c5180b645e@google.com","name":"Tamas Berghammer"},"message":"Fix order of b and blx instrction in EmulateInstructionARM\n\nIn the previous ordering some \"blx <label>\" instruction was recognised\nas \"b #imm24\" instructions causing a failure in the instruction\nemulator.\n\nDifferential revision: http://reviews.llvm.org/D9218\n\ngit-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@235714 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/lldb/commits/d98d25d91ce8d4514bb49e4bb8317492146f3811"},{"sha":"53282f1b696bd0d2674a0bd7b51e63040dd79fde","author":{"email":"6a6e81840130faf487a180a0dbc979c5180b645e@google.com","name":"Tamas Berghammer"},"message":"Fix condition detection in EmulateInstructionARM\n\nThe condition detection code is calculating the result of the condition\nbased on the first 3 bit of the condition and then negate it if the LSB\nof the condition is set. It works for the normal conditions but 0b1110\nand 0b1111 are special as both of them should evaluate to true\nindependently the value of CPSR. This CL removes the negating logic from\nthose cases.\n\nDifferential revision: http://reviews.llvm.org/D9219\n\ngit-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@235715 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/lldb/commits/53282f1b696bd0d2674a0bd7b51e63040dd79fde"}]}