{"push_id":717527007,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"d0ef9f31157a9159cf6f2c62b7e4538cbdc81642","before":"b062a9b4116823a5f9a4c0629d82cfbe443e1766","commits":[{"sha":"d0ef9f31157a9159cf6f2c62b7e4538cbdc81642","author":{"email":"2d1e643b4e210f65379b4833263e8e5bc0251356@gmail.com","name":"Alex Lorenz"},"message":"MIR Parser: Verify the implicit machine register operands.\n\nThis commit verifies that the parsed machine instructions contain the implicit\nregister operands as specified by the MCInstrDesc. Variadic and call\ninstructions aren't verified.\n\nReviewers: Duncan P. N. Exon Smith\n\nDifferential Revision: http://reviews.llvm.org/D10781\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241537 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm/commits/d0ef9f31157a9159cf6f2c62b7e4538cbdc81642"}]}