{"push_id":823175209,"size":35,"distinct_size":35,"ref":"refs/heads/cm-13.0","head":"528ace083150b78db2d272bab827af14d77fc429","before":"425f22021d2233a6663b4dfe0563471d7503d7a1","commits":[{"sha":"5c1e070a510a42839612463c5f9c3ccc24f6126e","author":{"email":"331be22c6b63ca3e0a03d408c2d906b1b02cd5f2@stressinduktion.org","name":"Hannes Frederic Sowa"},"message":"ipv6: send unsolicited neighbour advertisements to all-nodes\n\n[ Upstream commit 60713a0ca7fd6651b951cc1b4dbd528d1fc0281b ]\n\nAs documented in RFC4861 (Neighbor Discovery for IP version 6) 7.2.6.,\nunsolicited neighbour advertisements should be sent to the all-nodes\nmulticast address.\n\nSigned-off-by: Hannes Frederic Sowa <hannes@stressinduktion.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/5c1e070a510a42839612463c5f9c3ccc24f6126e"},{"sha":"4df1a02725d1a5876f4b238c2065f0de19543ab4","author":{"email":"17c2d8920621522552b392f72d8fdb4d1e866b44@suug.ch","name":"Thomas Graf"},"message":"ipv6: Don't depend on per socket memory for neighbour discovery messages\n\n[ Upstream commit 25a6e6b84fba601eff7c28d30da8ad7cfbef0d43 ]\n\nAllocating skbs when sending out neighbour discovery messages\ncurrently uses sock_alloc_send_skb() based on a per net namespace\nsocket and thus share a socket wmem buffer space.\n\nIf a netdevice is temporarily unable to transmit due to carrier\nloss or for other reasons, the queued up ndisc messages will cosnume\nall of the wmem space and will thus prevent from any more skbs to\nbe allocated even for netdevices that are able to transmit packets.\n\nThe number of neighbour discovery messages sent is very limited,\nuse of alloc_skb() bypasses the socket wmem buffer size enforcement\nwhile the manual call to skb_set_owner_w() maintains the socket\nreference needed for the IPv6 output path.\n\nThis patch has orginally been posted by Eric Dumazet in a modified\nform.\n\nSigned-off-by: Thomas Graf <tgraf@suug.ch>\nCc: Eric Dumazet <eric.dumazet@gmail.com>\nCc: Hannes Frederic Sowa <hannes@stressinduktion.org>\nCc: Stephen Warren <swarren@wwwdotorg.org>\nCc: Fabio Estevam <festevam@gmail.com>\nTested-by: Fabio Estevam <fabio.estevam@freescale.com>\nTested-by: Stephen Warren <swarren@nvidia.com>\nAcked-by: Hannes Frederic Sowa <hannes@stressinduktion.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/4df1a02725d1a5876f4b238c2065f0de19543ab4"},{"sha":"e7870673f7b71258df89629621dc3f5632265043","author":{"email":"257d7d5bef225e0a56b3375b0c1e95c6bb0ab871@modio.se","name":"D.S. Ljungmark"},"message":"ipv6: Don't reduce hop limit for an interface\n\nlocal route may have a lower hop_limit set than global routes do.\nRFC 3756, Section 4.2.7, \"Parameter Spoofing\"\n>   1.  The attacker includes a Current Hop Limit of one or another small\n>       number which the attacker knows will cause legitimate packets to\n>       be dropped before they reach their destination.\n>   As an example, one possible approach to mitigate this threat is to\n>   ignore very small hop limits.  The nodes could implement a\n>   configurable minimum hop limit, and ignore attempts to set it below\n>   said limit.\nChange-Id: I135a11ccdf03fb1f6182c8560b235b340dea06b7\nSigned-off-by: D.S. Ljungmark <ljungmark@modio.se>\nAcked-by: Hannes Frederic Sowa <hannes@stressinduktion.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/e7870673f7b71258df89629621dc3f5632265043"},{"sha":"0fe0dbdfd91aed5cc73591980b1448be02af6c23","author":{"email":"74c05afa918858348d6db8037d82fa8124870113@openvz.org","name":"Andrey Vagin"},"message":"netfilter: nf_conntrack: reserve two bytes for nf_ct_ext->len\n\n\"len\" contains sizeof(nf_ct_ext) and size of extensions. In a worst\ncase it can contain all extensions. Bellow you can find sizes for all\ntypes of extensions. Their sum is definitely bigger than 256.\n\nnf_ct_ext_types[0]->len = 24\nnf_ct_ext_types[1]->len = 32\nnf_ct_ext_types[2]->len = 24\nnf_ct_ext_types[3]->len = 32\nnf_ct_ext_types[4]->len = 152\nnf_ct_ext_types[5]->len = 2\nnf_ct_ext_types[6]->len = 16\nnf_ct_ext_types[7]->len = 8\n\nI have seen \"len\" up to 280 and my host has crashes w/o this patch.\n\nThe right way to fix this problem is reducing the size of the ecache\nextension (4) and Florian is going to do this, but these changes will\nbe quite large to be appropriate for a stable tree.\n\nChange-Id: If9efaf2b103cf304bbfa583e354cfad3faa77ac2\nFixes: 5b423f6a40a0 (netfilter: nf_conntrack: fix racy timer handling with reliable)\nCc: Pablo Neira Ayuso <pablo@netfilter.org>\nCc: Patrick McHardy <kaber@trash.net>\nCc: Jozsef Kadlecsik <kadlec@blackhole.kfki.hu>\nCc: \"David S. Miller\" <davem@davemloft.net>\nSigned-off-by: Andrey Vagin <avagin@openvz.org>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/0fe0dbdfd91aed5cc73591980b1448be02af6c23"},{"sha":"986602f230a0ed05ee3781a9c552e7a2c5330fdd","author":{"email":"1db9dd262beaa64f35756dd39531d9747b7778bb@arm.com","name":"Mark Rutland"},"message":"arm: arch_timer: add arch_counter_set_user_access\n\nSeveral bits in CNTKCTL reset to 0, including PL0VTEN. For architectures\nusing the generic timer which wish to have a fast gettimeofday vDSO\nimplementation, these bits must be set to 1 by the kernel. For\narchitectures without a vDSO, it's best to leave the bits set to 0 for\nnow to ensure that if and when support is added, it's implemented sanely\narchitecture wide.\n\nAs the bootloader might set PL0VTEN to a value that doesn't correspond\nto that which the kernel prefers, we must explicitly set it to the\narchitecture port's preferred value.\n\nThis patch adds arch_counter_set_user_access, which sets the PL0 access\npermissions to that required by the architecture. For arch/arm, this\ncurrently means disabling all userspace access.\n\nCRs-fixed: 737660\nChange-Id: I053732864abf53bb08f2f6b0ea7a8b03510592b5\nSigned-off-by: Mark Rutland <mark.rutland@arm.com>\nAcked-by: Catalin Marinas <catalin.marinas@arm.com>\nGit-commit: b2deabe3ba664a1ec47400c0ca285e951874e0cc\nGit-repo: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git\nSigned-off-by: Srinivasarao P <spathi@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/986602f230a0ed05ee3781a9c552e7a2c5330fdd"},{"sha":"00b6a80aec6e08f2ff19c24ed7c74eb2d3a150ef","author":{"email":"cf639d9ddd282b24d64bea33a00fd44856701a5f@codeaurora.org","name":"Sheetal Sahasrabudhe"},"message":"msm: perf: tracectr: Initialize cnts after hotplug\n\nDue to the mismatch between counter values saved across CPU hotplug\nby perf and tracecounter logic, incorrect values are calculated for\nfirst entry in trace buffer.\nIgnore the first entry when CPU comes out of hotplug and set previous\ncounter values in this scenario.\n\nChange-Id: Ieeeaa301d713f338f11f6e84aeb984a3708e45fc\nSigned-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/00b6a80aec6e08f2ff19c24ed7c74eb2d3a150ef"},{"sha":"40479ffbc9eb9c93835b0fe11e0767b18f6e87c3","author":{"email":"cf639d9ddd282b24d64bea33a00fd44856701a5f@codeaurora.org","name":"Sheetal Sahasrabudhe"},"message":"Perf: Reset pmu after hotplug\n\nThe counter enable bits were staying in undefined state after CPU\ncame out of hotplug when perf was not enabled.\nThis was resulting into non-zero values for counters in ftrace buffer\nwhich were not enabled by perf.\nClear the pmu when CPU comes out of hotplug and perf is not enabled.\n\nChange-Id: I31e17565ad914650a12102a5c359b363f8f2ca2a\nSigned-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/40479ffbc9eb9c93835b0fe11e0767b18f6e87c3"},{"sha":"9fd4358ac496fbcadfc9f78f3c79ac6d53b7787e","author":{"email":"1c3a980dc8904497e49ebc91fe67bb60e7f048ac@codeaurora.org","name":"Neil Leeder"},"message":"msm: perf: set filter bits for cycle counter on krait\n\nWhen programming the cycle counter on krait, the filter\nregister needs to be programmed in order to set the\nusermode/kernelmode filter options.\n\nChange-Id: Ifd5b032c9a5df4821706438d4359f84d8f614468\nSigned-off-by: Neil Leeder <nleeder@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/9fd4358ac496fbcadfc9f78f3c79ac6d53b7787e"},{"sha":"c12dce789c323f5d5f754e1020f45b22ed5e8dbc","author":{"email":"577f74ec3f2c8a155237d5ad42a70103d17f8313@codeaurora.org","name":"Vikram Mulukutla"},"message":"msm: cpufreq: Move the enabling of the CPU/L2 clocks to CPU_STARTING\n\nIt is a requirement of PLLs in MSM SoCs that the PLL power\nsupplies be enabled while the PLL is running. If the PLL is\nlocked and outputs enabled, turning off the regulator(s)\nsupplying the PLL will cause the PLL to enter an unpredictable\nstate.\n\nNow in the CPU_UP_PREPARE notifier, the CPU clocks are prepared\nand enabled, causing the source HFPLLs to also turn on. Note\nthat the CPU isn't clocked yet. It is possible that execution is\npre-empted and the CPU running the notifier enters power\ncollapse. If all other CPUs also enter power collapse, then it\nis possible for an RPM notification to go out, allowing the RPM\nto transition the Apps processor to its sleep set. This can\nresult in the HFPLL supplies being turned off while the HFPLL is\nrunning, violating the requirement mentioned above. Once the CPU\nis unclamped, the CPU is effectively unclocked, due to the HFPLL\nbeing in an unknown state.\n\nThere is a check that is enabled in the PM code's CPU_UP_PREPARE\nnotifier callback. This check ensures that the problematic RPM\nnotification cannot occur until the core that is being brought\nonline also enters power collapse. However, there is no ordering\nguarantee between that PM's hotplug notifier callback's execution\nand the cpufreq hotplug notifier callback's execution. This\nordering depends on program link order, which is unreliable.\n\nIt is necessary to ensure that once the HFPLL is enabled, the\nRPM cannot transition apps to its sleep set. Move the enabling\nof the CPU clocks to the CPU_STARTING notifier, which runs on\nthe CPU bring brought online. The CPU_STARTING notifier is\nguaranteed to run after the CPU_UP_PREPARE notifier, which\nimplies that the aforementioned do-not-notify-rpm check is\nexecuted *before* the HFPLL is enabled. Therefore even if all\ncores enter power collapse after the HFPLL is enabled, the\nHFPLL supplies are guaranteed to stay on, or the CPU clock\nis switched to the safe source and the HFPLL is turned off.\n\nCRs-Fixed: 622738\nChange-Id: I136841405806c07e755919859e649ded0c719abb\nSigned-off-by: Vikram Mulukutla <markivx@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/c12dce789c323f5d5f754e1020f45b22ed5e8dbc"},{"sha":"d263a9109ddfd7def264ec8cf609400ff6ac20c3","author":{"email":"f353a1326f7aad71d23381a3beb9470c3b31d81b@codeaurora.org","name":"Matt Wagantall"},"message":"msm: krait-l2-accessors: Remove set_get_l2_indirect_reg() API\n\nThere are no remaining users of this API, which writes to an indirect\nregister and reads back the new value. To simplify the future addition\nof RTB logging for L2 indirect CP15 accesses, remove the unused API.\n\nset_l2_indirect_reg() and get_l2_indirect_reg() can be individually\ncalled to accomplish the same purpose that set_get_l2_indirect_reg()\nserved, with a negligible performance difference for common usecases.\n\nChange-Id: If372370eabda7cf5d9eee488222a17e139609a36\nSigned-off-by: Matt Wagantall <mattw@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/d263a9109ddfd7def264ec8cf609400ff6ac20c3"},{"sha":"2d9fa12f34321b8d86761732f2c286712465aef1","author":{"email":"98996d53ce579fa37f08d0061abc5355e223c79e@codeaurora.org","name":"Abhijeet Dharmapurikar"},"message":"msm: krait-regulator: handle efuse differences\n\nScaling factor version is valid for\n- 8974 based devices when the version bits read 1\n- 8974pro based devices when the version bits read 1 or 2\n- 8084 based devices when the version bits read 0\n- 8092 based devices when the version bits read 0\n\nMoreover the three bit scaling factor data for\n- 8974 based devices starts at bit 16\n- 8974pro based devices starts at bit 16\n- 8084 based devices starts at bit 14\n- 8092 based devices starts at bit 14\n\nUpdate the code to handle these differences.\n\nCRs-Fixed: 614657\nChange-Id: I30c65026341ece9a03f88514127b563417df46ee\nSigned-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/2d9fa12f34321b8d86761732f2c286712465aef1"},{"sha":"5bcbdef5a6ada1dfe3103623d2100cee093d5910","author":{"email":"98996d53ce579fa37f08d0061abc5355e223c79e@codeaurora.org","name":"Abhijeet Dharmapurikar"},"message":"msm: krait-regulator: fix unnecessary calls to switch to LDO\n\nWhen asked to set a LDO voltage the driver rounds it up to\nthe nearest step value. However, when checking if the requested voltage\nis already set it doesn't account for the rounding up.\n\nFix this by rounding up the requested value, which avoids\nunnecessary calls to set the LDO voltage and switch to LDO.\n\nCRs-Fixed: 609879\nChange-Id: Ia5a201721e39eece49dea3f61fbc585f116d5060\nSigned-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/5bcbdef5a6ada1dfe3103623d2100cee093d5910"},{"sha":"69a8751ba073303c7de66c1f7403375952c2efd9","author":{"email":"f353a1326f7aad71d23381a3beb9470c3b31d81b@codeaurora.org","name":"Matt Wagantall"},"message":"msm: msm-krait-l2-accessors: Add RTB logging\n\nAccesses to indirect CP15 registers are important system events that\nare worth recording in the RTB logs. The logs may aid in debugging\nissues seen following operations that use these APIs, like CPU clock\nsource selection changes.\n\nChange-Id: Ibc98ba2d58ab809a9e22bab4b6fcadd1e00e5f70\nSigned-off-by: Matt Wagantall <mattw@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/69a8751ba073303c7de66c1f7403375952c2efd9"},{"sha":"2b3bf0951ebf8d9d0776b1d24da2829a8d6f2c4b","author":{"email":"44ceede879ea4f76eb31b9f0c0bb1694e9323efd@codeaurora.org","name":"Kishan Kumar"},"message":"msm: socinfo: Add support for socinfo v9\n\nA new socinfo format version 9 is added with support\nfor foundry id. Update the socinfo struct to reflect\nthis change.\n\nCRs-Fixed: 645243\nChange-Id: I8cfd961cd29fc8b7173650e22738db81a7069811\nSigned-off-by: Kishan Kumar <kishank@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/2b3bf0951ebf8d9d0776b1d24da2829a8d6f2c4b"},{"sha":"0fdf5b8f20fc44dd2112426ee7a948ec73bf7059","author":{"email":"a6f2ac994249049ef4eb96bf7d9b29c8a674c97a@codeaurora.org","name":"Sarang Joshi"},"message":"coresight: modify function names and messages\n\nModify function names and messages to be consistent with other\nmodules. Modify function names starting with control_* to\nevent_*, abort_control_tracing to event_trace_user_fault and\nabort_tracing_undef_instr to event_trace_undef_instr.\n\nChange-Id: Ic6101dc8024b8d10713c162ea93e268ba59eaf8a\nSigned-off-by: Sarang Joshi <spjoshi@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/0fdf5b8f20fc44dd2112426ee7a948ec73bf7059"},{"sha":"21b858f46b5f59ef0b8839ec57f102c37845b13d","author":{"email":"a6f2ac994249049ef4eb96bf7d9b29c8a674c97a@codeaurora.org","name":"Sarang Joshi"},"message":"coresight: make coresight event module configurable\n\nThe coresight event module helps abort tracing on user fault\nand undefined instruction exceptions. Add module parameter to\ncontrol it dynamically.\n\nChange-Id: Iecaa144b99e3786c8c8f570f989f747be12c4fdc\nSigned-off-by: Sarang Joshi <spjoshi@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/21b858f46b5f59ef0b8839ec57f102c37845b13d"},{"sha":"1864ce5293329b15ff07c1b8765d7fb06a384b7e","author":{"email":"a6f2ac994249049ef4eb96bf7d9b29c8a674c97a@codeaurora.org","name":"Sarang Joshi"},"message":"coresight: abort tracing for unhandled aborts\n\nAdd trace event to abort tracing for unhandled aborts such as\ndata abort and prefetch abort. A common event 'trace_unhandled_abort'\nis shared for all unhandled aborts.\n\nChange-Id: I6da9b30c74be48252402188a6f9a7703d21d6276\nSigned-off-by: Sarang Joshi <spjoshi@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/1864ce5293329b15ff07c1b8765d7fb06a384b7e"},{"sha":"95605d2c7104a771697ddfcb6713a2388c6efbaf","author":{"email":"a6f2ac994249049ef4eb96bf7d9b29c8a674c97a@codeaurora.org","name":"Sarang Joshi"},"message":"coresight: add device attribute for etr ddr mem size\n\nAdd device attribute to control ETR DDR memory size dynamically\nfor TMC configuration. This will help users to specify DDR trace\nbuffer size at runtime.\n\nChange-Id: Ie1edef7f972435193c96dafb8a94fd6cce97ce6c\nSigned-off-by: Sarang Joshi <spjoshi@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/95605d2c7104a771697ddfcb6713a2388c6efbaf"},{"sha":"f4c1e2c37f25acf56a5908a7637577c6ce6cb9fd","author":{"email":"1acbbdd4274e187eda89cfa6ac00592dcfca8a01@codeaurora.org","name":"Pratik Patel"},"message":"coresight: stop copying etf contents when buffer size is reached\n\nCurrently we read the TMC ETF contents and copy them to DDR until\nthe end marker is seen. If for some reason HW doesn't provide the\nend marker, this can result in memory corruption since the code\nwill end up in an infinite loop that keeps copying contents\nbeyond the TMC ETF buffer.\n\nAdd an additional check to stop copying TMC ETF contents to DDR\nwhen buffer size is reached even if end marker is not seen due to\na potential HW misbehavior.\n\nCRs-Fixed: 671604\nChange-Id: I5a6ec1231371737b8e8c368ded75f5e73ac66095\nSigned-off-by: Pratik Patel <pratikp@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/f4c1e2c37f25acf56a5908a7637577c6ce6cb9fd"},{"sha":"1264274f26b73bcb5c8551a5744042ca9da1634b","author":{"email":"a62d066fcbab732c2ebe9cb02e2d29694a514faf@codeaurora.org","name":"Shiraz Hashim"},"message":"arm: mm: fix pte allocation with CONFIG_FORCE_PAGES feature\n\nCONFIG_FORCE_PAGES introduces a debug option to mark free\npages as read only in order to trigger a fault if any code\nattempts to write to a page on the buddy list.\n\nIn order to achieve this it splits all section mappings in\nto PAGE_SIZE pages during boot. While doing this split, it\nwrongly allocates a pte (of page size) for each pmd. Linux\nhowever in armv7 short descriptor format, uses same second\nlevel pte for 2 consecutive pmds offset by the actual second\nlevel table size. Refer comments in kernel file\narch/arm/include/asm/pgtable-2level.h for details.\n\nFix this by allocating pte for a section mapped pmd while\nproviding required offset if pte already exists.\n\nChange-Id: Iadbaa5e71e4b220208a7275bf039a2a413349e42\nSigned-off-by: Shiraz Hashim <shashim@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/KaranSrivastava/kernel_xiaomi_armani_kk/commits/1264274f26b73bcb5c8551a5744042ca9da1634b"}]}