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In both cases, the register is part\nof the optional Performance Monitors extension, so, add the feature,\nand enable it for the A-class processors we support.\n\nDifferential Revision: http://reviews.llvm.org/D12425\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246555 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/37d12daa3a8046362cb044d878b65c4b3d39d9ae"},{"sha":"70b9edea776cdaf029b1341589b77cf7cfa69879","author":{"email":"1cd424918902c1dbc16c61ea09f30b31f6c2f0e9@freebsd.org","name":"Davide Italiano"},"message":"[llvm-readobj] MachO -- correctly dump section field 'Reserved3'\n\nBefore we incorrectly ignored it.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246556 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/70b9edea776cdaf029b1341589b77cf7cfa69879"},{"sha":"20264d6c67012f8097b7602c267859ed88c697ff","author":{"email":"3be48e13e9b30a63e9f424c820cc2e041758d7dd@google.com","name":"Artem Belevich"},"message":"New bitcode linker flags:\n\n-only-needed -- link in only symbols needed by destination module\n-internalize -- internalize linked symbols\n\nDifferential Revision: http://reviews.llvm.org/D12459\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246561 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/20264d6c67012f8097b7602c267859ed88c697ff"},{"sha":"e1478f87afcc458fb1b080cf187550255fc0d470","author":{"email":"8800578b51f022c8d8adb9606a8b3db4fedbdac6@hanshq.net","name":"Hans Wennborg"},"message":"DeadArgElim: don't eliminate arguments from naked functions\n\nDifferential Revision: http://reviews.llvm.org/D12534\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246564 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/e1478f87afcc458fb1b080cf187550255fc0d470"},{"sha":"374ff4e100d36629ed298192da782c7b0937bfb5","author":{"email":"ea91796269c7842d401af30276638d4aaa593379@googlemail.com","name":"Benjamin Kramer"},"message":"Remove OutputBuffer.\n\nThis was last used by the pre-MC object emitter and has been dead for\nquite a while. We have better ways to emit endian-dependent stuff now.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246571 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/374ff4e100d36629ed298192da782c7b0937bfb5"},{"sha":"0a1d37b2e85cc428a49e120ea5ac67003d0ab620","author":{"email":"4b8373d016f277527198385ba72fda0feb5da015@pcc.me.uk","name":"Peter Collingbourne"},"message":"gold-plugin: Implement parallel LTO code generation using llvm::splitCodeGen.\n\nParallelism can be enabled using a new plugin option, jobs=N, where N is\nthe number of code generation threads.\n\nDifferential Revision: http://reviews.llvm.org/D12308\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246584 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/0a1d37b2e85cc428a49e120ea5ac67003d0ab620"},{"sha":"ac515c408782decf9ce1dff2cfc736dc790bd244","author":{"email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com","name":"Sanjay Patel"},"message":"rename \"slow-unaligned-mem-under-32\" to slow-unaligned-mem-16\" (NFCI)\n\nThis is a follow-on suggested by:\nhttp://reviews.llvm.org/D12154 ( http://reviews.llvm.org/rL245729 )\nhttp://reviews.llvm.org/D10662 ( http://reviews.llvm.org/rL245075 )\n\nThis makes the attribute name match most of the existing lowering logic\nand regression test expectations.\n\nBut the current use of this attribute is inconsistent; see the FIXME\ncomment for \"allowsMisalignedMemoryAccesses()\". That change will\nresult in functional changes and should be coming soon.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246585 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/ac515c408782decf9ce1dff2cfc736dc790bd244"},{"sha":"bb93db26e41de1324339755c13223ea2cf2be8e4","author":{"email":"0d2d6fe0cb2e9ade0d2bf90d72a72b8ac034ef0e@gmx.de","name":"Nico Weber"},"message":"Make trunk release notes point to 3.7, not 3.6\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246588 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/bb93db26e41de1324339755c13223ea2cf2be8e4"},{"sha":"3d58bd6369de960bcd144318b6209ccdea200c3f","author":{"email":"fbe9e45cbb51ebd86366cc402735e3c7e9b1e064@gmail.com","name":"David Majnemer"},"message":"[MC] Add support for generating COFF CRCs\n\nCOFF sections are accompanied with an auxiliary symbol which includes a\nchecksum.  This checksum used to be filled with just zero but this seems\nto upset LINK.exe when it is processing a /INCREMENTAL link job.\nInstead, fill the CheckSum field with the JamCRC of the section\ncontents.  This matches MSVC's behavior.\n\nThis fixes PR19666.\n\nN.B.  A rather simple implementation of JamCRC is given.  It implements\na byte-wise calculation using the method given by Sarwate.  There are\nimplementations with higher throughput like slice-by-eight and making\nuse of PCLMULQDQ.  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To ameliorate this, write the current time into the\nobject file's TimeDateStamp field.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246607 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/6ad37ecd02c9ad8a75adc5d2e0139e86d135f676"},{"sha":"ec0cd29de8f010d1b65226fcc38a2e7c2b53d046","author":{"email":"004c457a2ebaecf18123fd2614baa1d571fe5234@apple.com","name":"Vedant Kumar"},"message":"[CodeGen] Fix FREM on 32-bit MSVC on x86\n\nPatch by Dylan McKay!\n\nDifferential Revision: http://reviews.llvm.org/D12099\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246615 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/ec0cd29de8f010d1b65226fcc38a2e7c2b53d046"},{"sha":"aaac94c176a050011f93d6db9324f125e8b2a58a","author":{"email":"ed664c4bb5cadd95cb7521d1190a56e280fa6954@rutgers.edu","name":"Jan Vesely"},"message":"Fix rtti flags with cmake\n\nSigned-off-by: Jan Vesely <jan.vesely@rutgers.edu>","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/aaac94c176a050011f93d6db9324f125e8b2a58a"},{"sha":"5a11e4f4c266912be16013b178b2a34ec61fcb9b","author":{"email":"ed664c4bb5cadd95cb7521d1190a56e280fa6954@rutgers.edu","name":"Jan Vesely"},"message":"DAG: Dump offending operand when legalizing ops\n\nSigned-off-by: Jan Vesely <jan.vesely@rutgers.edu>","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/5a11e4f4c266912be16013b178b2a34ec61fcb9b"},{"sha":"42d4419d2c660cc65fea9a90d72a5be570f558a9","author":{"email":"ed664c4bb5cadd95cb7521d1190a56e280fa6954@rutgers.edu","name":"Jan Vesely"},"message":"R600: Limit FMA to EG+ with FP64 hw.\n\nv2: subtarget is now a pointer\n\nfixup nested predicates\n\nSigned-off-by: Jan Vesely <jan.vesely@rutgers.edu>","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/42d4419d2c660cc65fea9a90d72a5be570f558a9"},{"sha":"fa70751d807c4bde40a238f60ab135a987b817da","author":{"email":"ed664c4bb5cadd95cb7521d1190a56e280fa6954@rutgers.edu","name":"Jan Vesely"},"message":"R600/SI: Expand i64 ADDC/ADDE on SI\n\nFixes test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll on amdgpu\n\nSigned-off-by: Jan Vesely <jan.vesely@rutgers.edu>","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/fa70751d807c4bde40a238f60ab135a987b817da"}]}