{"action":"opened","issue":{"url":"https://api.github.com/repos/aqua-project/chisel-gaia/issues/2","labels_url":"https://api.github.com/repos/aqua-project/chisel-gaia/issues/2/labels{/name}","comments_url":"https://api.github.com/repos/aqua-project/chisel-gaia/issues/2/comments","events_url":"https://api.github.com/repos/aqua-project/chisel-gaia/issues/2/events","html_url":"https://github.com/aqua-project/chisel-gaia/issues/2","id":107841392,"number":2,"title":"adjust timing between DRAM controller and last level cache","user":{"login":"MasWag","id":2862763,"avatar_url":"https://avatars.githubusercontent.com/u/2862763?v=3","gravatar_id":"","url":"https://api.github.com/users/MasWag","html_url":"https://github.com/MasWag","followers_url":"https://api.github.com/users/MasWag/followers","following_url":"https://api.github.com/users/MasWag/following{/other_user}","gists_url":"https://api.github.com/users/MasWag/gists{/gist_id}","starred_url":"https://api.github.com/users/MasWag/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/MasWag/subscriptions","organizations_url":"https://api.github.com/users/MasWag/orgs","repos_url":"https://api.github.com/users/MasWag/repos","events_url":"https://api.github.com/users/MasWag/events{/privacy}","received_events_url":"https://api.github.com/users/MasWag/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":0,"created_at":"2015-09-23T03:05:59Z","updated_at":"2015-09-23T03:05:59Z","closed_at":null,"body":"Now, the timing used in test of cache may be different from that of DRAM controller(zept is making). After zept finish writting it, cache's timing has to be adjusted."}}