{"push_id":639924402,"size":363,"distinct_size":1,"ref":"refs/heads/picoxcell/04-hwrng","head":"51c4a91d554ad8fe2b08f121c1e3ecdf1c616f4c","before":"77f92b3fc21f91e43789195ca2895942dac75863","commits":[{"sha":"1a21dfed63515faeb2cda334fbf00787b92d7771","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add binding document for Exynos5433 clock domains\n\nThis patch adds devicetree binding document for Exynos5433 SoC system clock\ncontroller.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/1a21dfed63515faeb2cda334fbf00787b92d7771"},{"sha":"96bd6224f07b8bf73e0359f15a3d7678118494e6","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks using common clock framework\n\nThis patch adds support for the CMU (Clock Management Units) of Exynos5433\nwhich is an Octa-core 64bit SoC. This patch supports necessary clocks\n(PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation\nfor Exynos5433 clock controller.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\n[s.nawrocki@samsung.com: whitespace cleanup in dt-bindings/clock/exynos5433.h]\n[                        added U suffix to first arguments of PLL_35XX_RATE()]\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/96bd6224f07b8bf73e0359f15a3d7678118494e6"},{"sha":"232364969d8a8a17c52fd9b754d15924abf98d6a","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain\n\nThis patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.\nCMU_TOP domain provides source clocks to other CMU domains.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nReviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/232364969d8a8a17c52fd9b754d15924abf98d6a"},{"sha":"d0f5de6677de4405c9acdb88db7c7cf7b9cc954e","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_PERIC domain\n\nThis patch adds missing divider/gate clocks of CMU_PERIC domain\nwhich includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use\nexternal input clock which has 'ioclk_*' prefix.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\n[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on]\nSigned-off-by: Inha Song <ideal.song@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/d0f5de6677de4405c9acdb88db7c7cf7b9cc954e"},{"sha":"56bcf3f3ea39402acff09cba9558a0d3b13fc56f","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_PERIS domain\n\nThis patch adds missing gate clocks of CMU_PERIS domain\nwhich includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.\nThe special clocks of CMU_PERIS use oscclk source clock directly.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nReviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/56bcf3f3ea39402acff09cba9558a0d3b13fc56f"},{"sha":"a29308dad5dc4695a344ed9042cae8a1b8e35267","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_G2D domain\n\nThis patch adds ths mux/divider/gate clocks of CMU_G2D domain which\nincludes G2D/MDMA IPs. The CMU_G2D requires its parent defined in\nthe CMU_TOP domain. Hence this patch adds G2D related clocks to the\nCMU_TOP domain.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nReviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/a29308dad5dc4695a344ed9042cae8a1b8e35267"},{"sha":"06d2f9dfa663367e8cc1690d7e5ce4113e5dbcc1","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_MIF domain\n\nThis patch adds the mux/divider/gate clocks of CMU_MIF domain which includes\nthe clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).\nThe CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/06d2f9dfa663367e8cc1690d7e5ce4113e5dbcc1"},{"sha":"2a1808a6c00fb6d75ebfa596add57638b9290926","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_DISP domain\n\nThis patch adds the the mux/divider/gate clocks for CMU_DISP domain\nwhich includes clocks of the display IPs (DECON/HDMI/DSIM/MIXER).\n\nAlso, CMU_DISP requires 'sclk_hdmi_spdif_disp' source clock from CMU_TOP\ndomain. This patch adds the clocks of CMU_TOP related to HDMI.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/2a1808a6c00fb6d75ebfa596add57638b9290926"},{"sha":"2e997c035945784fb8c564305c0f0ddacc374fe4","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_AUD domain\n\nThis patch adds the mux/divider/gate clocks for CMU_AUD domain which\nincludes the clocks of Cortex-A5/Bus/Audio clocks.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/2e997c035945784fb8c564305c0f0ddacc374fe4"},{"sha":"5785d6e61f27f7af4d239c1647d5a22e0dbff19b","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains\n\nThis patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains\nwhich contain global data buses clocked at up the 400MHz. These blocks\ntransfer data between DRAM and various sub-blocks. These clock domains\nalso contain global peripheral buses clocked at 67/111/200/222/266/333/400\nMHz and used for register accesses.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nReviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/5785d6e61f27f7af4d239c1647d5a22e0dbff19b"},{"sha":"4b8013554b0454984e71bc20bc31966886079e15","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain\n\nThis patch adds the mux/divider/gate clocks for CMU_FSYS domain which\ncontains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/4b8013554b0454984e71bc20bc31966886079e15"},{"sha":"453e519e5aed806c1b70bcbe92aeab39a93dda22","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_G3D domain\n\nThis patch adds the mux/divider/gate clocks for CMU_G3D domain which contains\nthe clocks for GPU(3D Graphics Engine).\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nReviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/453e519e5aed806c1b70bcbe92aeab39a93dda22"},{"sha":"2a2f33e83ddb6c0abe3d32075f795aa14e4b9476","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_GSCL domain\n\nThis patch adds the divider/gate of CMU_GSCL domain which contains\ngscaler clocks.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/2a2f33e83ddb6c0abe3d32075f795aa14e4b9476"},{"sha":"df40a13ca53e6f83ead88e718dd96654e75365ec","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_APOLLO domain\n\nThis patch adds the mux/divider/gate clocks for CMU_APOLLO domain\nwhich generates the clocks for Cortex-A53 Quad-core processsor.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\n[s.nawrocki@samsung.com: Renamed pclk_pmu_sysreg_apollo to pclk_sysreg_apollo]\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/df40a13ca53e6f83ead88e718dd96654e75365ec"},{"sha":"6c5d76d15ab6da9b30af020a44e071eb5145e1a0","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_ATLAS domain\n\nThis patch adds the mux/divider/gate clocks for CMU_ATLAS domain which\ngenerates the clocks for Cortex-A57 Quad-core processsor, L2 cache\ncontroller and CoreSight.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nReviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/6c5d76d15ab6da9b30af020a44e071eb5145e1a0"},{"sha":"b274bbfd8b4a94cb5bd6fe21801264a27dd8ec75","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_MSCL domain\n\nThis patch adds the mux/divider/gate clocks for CMU_MSCL domain which\ngenerates the clocks for M2M (Memory to Memory) scaler, JPEG IPs.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nReviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/b274bbfd8b4a94cb5bd6fe21801264a27dd8ec75"},{"sha":"9910b6bbaa7b16cd3a8a7d8be53980fa1b8183a6","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_MFC domain\n\nThis patch adds the mux/divider/gate clocks for CMU_MFC domain which\ngenerates the clocks for MFC(Multi-Format Codec) IP.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/9910b6bbaa7b16cd3a8a7d8be53980fa1b8183a6"},{"sha":"45e58aa5f751fd861d46f7b6d438c1be147458c6","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_HEVC domain\n\nThis patch adds the mux/divider/gate clocks for CMU_HEVC domain which\ngenerates the clocks for HEVC(High Efficiency Video Codec) decoder IP.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/45e58aa5f751fd861d46f7b6d438c1be147458c6"},{"sha":"8e46c4b84faf317773d5a4ec6d807ceae2d0eb41","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_ISP domain\n\nThis patch adds the mux/divider/gate clocks for CMU_ISP domain which\ngenerates the clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/8e46c4b84faf317773d5a4ec6d807ceae2d0eb41"},{"sha":"6958f22f39f9292f6e871b4383a11f183c1271ed","author":{"email":"42eed19c0f56a8d487deac90c6d19d6364b7ba73@samsung.com","name":"Chanwoo Choi"},"message":"clk: samsung: exynos5433: Add clocks for CMU_CAM0 domain\n\nThis patch adds the mux/divider/gate clocks for CMU_CAM0 domain which\ngenerates the clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.\n\nSigned-off-by: Chanwoo Choi <cw00.choi@samsung.com>\nAcked-by: Inki Dae <inki.dae@samsung.com>\nSigned-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/6958f22f39f9292f6e871b4383a11f183c1271ed"}]}