{"push_id":658827722,"size":38,"distinct_size":38,"ref":"refs/heads/pureCM-smdk4412-N710x-CM11","head":"c5672f1ac55d41a2d54defaf22bc6b11be88398e","before":"e2e67f69c2b447fda869190b5ef22394cf8cf0f5","commits":[{"sha":"d197a3603d96ec5cfc2069c05a8062fd8b1596b8","author":{"email":"25b579819dea484f65b5a9421e032e9e72afca96@gmail.com","name":"psndna88"},"message":"Revert \"Implement kexec-hardboot\"","distinct":true,"url":"https://api.github.com/repos/psndna88/AGNi-pureCM/commits/d197a3603d96ec5cfc2069c05a8062fd8b1596b8"},{"sha":"4ec9edd3f24ff2bf7c46c46e9dcd673e1503c02d","author":{"email":"25b579819dea484f65b5a9421e032e9e72afca96@gmail.com","name":"psndna88"},"message":"arm/crypto: Add optimized AES and SHA1 routines\n\nAdd assembler versions of AES and SHA1 for ARM platforms.  This has provided\nup to a 50% improvement in IPsec/TCP throughout for tunnels using AES128/SHA1.\n\nPlatform   CPU SPeed    Endian   Before (bps)   After (bps)   Improvement\n\nIXP425      533 MHz      big     11217042        15566294        ~38%\nKS8695      166 MHz     little    3828549         5795373        ~51%\n\nSigned-off-by: David McCullough <ucdevel@gmail.com>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>\n\nARM: 7626/1: arm/crypto: Make asm SHA-1 and AES code Thumb-2 compatible\n\nThis patch fixes aes-armv4.S and sha1-armv4-large.S to work\nnatively in Thumb.  This allows ARM/Thumb interworking workarounds\nto be removed.\n\nI also take the opportunity to convert some explicit assembler\ndirectives for exported functions to the standard\nENTRY()/ENDPROC().\n\nFor the code itself:\n\n  * In sha1_block_data_order, use of TEQ with sp is deprecated in\n    ARMv7 and not supported in Thumb.  For the branches back to\n    .L_00_15 and .L_40_59, the TEQ is converted to a CMP, under the\n    assumption that clobbering the C flag here will not cause\n    incorrect behaviour.\n\n    For the first branch back to .L_20_39_or_60_79 the C flag is\n    important, so sp is moved temporarily into another register so\n    that TEQ can be used for the comparison.\n\n  * In the AES code, most forms of register-indexed addressing with\n    shifts and rotates are not permitted for loads and stores in\n    Thumb, so the address calculation is done using a separate\n    instruction for the Thumb case.\n\nThe resulting code is unlikely to be optimally scheduled, but it\nshould not have a large impact given the overall size of the code.\nI haven't run any benchmarks.\n\nSigned-off-by: Dave Martin <dave.martin@linaro.org>\nTested-by: David McCullough <ucdevel@gmail.com> (ARM only)\nAcked-by: David McCullough <ucdevel@gmail.com>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nARM: 7723/1: crypto: sha1-armv4-large.S: fix SP handling\n\nMake the SHA1 asm code ABI conformant by making sure all stack\naccesses occur above the stack pointer.\n\nOrigin:\nhttp://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nCc: stable@vger.kernel.org\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nARM: 7837/3: fix Thumb-2 bug in AES assembler code\n\ncommit 40190c85f427dcfdbab5dbef4ffd2510d649da1f upstream.\n\nPatch 638591c enabled building the AES assembler code in Thumb2 mode.\nHowever, this code used arithmetic involving PC rather than adr{l}\ninstructions to generate PC-relative references to the lookup tables,\nand this needs to take into account the different PC offset when\nrunning in Thumb mode.\n\nChange-Id: I0d036eaa94dabefa0a025d522f415c663d00ae9f\nSigned-off-by: Ard Biesheuvel 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