{"push_id":787734150,"size":60,"distinct_size":60,"ref":"refs/heads/11.0","head":"271290f0774e123f221d6415e4b158e4d4b958cc","before":"ab94875352c47d3815d78166ee9826af6b17b143","commits":[{"sha":"3d58fea2e39e406ae0a4183317170451813f7794","author":{"email":"feea5431f8695a3af7470d472cb16ac8e02bab01@gmail.com","name":"Glenn Kennard"},"message":"r600g: Fix assert in tgsi_cmp\n\nFixes https://bugs.freedesktop.org/show_bug.cgi?id=91726\n\nSigned-off-by: Glenn Kennard <glenn.kennard@gmail.com>\nCc: \"11.0\" <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Dave Airlie <airlied@gmail.com>\n(cherry picked from commit 50932268aad0cc21511f370793e77c76e038bd06)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/3d58fea2e39e406ae0a4183317170451813f7794"},{"sha":"2ef343432828f563d793908af6e1b0401d6cba5a","author":{"email":"822ec91a7ef82248fd36162ca8ac3283eba70848@linux.intel.com","name":"Neil Roberts"},"message":"i965: Swap the order of the vertex ID and edge flag attributes\n\nThe edge flag data on Gen6+ is passed through the fixed function hardware as\nan extra attribute. According to the PRM it must be the last valid\nVERTEX_ELEMENT structure. However if the vertex ID is also used then another\nextra element is added to source the VID. This made it so the vertex ID is in\nthe wrong register in the vertex shader and the edge attribute is no longer in\nthe last element.\n\nv2: Also implement for BDW+\n\nv3 [by Ben]: Remove 10.5 tag. Too late.\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84677\nCc: <mesa-stable@lists.freedesktop.org>\nReviewed-by: Kristian Høgsberg <krh@bitplanet.net>\nSigned-off-by: Ben Widawsky <ben@bwidawsk.net>\nTested-by: Ben Widawsky <ben@bwidawsk.net>\nTested-by: Mark Janes <mark.a.janes@intel.com>\n(cherry picked from commit fb02b4ec482762ccf2a9fedf24fe6f50787932a9)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/2ef343432828f563d793908af6e1b0401d6cba5a"},{"sha":"aab6075613ec078257cc7008e40319f844d2ba9c","author":{"email":"822ec91a7ef82248fd36162ca8ac3283eba70848@linux.intel.com","name":"Neil Roberts"},"message":"i965/bdw: Fix 3DSTATE_VF_INSTANCING when the edge flag is used\n\nWhen the edge flag element is enabled then the elements are slightly\nreordered so that the edge flag is always the last one. This was\nconfusing the code to upload the 3DSTATE_VF_INSTANCING state because\nthat is uploaded with a separate loop which has an instruction for\neach element. The indices used in these instructions weren't taking\ninto account the reordering so the state would be incorrect.\n\nv2: Use nr_elements instead of brw->vb.nr_enabled so that it will cope\n    when gl_VertexID is used.\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91292\nCc: <mesa-stable@lists.freedesktop.org>\nReviewed-by: Ben Widawsky <ben@bwidawsk.net>\nSigned-off-by: Ben Widawsky <ben@bwidawsk.net>\nTested-by: Mark Janes <mark.a.janes@intel.com>\n(cherry picked from commit 3a1ab2348050fd32f41553b9febfd9972b5761aa)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/aab6075613ec078257cc7008e40319f844d2ba9c"},{"sha":"bf84c85130d7b9160f62ce8b54e33d5228531217","author":{"email":"bcbbb7aa705ec3a5fc5824c01a845186c3d62fca@alum.mit.edu","name":"Ilia Mirkin"},"message":"nv50,nvc0: disable depth bounds test on blit\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nCc: \"11.0\" <mesa-stable@lists.freedesktop.org>\n(cherry picked from commit abbf05cfc2bea0787bcf710ef984d73ee8ba8f9e)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/bf84c85130d7b9160f62ce8b54e33d5228531217"},{"sha":"7a8d2048bc830c77be7baf5eb71aaef645cb1bf6","author":{"email":"f2295d84e358395675bc8031be58672073ae065e@redhat.com","name":"Dave Airlie"},"message":"mesa/arb_gpu_shader_fp64: add support for glGetUniformdv\n\nThis was missed when I did fp64, I've sent a piglit test to cover\nthe case as well.\n\nReviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>\nCc: \"11.0\" <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Dave Airlie <airlied@redhat.com>\n(cherry picked from commit 45971fd0df1cbfc400f89f2e8df206625b40d65f)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/7a8d2048bc830c77be7baf5eb71aaef645cb1bf6"},{"sha":"67fc4b417a7e73feb840b6666b343f4d32d23f22","author":{"email":"bcbbb7aa705ec3a5fc5824c01a845186c3d62fca@alum.mit.edu","name":"Ilia Mirkin"},"message":"nv50: account for the int RT0 rule for alpha-to-one/cov\n\nSame as commit 1af0641db but for nvc0. If an integer texture is\nbound to RT0, don't do alpha-to-one or alpha-to-coverage.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nCc: \"11.0\" <mesa-stable@lists.freedesktop.org>\n(cherry picked from commit a6ad49cbbd599aec054d0a3163fff5ad724f2b18)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/67fc4b417a7e73feb840b6666b343f4d32d23f22"},{"sha":"0b690e39dc3f84dbce97d507fd7955ecdecbe5c2","author":{"email":"bcbbb7aa705ec3a5fc5824c01a845186c3d62fca@alum.mit.edu","name":"Ilia Mirkin"},"message":"nv50: fix 2d engine blits for 64- and 128-bit formats\n\nThis fixes bin/ext_framebuffer_multisample-formats all_samples\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nCc: \"11.0\" <mesa-stable@lists.freedesktop.org>\n(cherry picked from commit e18c29b03105567cf20bc235ce23cf08986cc537)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/0b690e39dc3f84dbce97d507fd7955ecdecbe5c2"},{"sha":"adae777f24fd84d3a0c074c5f2c01a31d9f63cce","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"Revert \"radeon/winsys: increase the IB size for VM\"\n\nThis reverts commit 567394112d904096abff1d994ab952f475dfb444.\n\nIt regressed performance. It looks like smaller IBs are better, because\nthe GPU goes idle quicker and there is less waiting for buffers and fences.\n\nCc: 11.0 <mesa-stable@lists.freedesktop.org>\n(cherry picked from commit a83c36b5c0c64c717ced76db89bab900006648aa)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/adae777f24fd84d3a0c074c5f2c01a31d9f63cce"},{"sha":"6659fba2c0ea9a5c358e3ef3770585381e619d39","author":{"email":"711c73f64afdce07b7e38039a96d2224209e9a6c@chris-wilson.co.uk","name":"Chris Wilson"},"message":"i965: Always re-emit the pipeline select during invariant state emission\n\nOn the older platforms where we don't have logical contexts preserving\nstate across batches, we emit the invariant state setup on every batch\nusing the brw_invariant_state atom. This includes the pipeline selection\nwhich is cached with the introduction of\n\ncommit 0e0e23ef537c9add672ff322f34e129a07edc55e\nAuthor: Jordan Justen <jordan.l.justen@intel.com>\nDate:   Wed Apr 22 11:43:50 2015 -0700\n\n    i965/state: Emit pipeline select when changing pipelines\n\nHowever, we do not reset the cache between batches on context-less\nplatforms resulting in us not setting the pipeline selection and can\ncause GPU hangs if a media pipelined was loaded in the meantime (e.g.\nmixing mplayer/gstreamer using libva and gnome-shell). A simple solution\nis to just forcibly re-emit the pipeline select along with the invariant\nstate and reset the cache at that point.\n\nReported-and-tested-by: Tomasz C. <tomaszc@o2.pl>\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91254\nSigned-off-by: Chris Wilson <chris@chris-wilson.co.uk>\nCc: Jordan Justen <jordan.l.justen@intel.com>\nCc: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>\nCc: \"10.6 11.0\" <mesa-stable@lists.freedesktop.org>\n(cherry picked from commit 4e5752e2b78243a71766538f62ca0a80488047a7)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/6659fba2c0ea9a5c358e3ef3770585381e619d39"},{"sha":"33b0f6e5e181c52c3eeb7ba4cb3bc0db13f10670","author":{"email":"f2295d84e358395675bc8031be58672073ae065e@redhat.com","name":"Dave Airlie"},"message":"mesa: enable texture stencil8 for multisample\n\nThis fixes GL45-CTS.gtf44.GL31Tests.texture_stencil8.texture_stencil8_gl44\nfrom the ogl conform suite.\n\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>\nCc: 10.6 11.0 <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Dave Airlie <airlied@redhat.com>\n(cherry picked from commit 529acab22a3e21e0ed0c5243675aec6c0ee27e8f)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/33b0f6e5e181c52c3eeb7ba4cb3bc0db13f10670"},{"sha":"5d8ce45d9031e9949dfbab27ab4d608853b86d72","author":{"email":"f2295d84e358395675bc8031be58672073ae065e@redhat.com","name":"Dave Airlie"},"message":"mesa/texgetimage: fix missing stencil check\n\nGetTexImage can read to stencil8 but only from\na stencil or depthstencil textures.\n\nThis fixes a bunch of failures in CTS\nGL33-CTS.gtf32.GL3Tests.packed_pixels\n\nReviewed-by: Marek Olšák <marek.olsak@amd.com>\nCc: \"11.0\" <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Dave Airlie <airlied@redhat.com>\n(cherry picked from commit c1452983b44cc8ee238b8c7e2cfca1105c707487)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/5d8ce45d9031e9949dfbab27ab4d608853b86d72"},{"sha":"812f2855dd601e23a4f813f53547d446ca484df7","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"mesa: create multisample fallback textures like normal textures\n\nThis works if drivers upsample on upload (like all radeon ones do).\nThe alternative is an unexpected GL error from anything calling\n_mesa_update_state and possibly other issues.\n\nCc: 10.6 11.0 <mesa-stable@lists.freedesktop.org>\nReviewed-by: Dave Airlie <airlied@redhat.com>\n(cherry picked from commit f432ae899fb81468778dbeb17ac7615da3ed5c0d)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/812f2855dd601e23a4f813f53547d446ca484df7"},{"sha":"594388e5776312c1bdc9d5613369ed530bb7fbbc","author":{"email":"b186559eaedf698788888c8a2559b4efb4db10d6@intel.com","name":"Jason Ekstrand"},"message":"i965/fs: Split VGRFs after lowering pull constants\n\nThe split_virtual_grfs code doesn't properly rewrite reladdr so we need to\nmake sure that any uniform indirects are lowered away first.\n\nThis fixes the glsl-fs-uniform-indexed-by-swizzled-vec4.shader_test in piglit\n\nCc: \"10.6\" <mesa-stable@lists.freedesktop.org>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>\n(cherry picked from commit fee0c5af11dd0995de96e7053377d425a66d03a0)\n\nConflicts:\n\tsrc/mesa/drivers/dri/i965/brw_fs.cpp","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/594388e5776312c1bdc9d5613369ed530bb7fbbc"},{"sha":"896ef5cb95557fbf68c75600d2bcbb01f8933b98","author":{"email":"bcbbb7aa705ec3a5fc5824c01a845186c3d62fca@alum.mit.edu","name":"Ilia Mirkin"},"message":"mesa: only copy the requested teximage faces\n\nCube maps are special in that they have separate teximages for each\nface. We handled that by copying the data to them separately, but in\ncase zoffset != 0 or depth != 6 we would read off the end of the client\narray or modify the wrong images.\n\nzoffset/depth have already been verified by the time the code gets to\nthis stage, so no need to double-check.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nReviewed-by: Brian Paul <brianp@vmware.com>\nCc: \"10.6 11.0\" <mesa-stable@lists.freedesktop.org>\n(cherry picked from commit 2259b111003f2e8c55cae42677ec45345fb1b6e3)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/896ef5cb95557fbf68c75600d2bcbb01f8933b98"},{"sha":"08c41221d7102106d0b70a6399e2270919458077","author":{"email":"feea5431f8695a3af7470d472cb16ac8e02bab01@gmail.com","name":"Glenn Kennard"},"message":"r600g/sb: Handle undef in read port tracker\n\ne8e443 missed adding check for undef values also in\nunreserve function, leading to an assert triggering.\n\nSigned-off-by: Glenn Kennard <glenn.kennard@gmail.com>\nCc: <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Dave Airlie <airlied@redhat.com>\n(cherry picked from commit 36f1999a87258603b6720d55e6020d5d24c215c9)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/08c41221d7102106d0b70a6399e2270919458077"},{"sha":"9db5c2ca2ea8f4172611337db1cc81f19aab443e","author":{"email":"feea5431f8695a3af7470d472cb16ac8e02bab01@gmail.com","name":"Glenn Kennard"},"message":"r600g/sb: Don't read junk after EOP\n\nShaders that contain instruction data after an instruction with EOP could end\nup parsing that as an instruction, leading to various crashes and asserts in\nSB as it gets very confused if it sees for instance a loop start instruction\njumping off to some random point.\n\nAdd a couple of asserts, and print EOP bit if set in old asm printer.\n\nSigned-off-by: Glenn Kennard <glenn.kennard@gmail.com>\nCc: <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Dave Airlie <airlied@redhat.com>\n(cherry picked from commit a830225adbb77073272961df409885cca6b861ee)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/9db5c2ca2ea8f4172611337db1cc81f19aab443e"},{"sha":"68bd2ddda026afd5e45324d51a5b6b74227c5408","author":{"email":"feea5431f8695a3af7470d472cb16ac8e02bab01@gmail.com","name":"Glenn Kennard"},"message":"r600g/sb: Don't crash on empty if jump target\n\nSigned-off-by: Glenn Kennard <glenn.kennard@gmail.com>\nCc: <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Dave Airlie <airlied@redhat.com>\n(cherry picked from commit 608c7b4a63d5818f7ae0b3d48496b02cf8458d9b)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/68bd2ddda026afd5e45324d51a5b6b74227c5408"},{"sha":"b83b452eea6db023f50611e090f05c5dcafdbc93","author":{"email":"3d0f3b9ddcacec30c4008c5e030e6c13a478cb4f@constexpr.org","name":"Daniel Scharrer"},"message":"mesa: add missing queries for ARB_direct_state_access\n\nThis adds index queries (glGet*i_v) for GL_TEXTURE_BINDING_* and\nGL_SAMPLER_BINDING, as well as textue queries\n(glGetTex{,ture}Parameter*) for GL_TEXTURE_TARGET.\n\nCC: \"10.6 11.0\" <mesa-stable@lists.freedesktop.org>\n\nReviewed-by: Fredrik Höglund <fredrik@kde.org>\nSigned-off-by: Fredrik Höglund <fredrik@kde.org>\n(cherry picked from commit 5aaaaebf22c920745d577c49e463d23b90ba5ea8)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/b83b452eea6db023f50611e090f05c5dcafdbc93"},{"sha":"2fe87a1b68c282846c119bdd930aa936c6504054","author":{"email":"f2295d84e358395675bc8031be58672073ae065e@redhat.com","name":"Dave Airlie"},"message":"gallium/util: fix debug_get_flags_option on 32-bit\n\nOn 32-bit we need to use PRIu64 flags for printfs,\notherwise this segfaults in R600_DEBUG=help otherwise.\n\nReviewed-by: Marek Olšák <marek.olsak@amd.com>\nCc: \"11.0\" <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Dave Airlie <airlied@redhat.com>\n(cherry picked from commit 8d6d0cc17d945317f44328a7761801e6781dc3fc)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/2fe87a1b68c282846c119bdd930aa936c6504054"},{"sha":"1b40221850d41b622e66f7bbea0eed6594b85c4a","author":{"email":"f2295d84e358395675bc8031be58672073ae065e@redhat.com","name":"Dave Airlie"},"message":"r600: port si_conv_prim_to_gs_out from radeonsi\n\nThis code was broken by the tess merge, and I totally missed it\nuntil now. I'm not sure this fixes anything but it stops the assert.\n\nCc: \"11.0\" <mesa-stable@lists.freedesktop.org>\nReviewed-by: Glenn Kennard <glenn.kennard@gmail.com>\nSigned-off-by: Dave Airlie <airlied@redhat.com>\n(cherry picked from commit 6941883175612ae602a8745945153ba064f53a7a)","distinct":true,"url":"https://api.github.com/repos/Uroc327Mirrors/mesa3d/commits/1b40221850d41b622e66f7bbea0eed6594b85c4a"}]}