{"push_id":807503525,"size":16,"distinct_size":1,"ref":"refs/heads/topics/drivers/pc3x3-hw_random-drivers","head":"b6e4d85cd30b54e1e9025cd6ae10d0c800956255","before":"bc3fb61b542e45deb6e9d3f9d522d731ad42ee2b","commits":[{"sha":"fc2ca674470bbfe11d72a20a3f19fd3dc43bfca0","author":{"email":"ba324ca7b1c77fc20bb970d5aff6eea9377918a5@roeck-us.net","name":"Guenter Roeck"},"message":"MIPS: Fix console output for Fulong2e system\n\nCommit 3adeb2566b9b (\"MIPS: Loongson: Improve LEFI firmware interface\")\nmade the number of UARTs dynamic if LEFI_FIRMWARE_INTERFACE is configured.\nUnfortunately, it did not initialize the number of UARTs if\nLEFI_FIRMWARE_INTERFACE is not configured. As a result, the Fulong2e\nsystem has no console.\n\nFixes: 3adeb2566b9b (\"MIPS: Loongson: Improve LEFI firmware interface\")\nAcked-by: Huacai Chen <chenhc@lemote.com>\nSigned-off-by: Guenter Roeck <linux@roeck-us.net>\nTested-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/11076/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/fc2ca674470bbfe11d72a20a3f19fd3dc43bfca0"},{"sha":"88d3426942d748b90b051b7ef2d5d765f5f3054c","author":{"email":"dace7423e438e9d50a283477134876fe17cd3341@gmail.com","name":"Alexander Sverdlin"},"message":"MIPS: bootmem: Fix mapstart calculation for contiguous maps\n\nCommit a6335fa1 fixed the case with gap between initrd and next usable PFN zone,\nbut broken the case when initrd is combined with usable memory into one region\n(in add_memory_region()). Restore the fixup initially brought in by f9a7febd.\n\n---- error message ----\nUnpacking initramfs...\nInitramfs unpacking failed: junk in compressed archive\nBUG: Bad page state in process swapper  pfn:00261\npage:81004c20 count:0 mapcount:-127 mapping:  (null) index:0x2\nflags: 0x0()\npage dumped because: nonzero mapcount\nCPU: 0 PID: 1 Comm: swapper Not tainted 4.2.0+ #1782\n-----------------------\n\nSigned-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>\nReported-by: Tony Wu <tung7970@gmail.com>\nTested-by: Tony Wu <tung7970@gmail.com>\nCc: David Daney <david.daney@cavium.com>\nCc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>\nCc: Huacai Chen <chenhc@lemote.com>\nCc: Joe Perches <joe@perches.com>\nCc: Steven J. Hill <Steven.Hill@imgtec.com>\nCc: Aaro Koskinen <aaro.koskinen@iki.fi>\nCc: stable@vger.kernel.org\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/11086/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/88d3426942d748b90b051b7ef2d5d765f5f3054c"},{"sha":"faa9724a674e5e52316bb0d173aed16bd17d536c","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"MIPS: BPF: Avoid unreachable code on little endian\n\nOn little endian, avoid generating the big endian version of the code\nby using #else in addition to #ifdef #endif. Also fix one alignment\nissue wrt delay slot.\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nReviewed-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: stable@vger.kernel.org # v4.2+\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/11097/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/faa9724a674e5e52316bb0d173aed16bd17d536c"},{"sha":"b259e51f2e29390518021f9b8df55a3de42f371b","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"MIPS: BPF: Fix build on pre-R2 little endian CPUs\n\nThe rotr, seh and wsbh instructions have been introduced with the R2\nISA. Thus the current BPF code fails to build on pre-R2 little endian\nCPUs:\n\n    CC      arch/mips/net/bpf_jit.o\n    AS      arch/mips/net/bpf_jit_asm.o\n  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S: Assembler messages:\n  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:67: Error: opcode not supported on this processor: mips32 (mips32) `wsbh $8,$19'\n  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:68: Error: opcode not supported on this processor: mips32 (mips32) `rotr $19,$8,16'\n  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:83: Error: opcode not supported on this processor: mips32 (mips32) `wsbh $8,$19'\n  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:84: Error: opcode not supported on this processor: mips32 (mips32) `seh $19,$8'\n  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:151: Error: opcode not supported on this processor: mips32 (mips32) `wsbh $8,$12'\n  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:153: Error: opcode not supported on this processor: mips32 (mips32) `rotr $19,$8,16'\n  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:164: Error: opcode not supported on this processor: mips32 (mips32) `wsbh $19,$12'\n  /home/aurel32/linux-4.2/scripts/Makefile.build:294: recipe for target 'arch/mips/net/bpf_jit_asm.o' failed\n\nFix that by providing equivalent code for these CPUs.\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nReviewed-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: stable@vger.kernel.org # v4.2+\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/11098/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/b259e51f2e29390518021f9b8df55a3de42f371b"},{"sha":"84dedd71cf3bc61cc65ca43a48f7252344a1bb68","author":{"email":"c600dc1dfcd5dfaa88c69d8339e7002b7cd99cd3@fe80.eu","name":"Alexander Couzens"},"message":"MIPS: ATH79: Set missing irq ack handler for ar7100-misc-intc irq chip\n\nThe irq ack handler was forgotten while introducing OF support.\nOnly ar71xx and ar933x based devices require it.\n\nSigned-off-by: Alexander Couzens <lynxis@fe80.eu>\nAcked-by: Alban Bedel <albeu@free.fr>\nAcked-by: Thomas Gleixner <tglx@linutronix.de>\nCc: linux-mips@linux-mips.org\nCc: Rob Herring <robh+dt@kernel.org>\nCc: Pawel Moll <pawel.moll@arm.com>\nCc: Mark Rutland <mark.rutland@arm.com>\nCc: Ian Campbell <ijc+devicetree@hellion.org.uk>\nCc: Kumar Gala <galak@codeaurora.org>\nCc: devicetree@vger.kernel.org\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Marc Zyngier <marc.zyngier@arm.com>\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/11163/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/84dedd71cf3bc61cc65ca43a48f7252344a1bb68"},{"sha":"19446da415e0f01d56364b700fe984cda78bca50","author":{"email":"c600dc1dfcd5dfaa88c69d8339e7002b7cd99cd3@fe80.eu","name":"Alexander Couzens"},"message":"MIPS: ATH79: Add irq chip ar7240-misc-intc\n\nThe ar7240 misc irq chip use ack handler\ninstead of ack_mask handler. All new ath79 chips use\nthe ar7240 misc irq chip\n\nSigned-off-by: Alexander Couzens <lynxis@fe80.eu>\nAcked-by: Alban Bedel <albeu@free.fr>\nAcked-by: Thomas Gleixner <tglx@linutronix.de>\nCc: linux-mips@linux-mips.org\nCc: Rob Herring <robh+dt@kernel.org>\nCc: Pawel Moll <pawel.moll@arm.com>\nCc: Mark Rutland <mark.rutland@arm.com>\nCc: Ian Campbell <ijc+devicetree@hellion.org.uk>\nCc: Kumar Gala <galak@codeaurora.org>\nCc: devicetree@vger.kernel.org\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Marc Zyngier <marc.zyngier@arm.com>\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/11164/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/19446da415e0f01d56364b700fe984cda78bca50"},{"sha":"2f6f31363cb7890784458d7805140687b4de5b59","author":{"email":"547fa85bb3888a0222eed8ec39e36708605c6d53@imgtec.com","name":"James Hogan"},"message":"MIPS: cpu-features: Add cpu_has_ftlb\n\nAdd cpu_has_ftlb, which specifies that an FTLB is present in addition to\nthe VTLB, probed based on whether Config.MT == 4 (rather than 1 for\nstandard JTLB).\n\nThis is necessary since MIPS release 6 removes Config4.MMUExtDef, so the\npresence of the FTLB fields in Config4 must be determined from Config.MT\ninstead.\n\nSigned-off-by: James Hogan <james.hogan@imgtec.com>\nCc: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/11159/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/2f6f31363cb7890784458d7805140687b4de5b59"},{"sha":"43d104db596977a8fddc1e71245859a7fe85a658","author":{"email":"547fa85bb3888a0222eed8ec39e36708605c6d53@imgtec.com","name":"James Hogan"},"message":"MIPS: Fix FTLB detection for R6\n\nR6 removed the Config4.MMUExtDef field, with the low 16 bits only\nallowed to contain FTLB fields, and commit e87569cd6c57 (\"MIPS:\ncpu-probe: Fix VTLB/FTLB configuration for R6\") updated the probing of\nthis field to assume an FTLB is always present for R6.\n\nHowever the FTLB may still be absent. The presence of those fields is\nactually specified by the MMU type in the Config.MT field, so use that\n(the new cpu_has_ftlb) to determine whether the FTLB is actually\npresent.\n\nFixes: e87569cd6c57 (\"MIPS: cpu-probe: Fix VTLB/FTLB configuration for R6\")\nSigned-off-by: James Hogan <james.hogan@imgtec.com>\nCc: Ralf Baechle <ralf@linux-mips.org>\nCc: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/11160/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/43d104db596977a8fddc1e71245859a7fe85a658"},{"sha":"7573b94e08aeb5b814e2f277210bdcdf21a83869","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: CM: Provide a function to map from CPU to VP ID.\n\nThe VP ID of a given CPU may not match up with the CPU number used by\nLinux. For example, if the width of the VP part of the VP ID is wider\nthan log2(number of VPs per core) and the system has multiple cores then\nthis will be the case. Alternatively, if a pre-r6 system implements the\nMT ASE with multiple VPEs per core and Linux is built without support\nfor the MT ASE then the numbers won't match up either. Provide a\nfunction to convert from CPU number to VP ID.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nAcked-by: Thomas Gleixner <tglx@linutronix.de>\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nCc: James Hogan <james.hogan@imgtec.com>\nCc: Markos Chandras <markos.chandras@imgtec.com>\nPatchwork: https://patchwork.linux-mips.org/patch/11211/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/7573b94e08aeb5b814e2f277210bdcdf21a83869"},{"sha":"ab41f6c8620a6e65df4ee19d284c97efdd3d9b63","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"irqchip: mips-gic: Convert CPU numbers to VP IDs.\n\nMake use of the mips_cm_vp_id function to convert from Linux CPU numbers\nto the VP IDs used by hardware, which are not identical in all systems.\nWithout doing so we map interrupts to incorrect VP(E)s.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nAcked-by: Thomas Gleixner <tglx@linutronix.de>\nCc: linux-mips@linux-mips.org\nCc: Paul Burton <paul.burton@imgtec.com>\nCc: Marc Zyngier <marc.zyngier@arm.com>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/11212/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/ab41f6c8620a6e65df4ee19d284c97efdd3d9b63"},{"sha":"d77d5ac9c9b5abf45aeb6e12930fab832e5c81d1","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"irqchip: mips-gic: Fix pending & mask reads for MIPS64 with 32b GIC.\n\ngic_handle_shared_int reads the GIC interrupt pending & mask registers\ndirectly into a bitmap, which is defined as an array of unsigned longs.\nThe GIC pending registers may be 32 bits wide if the CM is older than\nCM3, regardless of the bit width of the CPU, but for MIPS64 kernels\nthe unsigned longs in the bitmap will be 64 bits wide. In this case we\nneed to perform 2 x 32 bit reads per 64 bit unsigned long in order to\navoid missing interrupts.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nAcked-by: Thomas Gleixner <tglx@linutronix.de>\nCc: linux-mips@linux-mips.org\nCc: Marc Zyngier <marc.zyngier@arm.com>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/11213/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/d77d5ac9c9b5abf45aeb6e12930fab832e5c81d1"},{"sha":"def3ab5d0a0fe53026c2495b054dcc46cf923dac","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: mm: compile maar_init unconditionally\n\nmaar_init was previously only compiled when CONFIG_NEED_MULTIPLE_NODES\nwas not set, which has been fine since it is only called from the\nstandard implementation of mem_init which has the same condition. In\npreparation for calling it from the SMP startup code on secondary CPUs,\nmove maar_init outside of the #ifndef such that it is always compiled.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nCc: Steven J. Hill <Steven.Hill@imgtec.com>\nCc: David Hildenbrand <dahi@linux.vnet.ibm.com>\nCc: linux-kernel@vger.kernel.org\nCc: Ingo Molnar <mingo@kernel.org>\nPatchwork: https://patchwork.linux-mips.org/patch/11237/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/def3ab5d0a0fe53026c2495b054dcc46cf923dac"},{"sha":"651ca7f4dab77f07fdac9cfb68bcab6bd2b7f827","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: print MAAR configuration during boot\n\nVerifying that the MAAR configuration is as expected is useful when\ndebugging the performance of a system. Print out the memory regions\nconfigured via MAAR along with their attributes.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: linux-mips@linux-mips.org\nCc: Steven J. Hill <Steven.Hill@imgtec.com>\nCc: David Hildenbrand <dahi@linux.vnet.ibm.com>\nCc: linux-kernel@vger.kernel.org\nCc: Peter Zijlstra (Intel) <peterz@infradead.org>\nPatchwork: https://patchwork.linux-mips.org/patch/11238/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/651ca7f4dab77f07fdac9cfb68bcab6bd2b7f827"},{"sha":"e060f6ed281669b6d2f22d8dafd664b532386918","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: Initialise MAARs on secondary CPUs\n\nMAARs should be initialised on each CPU (or rather, core) in the system\nin order to achieve consistent behaviour & performance. Previously they\nhave only been initialised on the boot CPU which leads to performance\nproblems if tasks are later scheduled on a secondary CPU, particularly\nif those tasks make use of unaligned vector accesses where some CPUs\ndon't handle any cases in hardware for non-speculative memory regions.\nFix this by recording the MAAR configuration from the boot CPU and\napplying it to secondary CPUs as part of their bringup.\n\nReported-by: Doug Gilmore <doug.gilmore@imgtec.com>\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: linux-mips@linux-mips.org\nCc: Rusty Russell <rusty@rustcorp.com.au>\nCc: Steven J. Hill <Steven.Hill@imgtec.com>\nCc: Andrew Bresticker <abrestic@chromium.org>\nCc: Bjorn Helgaas <bhelgaas@google.com>\nCc: David Hildenbrand <dahi@linux.vnet.ibm.com>\nCc: linux-kernel@vger.kernel.org\nCc: Aaro Koskinen <aaro.koskinen@iki.fi>\nCc: James Hogan <james.hogan@imgtec.com>\nCc: Ingo Molnar <mingo@kernel.org>\nCc: Markos Chandras <markos.chandras@imgtec.com>\nCc: Hemmo Nieminen <hemmo.nieminen@iki.fi>\nCc: Alex Smith <alex.smith@imgtec.com>\nCc: Peter Zijlstra (Intel) <peterz@infradead.org>\nPatchwork: https://patchwork.linux-mips.org/patch/11239/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/e060f6ed281669b6d2f22d8dafd664b532386918"},{"sha":"097f70b3c4d84ffccca15195bdfde3a37c0a7c0f","author":{"email":"69652caca27c8b940640ad396ab71f93cacec34f@linux-foundation.org","name":"Linus Torvalds"},"message":"Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus\n\nPull MIPS fixes from Ralf Baechle:\n - Properly setup irq handling for ATH79 platforms\n - Fix bootmem mapstart calculation for contiguous maps\n - Handle little endian and older CPUs correct in BPF\n - Fix console for Fulong 2E systems\n - Handle FTLB correctly on R6 CPUs\n - Fixes for CM, GIC and MAAR support code\n\n* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:\n  MIPS: Initialise MAARs on secondary CPUs\n  MIPS: print MAAR configuration during boot\n  MIPS: mm: compile maar_init unconditionally\n  irqchip: mips-gic: Fix pending & mask reads for MIPS64 with 32b GIC.\n  irqchip: mips-gic: Convert CPU numbers to VP IDs.\n  MIPS: CM: Provide a function to map from CPU to VP ID.\n  MIPS: Fix FTLB detection for R6\n  MIPS: cpu-features: Add cpu_has_ftlb\n  MIPS: ATH79: Add irq chip ar7240-misc-intc\n  MIPS: ATH79: Set missing irq ack handler for ar7100-misc-intc irq chip\n  MIPS: BPF: Fix build on pre-R2 little endian CPUs\n  MIPS: BPF: Avoid unreachable code on little endian\n  MIPS: bootmem: Fix mapstart calculation for contiguous maps\n  MIPS: Fix console output for Fulong2e system","distinct":false,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/097f70b3c4d84ffccca15195bdfde3a37c0a7c0f"},{"sha":"b6e4d85cd30b54e1e9025cd6ae10d0c800956255","author":{"email":"17b9e1c64588c7fa6419b4d29dc1f4426279ba01@smart-africa.com","name":"Michael van der Westhuizen"},"message":"arm: Add a hardware random number generator for pc3x3\n\nThis requires cleanup.","distinct":true,"url":"https://api.github.com/repos/r1mikey/linux-picoxcell/commits/b6e4d85cd30b54e1e9025cd6ae10d0c800956255"}]}