{"push_id":646951467,"size":168,"distinct_size":168,"ref":"refs/heads/master","head":"ed3ff94050c7768bf0aeec50a0e62c58b298d15f","before":"6ad1ec4220d6d76ccc30c0c4f1ae49987a3bf9ed","commits":[{"sha":"584f8e1ec56b45057b53e161233308f38e1c3b09","author":{"email":"822ec91a7ef82248fd36162ca8ac3283eba70848@linux.intel.com","name":"Neil Roberts"},"message":"i965/skl: Don't use ALL_SLICES_AT_EACH_LOD\n\nThe render surface state command for Skylake doesn't have the surface\narray spacing bit so it's not possible to select this layout. I think\nit was only used in order to make it pick a tightly-packed qpitch\nvalue that doesn't include space for the mipmaps. However this won't\nbe necessary after the next patch because it will automatically pick a\npacked qpitch value whenever first_level==last_level. It is better to\nremove this layout entirely on Gen8+ because although it can\neffectively be implemented with a small qpitch value when there are no\nmipmaps it isn't possible to support the case where there are mipmaps\nbecause in that case the layout is very different.\n\nIt could be good to make a similar change for Gen8 if we also change\nthe layouting code to pick the qpitch value in a similar way.\n\nv2: Make the commit message and comments more convincing\n\nReviewed-by: Ben Widawsky <ben@bwidawsk.net>\nTested-by: Ben Widawsky <ben@bwidawsk.net>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/584f8e1ec56b45057b53e161233308f38e1c3b09"},{"sha":"7004632b28d8a31b16acc553a1fb31202767bd80","author":{"email":"822ec91a7ef82248fd36162ca8ac3283eba70848@linux.intel.com","name":"Neil Roberts"},"message":"i965/skl: Fix the qpitch value\n\nOn Skylake the qpitch value is uploaded as part of the surface state\nso we don't need to add the extra rows that are done for other\ngenerations. However for 3D textures it needs to be aligned to the\ntile height and for depth/stencil textures it needs to be a multiple\nof 8. Unlike previous generations the qpitch is measured as a multiple\nof the block size for compressed surfaces. When the horizontal mipmap\nlayout is used for 1D textures then the qpitch is measured in pixels\ninstead of rows.\n\nv2: Align the depth/stencil textures to a multiple of 8\nv3: Add an assert that ALL_SLICES_AT_EACH_LOD is not used. Ignore the\n    vertical alignment when picking the qpitch for 1D_ARRAY textures.\n\nReviewed-by: Ben Widawsky <ben@bwidawsk.net>\nReviewed-by: Anuj Phogat <anuj.phogat@gmail.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/7004632b28d8a31b16acc553a1fb31202767bd80"},{"sha":"054c7dc7eb091e631a01ade3e6a46d6cc77fc9f3","author":{"email":"cdcb67a5e49297de94340ca09f25994bd5e7f762@intel.com","name":"Tapani Pälli"},"message":"mesa: fix UBO queries for active uniforms\n\nCommit 34df5eb introduced regression to GetActiveUniformBlockiv\nwhen querying one of the following properties:\n\n   GL_UNIFORM_BLOCK_ACTIVE_UNIFORMS\n   GL_UNIFORM_BLOCK_ACTIVE_UNIFORM_INDICES\n\nImplementation counted all uniforms in ubo directly while query should\ncheck first if the uniform in question is _active_.\n\nSigned-off-by: Tapani Pälli <tapani.palli@intel.com>\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90109\nReviewed-By: Martin Peres <martin.peres@linux.intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/054c7dc7eb091e631a01ade3e6a46d6cc77fc9f3"},{"sha":"5917ca349ae88b35779179a6a0d949ec910bc680","author":{"email":"cdcb67a5e49297de94340ca09f25994bd5e7f762@intel.com","name":"Tapani Pälli"},"message":"glsl: add fallthrough comment on switch\n\nSigned-off-by: Tapani Pälli <tapani.palli@intel.com>\nReviewed-By: Martin Peres <martin.peres@linux.intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/5917ca349ae88b35779179a6a0d949ec910bc680"},{"sha":"ad5ae271e7514e35e97c58f032b2949e3eee62c3","author":{"email":"cdcb67a5e49297de94340ca09f25994bd5e7f762@intel.com","name":"Tapani Pälli"},"message":"mesa: add missing break in switch statement\n\nSigned-off-by: Tapani Pälli <tapani.palli@intel.com>\nReviewed-By: Martin Peres <martin.peres@linux.intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/ad5ae271e7514e35e97c58f032b2949e3eee62c3"},{"sha":"d8b14a57a98f4bad6528eda8dd1406c15bdcce75","author":{"email":"506e8ef0f54c4b319fda4cea9c72fd8d10099c5d@intel.com","name":"Marius Predut"},"message":"radeon: replace __FUNCTION__ with __func__\n\nConsistently just use C99's __func__ everywhere.\nNo functional changes.\n\nSigned-off-by: Marius Predut <marius.predut@intel.com>\nAcked-by: Michel Dänzer <michel.daenzer@amd.com>\nReviewed-by: Emil Velikov <emil.l.velikov@gmail.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/d8b14a57a98f4bad6528eda8dd1406c15bdcce75"},{"sha":"958b4965a23f69085dc04df165d6fccc2707d60e","author":{"email":"506e8ef0f54c4b319fda4cea9c72fd8d10099c5d@intel.com","name":"Marius Predut"},"message":"main: remove __FUNCTION__ defined because it is obsolete\n\nConsistently just use C99's __func__ everywhere.\nNo functional changes.\n\nSigned-off-by: Marius Predut <marius.predut@intel.com>\nReviewed-by: Emil Velikov <emil.l.velikov@gmail.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/958b4965a23f69085dc04df165d6fccc2707d60e"},{"sha":"3b4abdae041802183fa7d3792a21bf9ca10df96e","author":{"email":"789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com","name":"Matt Turner"},"message":"i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.\n\nThe BSpec says this applies to Gen6 as well.\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/3b4abdae041802183fa7d3792a21bf9ca10df96e"},{"sha":"dd5c8250537640f92dbc1ee63d516c6e3e2aaf77","author":{"email":"789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com","name":"Matt Turner"},"message":"i965: Replace guess_execution_size with something simpler.\n\nguess_execution_size() does two things:\n\n   1. Cope with small destination registers.\n   2. Cope with SIMD8 vs SIMD16 mode.\n\nThis patch replaces the first with a simple if block in brw_set_dest: if\nthe destination register width is less than 8, you probably want the\nexecution size to match.  (I didn't put this in the 3src block because\nit doesn't seem to matter.)\n\nSince only the FS compiler cares about SIMD16 mode, it's easy to just\nset the default execution size there.\n\nThis pattern was already been proven in the Gen8+ generator, but we\ndidn't port it back to the existing generator when we combined the two.\n\nThis is based on a patch from Ken from about a year ago. I've rebased it\nand and fixed a few bugs.\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/dd5c8250537640f92dbc1ee63d516c6e3e2aaf77"},{"sha":"45a13486126fdf0cbb68b7a888cff642c32c1d12","author":{"email":"789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com","name":"Matt Turner"},"message":"i965: Make type_sz() return unsigned.\n\nAvoids annoying warnings when comparing with sizeof(...).\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/45a13486126fdf0cbb68b7a888cff642c32c1d12"},{"sha":"b5a5b63548e9b27a3d0b8ad1b399006c71dcc3c4","author":{"email":"789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com","name":"Matt Turner"},"message":"i965/fs: Allow an execution size of 32.\n\nIn a few commits, we'll start emitting an add(32) instruction on some\nplatforms.\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/b5a5b63548e9b27a3d0b8ad1b399006c71dcc3c4"},{"sha":"8bc49f9536058a8373d3057324e22fcbf79a7d89","author":{"email":"789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com","name":"Matt Turner"},"message":"i965/fs: Set compression only if writing two registers.\n\nWe don't want to set compression control on a SIMD16 instruction\noperating on words or smaller.\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/8bc49f9536058a8373d3057324e22fcbf79a7d89"},{"sha":"a1dd2f0bb6f9bf61d4a40d033740140b86c060e0","author":{"email":"789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com","name":"Matt Turner"},"message":"i965/fs: Add LINTERP's src0 to fs_inst::regs_read().\n\nLINTERP's src0 is PLN's src1, and PLN's src1 reads exec_size / 4\nregisters.\n\nHaving that information lets us drop the delta_x/y special case code in\nsplit_virtual_grfs().\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/a1dd2f0bb6f9bf61d4a40d033740140b86c060e0"},{"sha":"b14313e45295d91b5737775ec788c76d8f0c2f93","author":{"email":"789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com","name":"Matt Turner"},"message":"i965/fs: Manually set source regioning on PLN instructions.\n\nLike LINE (commit 92346db0), src0 must have a scalar region. Setting\nsrc1's region to <8,8,1> lets us pass a properly sized combined delta_xy\nargument in a few commits without getting a bogus <16,16,1> region.\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/b14313e45295d91b5737775ec788c76d8f0c2f93"},{"sha":"fde3100fe65a175f034c77e7989601839c9983bb","author":{"email":"789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com","name":"Matt Turner"},"message":"i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.\n\nThese were used only on Gen4 and 5. emit_interpolation_setup_gen6() emits\nADDs directly. The virtual opcodes weren't providing anything useful.\n\nI'm going to repurpose these opcodes, so deleting and readding them makes\nit simpler to see what's going on.\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/fde3100fe65a175f034c77e7989601839c9983bb"},{"sha":"5af0604d528733af9113a6f8711c39796ce0ae40","author":{"email":"789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com","name":"Matt Turner"},"message":"i965/fs: Calculate delta_x and delta_y together.\n\nThis lets SIMD16 programs on G45 and Gen5 use the PLN instruction.\n\nOn Ironlake:\n\ntotal instructions in shared programs: 5634757 -> 5518055 (-2.07%)\ninstructions in affected programs:     1745837 -> 1629135 (-6.68%)\nhelped:                                11439\nHURT:                                  4\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/5af0604d528733af9113a6f8711c39796ce0ae40"},{"sha":"529064f6a80d72294cc865a46304110e0401296d","author":{"email":"789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com","name":"Matt Turner"},"message":"i965/fs: Combine pixel center calculation into one inst.\n\nThe X and Y values come interleaved in g1 (.4-.11 inclusive), so we can\ncalculate them together with a single add(32) instruction on some\nplatforms like Broadwell and newer or in SIMD8 elsewhere.\n\nNote that I also moved the PIXEL_X/PIXEL_Y virtual opcodes from before\nLINTERP to after it. That's because the writes_accumulator_implicitly()\nfunction in backend_instruction tests for <= LINTERP for determining\nwhether the instruction indeed writes the accumulator implicitly. The\nold FS_OPCODE_PIXEL_X/Y emitted ADD instructions, which did, but the new\nopcodes just emit MOVs, which don't. It doesn't matter, since we don't\nuse these opcodes on Gen4/5 anymore, but in the case that we do...\n\nOn Broadwell:\ntotal instructions in shared programs: 7192355 -> 7186224 (-0.09%)\ninstructions in affected programs:     1190700 -> 1184569 (-0.51%)\nhelped:                                6131\n\nOn Haswell:\ntotal instructions in shared programs: 6155979 -> 6152800 (-0.05%)\ninstructions in affected programs:     652362 -> 649183 (-0.49%)\nhelped:                                3179\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/529064f6a80d72294cc865a46304110e0401296d"},{"sha":"ed10f9cfad1a01226725d542155a240bcf70e9cb","author":{"email":"cdcb67a5e49297de94340ca09f25994bd5e7f762@intel.com","name":"Tapani Pälli"},"message":"glsl: correct indentation of comment, Trivial.\n\nSigned-off-by: Tapani Pälli <tapani.palli@intel.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/ed10f9cfad1a01226725d542155a240bcf70e9cb"},{"sha":"44461e70985278464f5c2ce89bda2336c7299b0b","author":{"email":"bd2562f754ec92342f93f61c25d731e290a2ffa8@whitecape.org","name":"Kenneth Graunke"},"message":"nir: Fix per-component negation in prog_to_nir's SWZ handling.\n\nI missed the fact that the ARB_fragment_program SWZ instruction allows\nper-component negation.  To fix this, move Abs/Negate handling into both\nthe simple case and the SWZ case's per-component loop.\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90000\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Matt Turner <mattst88@gmail.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/44461e70985278464f5c2ce89bda2336c7299b0b"},{"sha":"00bf7d2e9cd60dbd82d25b459c448e11c545a89a","author":{"email":"bd2562f754ec92342f93f61c25d731e290a2ffa8@whitecape.org","name":"Kenneth Graunke"},"message":"drirc: Add \"Second Life\" quirk (allow_glsl_extension_directive_midshader).\n\nAppears to fix shader compilation.  Tested by starting the client,\ndragging the \"quality and speed\" slider back and forth, and watching the\nconsole output - instead of piles of \"shader failed to compile\", the CPU\nseems to be busy compiling shaders.  I haven't actually tried to play.\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69226\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71591\nCc: mesa-stable@lists.freedesktop.org","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/00bf7d2e9cd60dbd82d25b459c448e11c545a89a"}]}