{"push_id":563202552,"size":170,"distinct_size":170,"ref":"refs/heads/master","head":"112db9407dd338f71200beb0fc99dffa8dcb57a8","before":"2af13d6b6265a6700c4f65597410b769895024bf","commits":[{"sha":"5dea3a745b88041d677fc03d34df04dd2836265c","author":{"email":"c93d368f28096020dd845c4879a931e9d13ab23f@analog.com","name":"Sonic Zhang"},"message":"bfin: enlarge the monitor size for ip04 board to avoid oversize link error\n\nSigned-off-by: Sonic Zhang <sonic.zhang@analog.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/5dea3a745b88041d677fc03d34df04dd2836265c"},{"sha":"0d3fd562c4977af4e992f3f73a441081ff8c60d0","author":{"email":"c93d368f28096020dd845c4879a931e9d13ab23f@analog.com","name":"Sonic Zhang"},"message":"bfin: make env offset sector aligned for bct-brettl2 and ibf-dsp561 boards\n\nSigned-off-by: Sonic Zhang <sonic.zhang@analog.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/0d3fd562c4977af4e992f3f73a441081ff8c60d0"},{"sha":"2b8bcc5a2fca54648ece966902b8230de971b609","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: avoid .set ISA for cache operations\n\nAs a step towards unifying the cache maintenance code for mips32 &\nmips64 CPUs, stop using \".set <ISA>\" directives in the more developed\nmips32 version of the code. Instead, when present make use of the GCC\nbuiltin for emitting a cache instruction. When not present, simply don't\nbother with the .set directives since U-boot always builds with\n-march=mips32 or higher anyway.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/2b8bcc5a2fca54648ece966902b8230de971b609"},{"sha":"30374f98d14d5979f95a9d21d66346eaa9a795a1","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: unify cache maintenance functions\n\nMove the more developed mips32 version of the cache maintenance\nfunctions to a common arch/mips/lib/cache.c, in order to reduce\nduplication between mips32 & mips64.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/30374f98d14d5979f95a9d21d66346eaa9a795a1"},{"sha":"4a5d8898bca3e442b61e34b811aec8332752efd3","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: unify cache initialization code\n\nThe mips32 & mips64 cache initialization code differs only in that the\nmips32 code supports reading the cache size from coprocessor 0 registers\nat runtime. Move the more developed mips32 version to a common\narch/mips/lib/cache_init.S & remove the now-redundant mips64 version in\norder to reduce duplication. The temporary registers used are shuffled\nslightly in order to work for both mips32 & mips64 builds. The RA\nregister is defined differently to suit mips32 & mips64, but will be\nremoved by a later commit in the series after further cleanup.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/4a5d8898bca3e442b61e34b811aec8332752efd3"},{"sha":"536cb7ce1aca10c326ac864b3e1d05ab57b3ec7e","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: refactor L1 cache config reads to a macro\n\nReduce duplication between reading the configuration of the L1 dcache &\nicache by performing both using a macro which calculates the appropriate\nline & cache sizes from the coprocessor 0 Config1 register.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/536cb7ce1aca10c326ac864b3e1d05ab57b3ec7e"},{"sha":"ac22feca1135b81ecc4d38995e98b59943d1bbf5","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: refactor cache loops to a macro\n\nReduce duplication by performing loops through cache tags using an\nassembler macro.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/ac22feca1135b81ecc4d38995e98b59943d1bbf5"},{"sha":"ca4e833cd6409c72e5b13ee803a4f08381e6d160","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: inline mips_init_[id]cache functions\n\nThe mips_init_[id]cache functions are small & only called once from a\nsingle callsite. Inlining them allows mips_cache_reset to avoid having\nto bother moving arguments around & leaves it a leaf function which is\nthus able to simply keep the return address live in the ra register\nthroughout, simplifying the code.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/ca4e833cd6409c72e5b13ee803a4f08381e6d160"},{"sha":"dd7c72006e51f0d27e5cb1dcf60d5b9bf307565e","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: allow systems to skip loads during cache init\n\nCurrent MIPS systems do not require that loads be performed to force the\nparity of cache lines, a simple invalidate by clearing the tag for each\nline will suffice. Thus this patch makes the loads & subsequent second\ninvalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD\noption, and defines that for existing mips32 targets. Exceptions are\nmalta where this is known to be unnecessary, and qemu-mips where caches\nare not implemented.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/dd7c72006e51f0d27e5cb1dcf60d5b9bf307565e"},{"sha":"8755d50706742e4d302a335f4e69dd6430ec12a2","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: clear TagLo select 2 during cache init\n\nCurrent MIPS cores from Imagination Technologies use TagLo select 2 for\nthe data cache. The architecture requires that it is safe for software\nto write to this register even if it isn't present, so take the trivial\noption of clearing both selects 0 & 2.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/8755d50706742e4d302a335f4e69dd6430ec12a2"},{"sha":"ba21a453a58fc02b890f4064b293b1cb09fe7484","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"malta: IDE support\n\nThis patch adds IDE support to the MIPS Malta board. The IDE controller\nis enabled after probing the PCI bus and otherwise just makes use of\nU-boot generic IDE support.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/ba21a453a58fc02b890f4064b293b1cb09fe7484"},{"sha":"28c8c3d40fcc96e57d87c4a770adf7f11193bd69","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"malta: delay after reset\n\nReset isn't instant, so delay to give it a chance. Otherwise we go on\nto print a failure message before resetting anyway.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/28c8c3d40fcc96e57d87c4a770adf7f11193bd69"},{"sha":"a3bdaacaf61deb74565d1b9e9ad3497b6f7a4051","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"malta: enable HUSH parser\n\nThe malta board is used for development and thus the shell is interacted\nwith often. Enable HUSH to make the experience a little more pleasant.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/a3bdaacaf61deb74565d1b9e9ad3497b6f7a4051"},{"sha":"d4d774e00e7232b524ddb20d992c5b12d84e3ef2","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"malta: enable ELF loading\n\nThe ability to load ELF files is sometimes useful on Malta boards,\nparticularly for use with small embedded applications. Enable the\nloadelf command in the malta config.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/d4d774e00e7232b524ddb20d992c5b12d84e3ef2"},{"sha":"b558af81281975d032c063ad228a400d8e619ad5","author":{"email":"7e7c4459a6ddf96c6d5f3a5b845705a5b54f4f2e@mm-sol.com","name":"Lubomir Popov"},"message":"ARM: OMAP5: DRA7xx: Add support for power rail grouping\n\nOn the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC\ncore rails. This concept of using one SMPS to supply multiple\ncore domains (in various, although limited combinations, per\nprimary device use case) has now become common and is used by\nmany customer J6/J6Eco designs; it is supported by a number of\ncorresponding PMIC OTP versions.\n\nThis patch implements correct operation of the core voltages\nscaling routine by ensuring that each SMPS that is supplying\nmore than one domain shall be written only once, and with the\nhighest voltage of those fused in the SoC (or of those defined\nin the corresponding header if fuse read is disabled or fails)\nfor the power rails belonging to the group.\n\nThe patch also replaces some PMIC-related magic numbers with\nthe appropriate definitions. The default OPP_NOM voltages for\nthe DRA7xx SoCs are updated as well, per the latest DMs.\n\nSigned-off-by: Lubomir Popov <l-popov@ti.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/b558af81281975d032c063ad228a400d8e619ad5"},{"sha":"6e721bdb541e313528ffebb8c88532b41ae6df7c","author":{"email":"47764aff062bf9ebe98a2274b29052b74a9567e2@ti.com","name":"Tom Rini"},"message":"am335x_evm: Enable CONFIG_NAND_OMAP_GPMC_PREFETCH\n\nSigned-off-by: Tom Rini <trini@ti.com>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/6e721bdb541e313528ffebb8c88532b41ae6df7c"},{"sha":"8dcd1b720e5c44bb4ca6f41181f3b937ae6e08c1","author":{"email":"271b10744f2b592adf8fde144d536c86b011b93c@gmail.com","name":"Pali Rohár"},"message":"Nokia RX-51: Use generic board\n\nGeneric board with #define CONFIG_SYS_GENERIC_BOARD is working fine.\nThere is no visible difference between legacy and generic board code.\n\nSigned-off-by: Pali Rohár <pali.rohar@gmail.com>\nAcked-by: Pavel Machek <pavel@ucw.cz>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/8dcd1b720e5c44bb4ca6f41181f3b937ae6e08c1"},{"sha":"168f594765cb4692362e6e552c272c034e7efd88","author":{"email":"226e2ce7264e33e8fc912be1b12714b5383696f9@3adev.fr","name":"Albert ARIBAUD \\(3ADEV\\)"},"message":"omap3: enable GP9 timer and UART2\n\nThese are needed for the upcoming Cairo board support.\n\nSigned-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/168f594765cb4692362e6e552c272c034e7efd88"},{"sha":"03843da5d542b4516666434361c3a2211aa180ed","author":{"email":"226e2ce7264e33e8fc912be1b12714b5383696f9@3adev.fr","name":"Albert ARIBAUD \\(3ADEV\\)"},"message":"omap3: make SDRC SHARING setting configurable\n\nSigned-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/03843da5d542b4516666434361c3a2211aa180ed"},{"sha":"d215b3e5e3e40235b5f644e5b66e2f16d110b117","author":{"email":"226e2ce7264e33e8fc912be1b12714b5383696f9@3adev.fr","name":"Albert ARIBAUD \\(3ADEV\\)"},"message":"omap3: add SDRC settings for Samsung K4X51163PG\n\nSigned-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>","distinct":true,"url":"https://api.github.com/repos/ckuethe/uboot-denx/commits/d215b3e5e3e40235b5f644e5b66e2f16d110b117"}]}