{"push_id":766510050,"size":737,"distinct_size":2,"ref":"refs/heads/linux-next/master","head":"1ef981bcd18de26dc78bc79f092d6f4bb25e0e8f","before":"f0359ead9129821e4b3b5486e7837d3001a95574","commits":[{"sha":"9450918293b3c35f11883231a53da1aed2c78403","author":{"email":"978acd1567d5598152161fdf8bf3ca568f950c9b@linux-iscsi.org","name":"Nicholas Bellinger"},"message":"target: Perform RCU callback barrier before backend/fabric unload\n\nThis patch addresses a v4.2-rc1 regression where backend driver\nmodule unload happening immediately after TBO->free_device()\ndoes internal call_rcu(), will currently result in IRQ context\nrcu_process_callbacks() use-after-free paging OOPsen.\n\nIt adds the missing rcu_barrier() in target_backend_unregister()\nto perform an explicit RCU barrier waiting for all RCU callbacks\nto complete before releasing target_backend_ops memory, and\nallowing TBO->module exit to proceed.\n\nAlso, do the same for fabric drivers in target_unregister_template()\nto ensure se_deve_entry->rcu_head -> kfree_rcu() callbacks have\ncompleted, before allowing target_core_fabric_ops->owner module\nexit to proceed.\n\nAcked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>\nCc: Christoph Hellwig <hch@lst.de>\nCc: Hannes Reinecke <hare@suse.de>\nCc: Sagi Grimberg <sagig@mellanox.com>\nSigned-off-by: Nicholas Bellinger <nab@linux-iscsi.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/9450918293b3c35f11883231a53da1aed2c78403"},{"sha":"9547308bda296b6f69876c840a0291fcfbeddbb8","author":{"email":"7b9769c9c63db7b456a556857e9f88090ee9c9a2@purestorage.com","name":"Alexei Potashnik"},"message":"target/iscsi: Fix double free of a TUR followed by a solicited NOPOUT\n\nMake sure all non-READ SCSI commands get targ_xfer_tag initialized\nto 0xffffffff, not just WRITEs.\n\nDouble-free of a TUR cmd object occurs under the following scenario:\n\n1. TUR received (targ_xfer_tag is uninitialized and left at 0)\n2. TUR status sent\n3. First unsolicited NOPIN is sent to initiator (gets targ_xfer_tag of 0)\n4. NOPOUT for NOPIN (with TTT=0) arrives\n - its ExpStatSN acks TUR status, TUR is queued for removal\n - LIO tries to find NOPIN with TTT=0, but finds the same TUR instead,\n   TUR is queued for removal for the 2nd time\n\n(Drop unbalanced conditional bracket usage - nab)\n\nSigned-off-by: Alexei Potashnik <alexei@purestorage.com>\nSigned-off-by: Spencer Baugh <sbaugh@catern.com>\nCc: <stable@vger.kernel.org> # v3.1+\nSigned-off-by: Nicholas Bellinger <nab@linux-iscsi.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/9547308bda296b6f69876c840a0291fcfbeddbb8"},{"sha":"9c395170a559d3b23dad100b01fc4a89d661c698","author":{"email":"0d270388f2f92757a5de0f4bd891d3b392c44c4f@purestorage.com","name":"Roland Dreier"},"message":"target: REPORT LUNS should return LUN 0 even for dynamic ACLs\n\nIf an initiator doesn't have any real LUNs assigned, we should report\nLUN 0 and a LUN list length of 1.  Some versions of Solaris at least\ngo beserk if we report a LUN list length of 0.\n\nSigned-off-by: Roland Dreier <roland@purestorage.com>\nCc: <stable@vger.kernel.org> # v3.1+\nSigned-off-by: Nicholas Bellinger <nab@linux-iscsi.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/9c395170a559d3b23dad100b01fc4a89d661c698"},{"sha":"b7d0eb6507b6cbae48f3e47e479e6205ee2c4f0a","author":{"email":"08cd4c4b74f2a6d260dcb581967005084d725085@free.fr","name":"Alban Bedel"},"message":"MIPS: ath79: irq: IRQCHIP_DECLARE moved to linux/irqchip.h\n\nRemove the ugly cross tree include now that IRQCHIP_DECLARE moved to\nlinux/irqchip.h.\n\nSigned-off-by: Alban Bedel <albeu@free.fr>\nCc: linux-mips@linux-mips.org\nCc: Thomas Gleixner <tglx@linutronix.de>\nCc: Andrew Bresticker <abrestic@chromium.org>\nCc: Qais Yousef <qais.yousef@imgtec.com>\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/10633/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/b7d0eb6507b6cbae48f3e47e479e6205ee2c4f0a"},{"sha":"825b7b54bc9df54cfe75bf32c67f4e01add3e133","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: Add MIPS I6400 PRid and cputype identifiers\n\nAdd a Processor ID and CPU type for the MIPS I6400 core.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10634/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/825b7b54bc9df54cfe75bf32c67f4e01add3e133"},{"sha":"2e695b9f2bfb754e0a60900acfc4c094b4f41609","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: Add cases for CPU_I6400\n\nAdd a CPU_I6400 case to various switch statements, doing the same thing\nas for CPU_P5600.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10635/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/2e695b9f2bfb754e0a60900acfc4c094b4f41609"},{"sha":"4910bf6a2c7ea97c7c8f6e6081111e0e211e0c67","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: Add MIPS I6400 probe support\n\nAdd a case in cpu_probe_mips for the MIPS I6400 processor ID, which sets\nthe CPU type to the new CPU_I6400.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10636/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/4910bf6a2c7ea97c7c8f6e6081111e0e211e0c67"},{"sha":"e4db37e4d1bdf964abfbb18a19b6e34cb8b0c403","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: Kconfig: Disable MIPS MT and SMP implementations for R6\n\nR6 does not support the MIPS MT ASE and the CMP/SMP options so\nrestrict them in order to prevent users from selecting incompatible\nSMP configuration for R6 cores. We also disable the CPS/SMP option\nbecause its support hasn't been added to the CPS code yet.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10637/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/e4db37e4d1bdf964abfbb18a19b6e34cb8b0c403"},{"sha":"2140bc50374408ad56c53f9c003f647724b0df46","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: mips-cm: Implement mips_cm_revision\n\nProvide a function to trivially return the version of the CM present in\nthe system, or 0 if no CM is present. The mips_cm_revision() will be\nused later on to determine the CM register width, so it must not use\nthe regular CM accessors to read the revision register since that will\nlead to build failures due to recursive inlines.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10638/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/2140bc50374408ad56c53f9c003f647724b0df46"},{"sha":"39c73ae32e14dc17d2e98ca5a816c9ad5d9199d8","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: CM: Add GCR_L2_CONFIG register accessors\n\nProvide accessor functions for the GCR_L2_CONFIG register introduced\nwith CM3, and define the bits included in the register.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10639/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/39c73ae32e14dc17d2e98ca5a816c9ad5d9199d8"},{"sha":"321c4c3ab8650fa455cbf59f873c5f9ede874a79","author":{"email":"85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com","name":"Paul Burton"},"message":"MIPS: CM3: Add support for CM3 L2 cache.\n\nDetect the L2 cache configuration from GCR_L2_CONFIG when a CM3 is\npresent in the system, rather than from Config2 which does not expose\nthe L2 configuration on I6400.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10641/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/321c4c3ab8650fa455cbf59f873c5f9ede874a79"},{"sha":"572788564f085eac9d839db8f0e2f2c324c3f7ff","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: Add platform callback before initializing the L2 cache\n\nAllow platforms to perform platform-specific steps before configuring\nthe L2 cache. This is necessary for platforms with CM3 since the L2\nparameters no longer live in the Config2 register.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: Paul Burton <paul.burton@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10642/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/572788564f085eac9d839db8f0e2f2c324c3f7ff"},{"sha":"7c6ebb54d8b8cdcd9d722c5f701a39feeeb0486c","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: mips-cm: Extend CM accessors for 64-bit CPUs\n\nPreviously, the CM accessors were only accessing CM registers as u32\ntypes instead of using the native CM register with. However, newer CMs\nmay actually be 64-bit on MIPS64 cores. Fortunately, current 64-bit CMs\n(CM3) hold all the useful configuration bits in the lower half of the\n64-bit registers (at least most of them) so they can still be accessed\nusing the current 32-bit accessors.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: Thomas Gleixner <tglx@linutronix.de>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Andrew Bresticker <abrestic@chromium.org>\nCc: Paul Burton <paul.burton@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10707/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/7c6ebb54d8b8cdcd9d722c5f701a39feeeb0486c"},{"sha":"7cf910b7c9ea6e9d6cd44603ff66e133d2a18ecc","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels.\n\nThe CMGCRBase register (CP0, 15, 3) register is 64-bit on MIPS64\nso we change its type to unsigned long.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: Paul Burton <paul.burton@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10644/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/7cf910b7c9ea6e9d6cd44603ff66e133d2a18ecc"},{"sha":"225606f5bea896319a5176af23f8b99b67aa9343","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: CPC: Fix type for GCR CPC base reg for 64-bit\n\nThe GCR CPC base register is 64-bit on 64-bit processors so use the\nappropriate field.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10645/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/225606f5bea896319a5176af23f8b99b67aa9343"},{"sha":"94599999ac45ee347bb5af1f5dd235fce26a8f19","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: CM: Add support for reporting CM cache errors\n\nThe CM cache error reporting code is not Malta specific and as such it\nshould live in the mips-cm.c file. Moreover, CM2 and CM3 differ in the\nway cache errors are being recorded to the registers so extend the\nprevious code to add support for the CM3 as well.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10646/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/94599999ac45ee347bb5af1f5dd235fce26a8f19"},{"sha":"6b8f48ddcdf9b2514d0a5260419c2539a424e47d","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"IRQCHIP: irq-mips-gic: Extend GIC accessors for 64-bit CMs\n\nPreviously, the GIC accessors were only accessing u32 registers but\nnewer CMs may actually be 64-bit on MIPS64 cores. As a result of which,\nextended these accessors to support 64-bit reads and writes.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: Thomas Gleixner <tglx@linutronix.de>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Andrew Bresticker <abrestic@chromium.org>\nCc: Paul Burton <paul.burton@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10709/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/6b8f48ddcdf9b2514d0a5260419c2539a424e47d"},{"sha":"1e56f0ef3f3405f0443fce304d95a6f991fc52fa","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"IRQCHIP: irq-mips-gic: Add support for CM3 64-bit timer irqs\n\nCM3 uses a 64-bit counter and compare registers so add support for\nthem in the GIC counter interrupt.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: Thomas Gleixner <tglx@linutronix.de>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Andrew Bresticker <abrestic@chromium.org>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10648/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/1e56f0ef3f3405f0443fce304d95a6f991fc52fa"},{"sha":"042b0ef91f1de815dfdfff803c5b7b6b28879b16","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB\n\nWe are so early in the boot process where we really don't want to\nstall and wait for CP0 FTLB related changes become visible so just drop\nthe cp0 hazard barrier.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10649/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/042b0ef91f1de815dfdfff803c5b7b6b28879b16"},{"sha":"1fabd4cf2341c7953e0a6fd8d60001d47797a921","author":{"email":"5cdbcb0e11d2b5ebc39222958c54a1c6329d0c9d@imgtec.com","name":"Markos Chandras"},"message":"MIPS: Add default case for the FTLB enable/disable code\n\nAdd a default case for the FTLB enable/disable code. This will be used\nto detect that something went wrong in the set_ftlb_enable() function\neither because that function knows nothing about the running core, or\nsimply because the core can't turn its FTLB on/off.\n\nSigned-off-by: Markos Chandras <markos.chandras@imgtec.com>\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/10650/\nSigned-off-by: Ralf Baechle <ralf@linux-mips.org>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm/commits/1fabd4cf2341c7953e0a6fd8d60001d47797a921"}]}