{"push_id":704331133,"size":1,"distinct_size":1,"ref":"refs/heads/cmrt_enhancement","head":"69298d5e9ad536a15a76bf9727a22e750386ddab","before":"aae15f7b6967e81be070f20c14c7c708bc3fa7db","commits":[{"sha":"69298d5e9ad536a15a76bf9727a22e750386ddab","author":{"email":"ac030c976d1eb7000ef30b00e1c536269f2fc550@intel.com","name":"Midhun Kodiyath"},"message":"Add L3 cache changes for Gen9\n\nSigned-off-by: Midhun Kodiyath <midhunchandra.kodiyath@intel.com>","distinct":true,"url":"https://api.github.com/repos/MidhunKodiyath/cmrt/commits/69298d5e9ad536a15a76bf9727a22e750386ddab"}]}