{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/12","labels_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/12/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/12/comments","events_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/12/events","html_url":"https://github.com/ucb-bar/rocket-chip/issues/12","id":100454821,"number":12,"title":"how to convert the scala sources to verilog","user":{"login":"huangchengxtu","id":11765024,"avatar_url":"https://avatars.githubusercontent.com/u/11765024?v=3","gravatar_id":"","url":"https://api.github.com/users/huangchengxtu","html_url":"https://github.com/huangchengxtu","followers_url":"https://api.github.com/users/huangchengxtu/followers","following_url":"https://api.github.com/users/huangchengxtu/following{/other_user}","gists_url":"https://api.github.com/users/huangchengxtu/gists{/gist_id}","starred_url":"https://api.github.com/users/huangchengxtu/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/huangchengxtu/subscriptions","organizations_url":"https://api.github.com/users/huangchengxtu/orgs","repos_url":"https://api.github.com/users/huangchengxtu/repos","events_url":"https://api.github.com/users/huangchengxtu/events{/privacy}","received_events_url":"https://api.github.com/users/huangchengxtu/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"milestone":null,"comments":1,"created_at":"2015-08-12T03:04:34Z","updated_at":"2015-08-12T16:40:35Z","closed_at":"2015-08-12T16:40:35Z","body":"Hi all,\r\nI have changed the zscale. Mainly is to change the bus. I want to  convert the scala sources to verilog in rocket-chip. What should i do ?\r\n\r\nThanks a lot for your feedback."},"comment":{"url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/comments/130365352","html_url":"https://github.com/ucb-bar/rocket-chip/issues/12#issuecomment-130365352","issue_url":"https://api.github.com/repos/ucb-bar/rocket-chip/issues/12","id":130365352,"user":{"login":"ben-k","id":2288633,"avatar_url":"https://avatars.githubusercontent.com/u/2288633?v=3","gravatar_id":"","url":"https://api.github.com/users/ben-k","html_url":"https://github.com/ben-k","followers_url":"https://api.github.com/users/ben-k/followers","following_url":"https://api.github.com/users/ben-k/following{/other_user}","gists_url":"https://api.github.com/users/ben-k/gists{/gist_id}","starred_url":"https://api.github.com/users/ben-k/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ben-k/subscriptions","organizations_url":"https://api.github.com/users/ben-k/orgs","repos_url":"https://api.github.com/users/ben-k/repos","events_url":"https://api.github.com/users/ben-k/events{/privacy}","received_events_url":"https://api.github.com/users/ben-k/received_events","type":"User","site_admin":false},"created_at":"2015-08-12T16:40:34Z","updated_at":"2015-08-12T16:40:34Z","body":"As noted in the README, to generate VLSI-synthesizable verilog (output will be in vsim/generated-src):\r\n\r\n```\r\n$ cd vsim\r\n$ make verilog\r\n```"}}