{"push_id":775947858,"size":5,"distinct_size":5,"ref":"refs/heads/master","head":"1a8470837d1320c79da11bad2e2ad3030be8672c","before":"91646a37d5da41c21561b4b5189cdd3c5a04bc4f","commits":[{"sha":"5c5d8128774f094a4c6eadb25e1ad7738bb6bd19","author":{"email":"f29b71c75b9b1809bf1104c7050a1d956a5cd26b@gmail.com","name":"Sahand Kashani-Akhavan"},"message":"[cmos_sensor_input]\nReduced range for PACK_WIDTH to 256 bits maximun, as bitsPerSymbol is fixed to 8, and with a maximum of 32 symbols per cycle -> 256-bit maximum data width.","distinct":true,"url":"https://api.github.com/repos/sahandKashani/HDL-IP-cores/commits/5c5d8128774f094a4c6eadb25e1ad7738bb6bd19"},{"sha":"3c579d0d8bcdfaf39bb8a30f4c4ff6f3f4f987ae","author":{"email":"f29b71c75b9b1809bf1104c7050a1d956a5cd26b@gmail.com","name":"Sahand Kashani-Akhavan"},"message":"[cmos_sensor_input]\nQsys interface image for documentation.","distinct":true,"url":"https://api.github.com/repos/sahandKashani/HDL-IP-cores/commits/3c579d0d8bcdfaf39bb8a30f4c4ff6f3f4f987ae"},{"sha":"62e22e78444ec36058945d1be5ee54ef654b5f23","author":{"email":"f29b71c75b9b1809bf1104c7050a1d956a5cd26b@gmail.com","name":"Sahand Kashani-Akhavan"},"message":"[cmos_sensor_input]\n\nIn order for (future) unpacking API to work with this component, it is necessary for the pack width to be at least 1-byte.","distinct":true,"url":"https://api.github.com/repos/sahandKashani/HDL-IP-cores/commits/62e22e78444ec36058945d1be5ee54ef654b5f23"},{"sha":"c4852cebb4d7ce5538411d4e1cd201cbfb794d39","author":{"email":"f29b71c75b9b1809bf1104c7050a1d956a5cd26b@gmail.com","name":"Sahand Kashani-Akhavan"},"message":"[cmos_sensor_input]\n\nInitial code for unpacking frames in memory.","distinct":true,"url":"https://api.github.com/repos/sahandKashani/HDL-IP-cores/commits/c4852cebb4d7ce5538411d4e1cd201cbfb794d39"},{"sha":"1a8470837d1320c79da11bad2e2ad3030be8672c","author":{"email":"f29b71c75b9b1809bf1104c7050a1d956a5cd26b@gmail.com","name":"Sahand Kashani-Akhavan"},"message":"[cmos_sensor_input]\nModified packer so the last word of the frame isn't padded with 0s at the beginning, but rather at the end. This will make the software APIs used for unpacking the results simpler.","distinct":true,"url":"https://api.github.com/repos/sahandKashani/HDL-IP-cores/commits/1a8470837d1320c79da11bad2e2ad3030be8672c"}]}