{"push_id":712641518,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"84a640b4306bdef4401b89bc1e2efc1c8c32d273","before":"43b980ba350b02c17e9a17e041321f56ec286da7","commits":[{"sha":"84a640b4306bdef4401b89bc1e2efc1c8c32d273","author":{"email":"df323289078b86880edcf3d30bec97d05343169a@gmail.com","name":"Xin Qian"},"message":"prepare pre signal processing","distinct":true,"url":"https://api.github.com/repos/BNLIF/wire-cell/commits/84a640b4306bdef4401b89bc1e2efc1c8c32d273"}]}