{"action":"created","issue":{"url":"https://api.github.com/repos/RIOT-OS/RIOT/issues/3692","labels_url":"https://api.github.com/repos/RIOT-OS/RIOT/issues/3692/labels{/name}","comments_url":"https://api.github.com/repos/RIOT-OS/RIOT/issues/3692/comments","events_url":"https://api.github.com/repos/RIOT-OS/RIOT/issues/3692/events","html_url":"https://github.com/RIOT-OS/RIOT/issues/3692","id":102525871,"number":3692,"title":"STM32L1 get_cpuid() hard faults when using a Cat. 1 or Cat. 2 STM32L1","user":{"login":"DipSwitch","id":476484,"avatar_url":"https://avatars.githubusercontent.com/u/476484?v=3","gravatar_id":"","url":"https://api.github.com/users/DipSwitch","html_url":"https://github.com/DipSwitch","followers_url":"https://api.github.com/users/DipSwitch/followers","following_url":"https://api.github.com/users/DipSwitch/following{/other_user}","gists_url":"https://api.github.com/users/DipSwitch/gists{/gist_id}","starred_url":"https://api.github.com/users/DipSwitch/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/DipSwitch/subscriptions","organizations_url":"https://api.github.com/users/DipSwitch/orgs","repos_url":"https://api.github.com/users/DipSwitch/repos","events_url":"https://api.github.com/users/DipSwitch/events{/privacy}","received_events_url":"https://api.github.com/users/DipSwitch/received_events","type":"User","site_admin":false},"labels":[{"url":"https://api.github.com/repos/RIOT-OS/RIOT/labels/arm","name":"arm","color":"dddddd"},{"url":"https://api.github.com/repos/RIOT-OS/RIOT/labels/bug","name":"bug","color":"fc2929"}],"state":"open","locked":false,"assignee":{"login":"thomaseichinger","id":56618,"avatar_url":"https://avatars.githubusercontent.com/u/56618?v=3","gravatar_id":"","url":"https://api.github.com/users/thomaseichinger","html_url":"https://github.com/thomaseichinger","followers_url":"https://api.github.com/users/thomaseichinger/followers","following_url":"https://api.github.com/users/thomaseichinger/following{/other_user}","gists_url":"https://api.github.com/users/thomaseichinger/gists{/gist_id}","starred_url":"https://api.github.com/users/thomaseichinger/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/thomaseichinger/subscriptions","organizations_url":"https://api.github.com/users/thomaseichinger/orgs","repos_url":"https://api.github.com/users/thomaseichinger/repos","events_url":"https://api.github.com/users/thomaseichinger/events{/privacy}","received_events_url":"https://api.github.com/users/thomaseichinger/received_events","type":"User","site_admin":false},"milestone":null,"comments":1,"created_at":"2015-08-22T11:17:21Z","updated_at":"2015-08-25T05:51:01Z","closed_at":null,"body":"From the STM32L1 Reference Manual (31.2 Unique device ID registers (96 bits)):\r\n\r\n    Base address: 0x1FF80050 for Cat.1 and Cat.2 devices and 0x1FF800D0 for Cat.3, Cat.4, Cat.5 and Cat.6 devices\r\n\r\nThree solutions possible for this problem:\r\n* Compile time: Via the linkerscript for the device (this I would prefer since this is the cleanest solution in my opinion)\r\n\r\n\t\tMEMORY\r\n\t\t{\r\n\t\t\trom (rx)        : ORIGIN = 0x08000000, LENGTH = 128K\r\n\t\t\tram (rw)        : ORIGIN = 0x20000000, LENGTH = 32K\r\n\t\t\t\r\n\t\t\tcpuid (r)\t\t: ORIGIN = 0x1FF80050, LENGTH = 12\r\n\t\t}\r\n\r\n\t\t_cpuid_address = ORIGIN(cpuid);\r\n\r\n\t\tINCLUDE cortexm_base.ld\r\n\r\n\r\n* Runtime: read the DBGMCU_IDCODE register (address: 0xe004 2000) and use something like:\r\n\r\n\t\t#define STM32L1_DEV_ID_CAT1                 0x416\r\n\t\t#define STM32L1_DEV_ID_CAT2                 0x429\r\n\t\t#define STM32L1_DEV_ID_CAT3                 0x427\r\n\t\t#define STM32L1_DEV_ID_CAT4                 0x436\r\n\t\t#define STM32L1_DEV_ID_CAT56                0x437\r\n\r\n\t\t#define STM32L1_CPUID_ADDR_CAT12            (0x1ff80050)\r\n\t\t#define STM32L1_CPUID_ADDR_CAT3456          (0x1ff800d0)\r\n\r\n\t\tvoid cpuid_get(void *id)\r\n\t\t{\r\n\t\t#define ST_DEV_ID                           ((DBGMCU->IDCODE) & DBGMCU_IDCODE_DEV_ID)\r\n\t\t\tuint32_t cpuid_address = (ST_DEV_ID == STM32L1_DEV_ID_CAT1 || ST_DEV_ID == STM32L1_DEV_ID_CAT2)\r\n\t\t\t\t\t\t\t\t\t\t? STM32L1_CPUID_ADDR_CAT12\r\n\t\t\t\t\t\t\t\t\t\t: STM32L1_CPUID_ADDR_CAT3456;\r\n\r\n\t\t\tmemcpy(id, (void *)(cpuid_address), CPUID_ID_LEN);\r\n\t\t#undef ST_DEV_ID\r\n\t\t}\r\n\r\n* Compile time: By setting an define an extra define in `Makefile.include` or in `board.h`\r\n    Here I would prefer an extra define in `Makefile.include` since you already place CPU information here.\r\n\r\n\t\texport CPU = stm32l1\r\n\t\texport CPU_MODEL = stm32l151rba\r\n\t\texport CPUID_LOCATION = 0x1ff80050"},"comment":{"url":"https://api.github.com/repos/RIOT-OS/RIOT/issues/comments/134488576","html_url":"https://github.com/RIOT-OS/RIOT/issues/3692#issuecomment-134488576","issue_url":"https://api.github.com/repos/RIOT-OS/RIOT/issues/3692","id":134488576,"user":{"login":"DipSwitch","id":476484,"avatar_url":"https://avatars.githubusercontent.com/u/476484?v=3","gravatar_id":"","url":"https://api.github.com/users/DipSwitch","html_url":"https://github.com/DipSwitch","followers_url":"https://api.github.com/users/DipSwitch/followers","following_url":"https://api.github.com/users/DipSwitch/following{/other_user}","gists_url":"https://api.github.com/users/DipSwitch/gists{/gist_id}","starred_url":"https://api.github.com/users/DipSwitch/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/DipSwitch/subscriptions","organizations_url":"https://api.github.com/users/DipSwitch/orgs","repos_url":"https://api.github.com/users/DipSwitch/repos","events_url":"https://api.github.com/users/DipSwitch/events{/privacy}","received_events_url":"https://api.github.com/users/DipSwitch/received_events","type":"User","site_admin":false},"created_at":"2015-08-25T05:51:01Z","updated_at":"2015-08-25T05:51:01Z","body":"Fixed with release d2cad2a"}}