{"push_id":894747373,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"90791f233e927096d99f14c64efd8055066f8ccd","before":"8d921c3b1aa7b5c3cf0035e8b99f4c9e13fd7aa7","commits":[{"sha":"3234a2ead0b8d75a95caa6e1519bbf22204e468a","author":{"email":"c5028ae03407bd8012a16f1f2957e10582f570b5@cs.cornell.edu","name":"Han Wang"},"message":"modelsim: allow generated systemverilog to be used in simulation\n\n--systemverilog can point to generated qsys directory\nmakefile will parse generated msim_setup.tcl and import\nsystemverilog simulation modules to library 'work'.\n\nthis help with using altera bfm models, now only\nbfm test_program, which is a sv module with no input and output\nis required to interact with bfm.\n\nsee tests/avalon_mm","distinct":true,"url":"https://api.github.com/repos/hanw/connectal/commits/3234a2ead0b8d75a95caa6e1519bbf22204e468a"},{"sha":"90791f233e927096d99f14c64efd8055066f8ccd","author":{"email":"c5028ae03407bd8012a16f1f2957e10582f570b5@cs.cornell.edu","name":"Han Wang"},"message":"tests used for developing avalon mm protocol against bfm model","distinct":true,"url":"https://api.github.com/repos/hanw/connectal/commits/90791f233e927096d99f14c64efd8055066f8ccd"}]}