{"push_id":548338093,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"d5e94fee52da08a17319cd3361722a3d51325c68","before":"db1a2795badaca3bf9c993bce82a15d4952fe2f8","commits":[{"sha":"d5e94fee52da08a17319cd3361722a3d51325c68","author":{"email":"477cf5b24d5c0cb561469a6faea86f0cd78ed1ab@sn.scee.net","name":"Andrea Di Biagio"},"message":"[X86][DAG] Disable target specific combine on INSERTPS dag nodes at -O0.\n\nThis patch disables target specific combine on X86ISD::INSERTPS dag nodes\nif optlevel is CodeGenOpt::None.\n\nThe backend currently implements a target specific combine rule that converts\na vector load used by an INSERTPS dag node into a scalar load plus a\nscalar_to_vector. This allows ISel to select a single INSERTPSrm instead of\ntwo instructions (i.e. a vector load plus INSERTPSrr).\n\nHowever, the existing target combine rule on INSERTPS nodes only works under\nthe assumption that ISel will always be able to match an INSERTPSrm. This is\nnot true in general at -O0, since the backend only allows folding a load into\nthe memory operand of an instruction if the optimization level is not\nCodeGenOpt::None.\n\nIn the example below:\n\n//\n__m128 test(__m128 a, __m128 *b) {\n  __m128 c = _mm_insert_ps(a, *b, 1 << 6);\n  return c;\n}\n//\n\nBefore this patch, at -O0, the backend would have canonicalized the load to 'b'\ninto a scalar load plus scalar_to_vector. Later on, ISel would have selected an\nINSERTPSrr leaving the insertps mask in an inconsistent state:\n\n  movss 4(%rdi), %xmm1\n  insertps  $64, %xmm1, %xmm0 # xmm0 = xmm1[1],xmm0[1,2,3].\n\nWith this patch, the backend avoids folding the vector load into the operand of\nthe INSERTPS. The new codegen at -O0 is:\n\n  movaps (%rdi), %xmm1\n  insertps  $64, %xmm1, %xmm0 # %xmm1[1],xmm0[1,2,3].","distinct":true,"url":"https://api.github.com/repos/chapuni/llvm-project/commits/d5e94fee52da08a17319cd3361722a3d51325c68"}]}