{"action":"created","issue":{"url":"https://api.github.com/repos/s5z/zsim/issues/49","labels_url":"https://api.github.com/repos/s5z/zsim/issues/49/labels{/name}","comments_url":"https://api.github.com/repos/s5z/zsim/issues/49/comments","events_url":"https://api.github.com/repos/s5z/zsim/issues/49/events","html_url":"https://github.com/s5z/zsim/issues/49","id":90484866,"number":49,"title":"How to differentiate memory controllers?","user":{"login":"Joyguo","id":7304069,"avatar_url":"https://avatars.githubusercontent.com/u/7304069?v=3","gravatar_id":"","url":"https://api.github.com/users/Joyguo","html_url":"https://github.com/Joyguo","followers_url":"https://api.github.com/users/Joyguo/followers","following_url":"https://api.github.com/users/Joyguo/following{/other_user}","gists_url":"https://api.github.com/users/Joyguo/gists{/gist_id}","starred_url":"https://api.github.com/users/Joyguo/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/Joyguo/subscriptions","organizations_url":"https://api.github.com/users/Joyguo/orgs","repos_url":"https://api.github.com/users/Joyguo/repos","events_url":"https://api.github.com/users/Joyguo/events{/privacy}","received_events_url":"https://api.github.com/users/Joyguo/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"milestone":null,"comments":1,"created_at":"2015-06-23T20:35:41Z","updated_at":"2015-07-05T18:08:49Z","closed_at":"2015-07-05T18:08:49Z","body":"I use ZSim + DRAMSim2 to simulate the heterogenous memory system, so there are two memory controllers with different configurations. I check ZSim source code, the DRAMSimAccEvent is only created in the DRAMSimMemory::access() which is called according to LLC's parent id? Per my understand, the only interface of DRAMSim2 is addTransaction which is encapsulate into DRAMSimMemory::enqueue. I don't what the DRAMSimMemory::access() is used for? I want to do some   scheduling between two controllers. Could you please help to explain how to differentiate memory controllers? By DRAMSimAccEvent or parent id or address? Thank you."},"comment":{"url":"https://api.github.com/repos/s5z/zsim/issues/comments/118644803","html_url":"https://github.com/s5z/zsim/issues/49#issuecomment-118644803","issue_url":"https://api.github.com/repos/s5z/zsim/issues/49","id":118644803,"user":{"login":"s5z","id":5559854,"avatar_url":"https://avatars.githubusercontent.com/u/5559854?v=3","gravatar_id":"","url":"https://api.github.com/users/s5z","html_url":"https://github.com/s5z","followers_url":"https://api.github.com/users/s5z/followers","following_url":"https://api.github.com/users/s5z/following{/other_user}","gists_url":"https://api.github.com/users/s5z/gists{/gist_id}","starred_url":"https://api.github.com/users/s5z/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/s5z/subscriptions","organizations_url":"https://api.github.com/users/s5z/orgs","repos_url":"https://api.github.com/users/s5z/repos","events_url":"https://api.github.com/users/s5z/events{/privacy}","received_events_url":"https://api.github.com/users/s5z/received_events","type":"User","site_admin":false},"created_at":"2015-07-05T18:08:49Z","updated_at":"2015-07-05T18:08:49Z","body":"When you create multiple memory controllers, zsim interleves memory addresses among them. See init.cpp:512 (SplitAddrMemory). By implementing something with similar functionality as SplitAddrMemoy, you can control the scheduling of memory across controllers."}}