{"push_id":543305044,"size":52,"distinct_size":5,"ref":"refs/heads/gpio","head":"e0f65b307138887107c084e3010da252b6c668ea","before":"87ca7caa7c6b5f98a672d89aa51f68f7bb936f51","commits":[{"sha":"501943696ea4f4194705b7449547fd3d66c13e97","author":{"email":"b6ffd6973e972cb999e8e535ab74da7fee0c035f@ingics.com","name":"Axel Lin"},"message":"spi: designware_spi: Fix detecting FIFO depth\n\nCurrent code tries to find the highest valid fifo depth by checking the value\nit wrote to DW_SPI_TXFLTR. There are a few problems in current code:\n1) There is an off-by-one in dws->fifo_len setting because it assumes the latest\n   register write fails so the latest valid value should be fifo - 1.\n2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary\n   to test fifo == 257. In the case fifo is 257, it means the latest valid\n   setting is fifo = 256. So after the for loop iteration, we should check\n   fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails.\nThis patch fixes above issues.\n\nSigned-off-by: Axel Lin <axel.lin@ingics.com>\nAcked-by: Stefan Roese <sr@denx.de>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/501943696ea4f4194705b7449547fd3d66c13e97"},{"sha":"741148625359ef92ad078b1096e3352cdb36dd0d","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi\n\nLinux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.\nFix the naming before we have to support both names.\n\nSigned-off-by: Marek Vasut <marex@denx.de>\nCc: Chin Liang See <clsee@opensource.altera.com>\nCc: Dinh Nguyen <dinguyen@opensource.altera.com>\nCc: Pavel Machek <pavel@denx.de>\nCc: Stefan Roese <sr@denx.de>\nCc: Vince Bridgers <vbridger@opensource.altera.com>\nReviewed-by: Stefan Roese <sr@denx.de>\nAcked-by: Pavel Machek <pavel@denx.de>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/741148625359ef92ad078b1096e3352cdb36dd0d"},{"sha":"653cda8f6605676504d03eb76f84932a20a6feb1","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"dt: socfpga: Replace num-chipselect with num-cs\n\nThis optional DT property is called 'num-cs', so repair the misnomers.\n\nSigned-off-by: Marek Vasut <marex@denx.de>\nCc: Chin Liang See <clsee@opensource.altera.com>\nCc: Dinh Nguyen <dinguyen@opensource.altera.com>\nCc: Pavel Machek <pavel@denx.de>\nCc: Stefan Roese <sr@denx.de>\nCc: Vince Bridgers <vbridger@opensource.altera.com>\nAcked-by: Pavel Machek <pavel@denx.de>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/653cda8f6605676504d03eb76f84932a20a6feb1"},{"sha":"a2358783875580fc7ad5e1554cb1a74a79360df6","author":{"email":"119ee8bfe841f60ca03ea257caa03354d3059526@freescale.com","name":"Peng Fan"},"message":"spi:fsl-quadspi support bank register read write\n\nTo support bigger than 16MB size qspi flashes, spi framework uses bank\nswitch to access higher bank or lower bank.\n\nIn this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR\nis initialized in LUT register with related pad and length configuration.\nqspi_op_pp is originally for page programming, this patch reuses this function\nfor bank register switch and renamed it with qspi_op_write.\n\nSince bank or EAR register is only 1 byte length, however original qspi_op_pp\nor now renamed qspi_op_write only support 4 bytes lenght as the access unit,\nthis will trigger data abort exception when access EAR or bank register.\nThis is because upper framework passes a 1 bytes pointer to qspi_op_write,\nhowever qspi_op_write treat it as an int pointer. This patch fixes this for\naccessing EAR or bank register.\n\nSigned-off-by: Peng Fan <Peng.Fan@freescale.com>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/a2358783875580fc7ad5e1554cb1a74a79360df6"},{"sha":"d87cbeccc54da2d39e1363e423953d8e24fb2008","author":{"email":"119ee8bfe841f60ca03ea257caa03354d3059526@freescale.com","name":"Peng Fan"},"message":"mx6sxsabresd: support qspi flash bigger than 16MB\n\nmx6sxsabresd revb board uses 32MB qspi flash, reva board uses 16MB qspi\nflash. Currently, the default supported platform is revb board.\n\nIf want to configure for reva board, just define CONFIG_MX6SX_SABRESD_REVA\nin mx6sxsabresd.h to support reva qspi flashes whose size is 16MB.\n\nSigned-off-by: Peng Fan <Peng.Fan@freescale.com>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/d87cbeccc54da2d39e1363e423953d8e24fb2008"},{"sha":"1dc7d00f2783991387fe715d61b50fe7b40fd30a","author":{"email":"b6ffd6973e972cb999e8e535ab74da7fee0c035f@ingics.com","name":"Axel Lin"},"message":"spi: cadence_qspi: Fix checking return value of fdt_first_subnode()\n\nfdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found.\n0 is supposed to be a valid offset returns from fdt_first_subnode().\n\nSigned-off-by: Axel Lin <axel.lin@ingics.com>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/1dc7d00f2783991387fe715d61b50fe7b40fd30a"},{"sha":"78c80114b5f7f31b4a1c09bfd0db61ded24b1f6b","author":{"email":"b6ffd6973e972cb999e8e535ab74da7fee0c035f@ingics.com","name":"Axel Lin"},"message":"spi: ftssp010_spi: Simplify code flow in ftssp010_[wait|wait_tx|wait_rx]\n\nNo functional change, just simplify the code a bit.\n\nSigned-off-by: Axel Lin <axel.lin@ingics.com>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/78c80114b5f7f31b4a1c09bfd0db61ded24b1f6b"},{"sha":"5e165b258f4231d8f9d07e773f19aaa57587f45a","author":{"email":"e4725b56ff6a11ac4309e92440cacb47b56011ab@jp.panasonic.com","name":"Masahiro Yamada"},"message":"ARM: UniPhier: fix SRAM size on support card\n\nThe max size of available memories on slot0 and slot1 is 32MB because\n - EA[25] signal is not output on the save-pin mode which is\n   used PH1-LD4 or later SoCs.\n - EA[25] signal is not connected by the limitation (or bug?) of\n   the PLD logic of DCC support card.\n\nSigned-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/5e165b258f4231d8f9d07e773f19aaa57587f45a"},{"sha":"2661dfd0046285e9007c1de126255bee11c0b8cd","author":{"email":"e4725b56ff6a11ac4309e92440cacb47b56011ab@jp.panasonic.com","name":"Masahiro Yamada"},"message":"ARM: UniPhier: enable output of system bus\n\nFor NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs,\nthe output of the system bus is disabled by default.\nIt must be enabled by software to have access to the system bus.\n\nSigned-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/2661dfd0046285e9007c1de126255bee11c0b8cd"},{"sha":"b4ad44baab713af371b1113dd63dd222ba73ba13","author":{"email":"e4725b56ff6a11ac4309e92440cacb47b56011ab@jp.panasonic.com","name":"Masahiro Yamada"},"message":"ARM: UniPhier: add UART initialization routine for low-level debug\n\nThe low-level debugging functions are useful to debug the early boot\nstage where the full UART driver is not available.\n\nUniPhier SoCs need to initialize the UART port 0 to use this feature.\nThe initialization routine is called at the very entry of the\nlowlevel_init().\n\nSigned-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/b4ad44baab713af371b1113dd63dd222ba73ba13"},{"sha":"b6b1b44586778885f37e1a2f2b17da7ddb04d565","author":{"email":"c28686e291da6ae2172ed112b2c872d861a0b865@nbsps.com","name":"Bill Pringlemeir"},"message":"scripts: fix binutils-version.sh for 'as' without a package.\n\nCommit 73c25753 fixed the common issue that binutil packages (tool/organization\nthat packaged or built the bin-utils) are included in brackets and this may\nfalsely be recognized as a version.  However, some tools do not provide a\n'package' and previously we add the 'Gnu assembler..' to the version.\n\nStrip out the '(package version text)' and then look for a ##.## string.\n\nSigned-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com>\nTested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>\nTested-by: Hans de Goede <hdegoede@redhat.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/b6b1b44586778885f37e1a2f2b17da7ddb04d565"},{"sha":"b349abbfe95972ee7770d8ffef0eaf45cc84f419","author":{"email":"2d324f4ca95610bde432fa2af2f28cd21110687d@free-electrons.com","name":"Maxime Ripard"},"message":"gpt: Fix the protective MBR partition size\n\nAccording to the UEFI Spec (Table 16, section 5.2.3 of the version 2.4 Errata\nB), the protective MBR partition record size must be set to the size of the\ndisk minus one, in LBAs.\n\nHowever, the current code was setting the size as the total number of LBAs on\nthe disk, resulting in an off-by-one error.\n\nThis confused the AM335x ROM code, and will probably confuse other tools as\nwell.\n\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/b349abbfe95972ee7770d8ffef0eaf45cc84f419"},{"sha":"f16d18627f6b9759b4c314f0ae66d1260572d2aa","author":{"email":"fe6d8aafe911b69ec3eecb89e7941038c0d25a22@sartura.hr","name":"Luka Perkov"},"message":"doc/gitmail-rc: fix whitespaces\n\nSigned-off-by: Luka Perkov <luka.perkov@sartura.hr>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/f16d18627f6b9759b4c314f0ae66d1260572d2aa"},{"sha":"5ea019616483bb5103ee57e576e9bc559ea537b5","author":{"email":"fe6d8aafe911b69ec3eecb89e7941038c0d25a22@sartura.hr","name":"Luka Perkov"},"message":"MAINTAINERS: add me as a co-maintainer of KIRKWOOD\n\nSigned-off-by: Luka Perkov <luka.perkov@sartura.hr>\nCC: Prafulla Wadaskar <prafulla@marvell.com>\nCC: Wolfgang Denk <wd@denx.de>\nAcked-by: Stefan Roese <sr@denx.de>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/5ea019616483bb5103ee57e576e9bc559ea537b5"},{"sha":"c36ecf3abfbc20719bbc7229c9a112e2e137a400","author":{"email":"119ee8bfe841f60ca03ea257caa03354d3059526@freescale.com","name":"Peng Fan"},"message":"i2c:mxc fix array size of i2c_data\n\nWe should not hardcode array size of i2c_data to 3. To CONFIG_FSL_LSCH3,\nthere are 4 i2c interface, but not 3. So the size of i2c_data array should\nbe calculated using \"ARRAY_SIZE(i2c_bases)\".\n\nTo avoid compile error, move i2c_bases before sram_data structure which\ncontains i2c_data array.\n\nSigned-off-by: Peng Fan <Peng.Fan@freescale.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/c36ecf3abfbc20719bbc7229c9a112e2e137a400"},{"sha":"8ed5e4ce0b9475f51f288409443b959b9a3a4f27","author":{"email":"679188261afeb60eb822cd934fd7b46a48ddd743@freescale.com","name":"Fabio Estevam"},"message":"mx25: Remove empty line after printing the reset cause\n\nCurrently there is an unneeded empty line after printing the reset cause:\n\nU-Boot 2015.01-rc4-00080-g0551a93 (Jan 06 2015 - 13:04:19)\n\nCPU:   Freescale i.MX25 rev1.2 at 399 MHz\nReset cause: POR\n\nBoard: MX25PDK\nI2C:   ready\nDRAM:  64 MiB\nMMC:   FSL_SDHC: 0\n\nRemove the extra \"\\n\" when printing the reset cause.\n\nSigned-off-by: Fabio Estevam <fabio.estevam@freescale.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/8ed5e4ce0b9475f51f288409443b959b9a3a4f27"},{"sha":"fa840b09216c6ea728240294b66d2d9ae42c36e1","author":{"email":"0c597d45353d741b4835ff5e56c2bc263abede5d@gmail.com","name":"Jeremiah Mahler"},"message":"doc: fix spelling errors in am335x/README\n\nFix several spelling errors and replace the invalid word\n\"architectured\" with \"designed\".\n\nSigned-off-by: Jeremiah Mahler <jmmahler@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/fa840b09216c6ea728240294b66d2d9ae42c36e1"},{"sha":"5f7f70c1718b74df12724724f6ec72fa1894d49c","author":{"email":"119ee8bfe841f60ca03ea257caa03354d3059526@freescale.com","name":"Peng Fan"},"message":"qspi:fsl implement AHB read\n\nThe QSPI controller in i.MX 6SoloX and Vybrid supports reading data using\nIP register and AHB bus.\n\nThe original driver only supports reading data from IP interface. The IC\nteam suggests to use AHB read which is faster then IP read. Using AHB read,\nwe can directly memcpy, a \"missed\" access to the buffer will cause the\ncontroller to clear the buffer and use the SEQID stored in bfgencr register\nto initiate a read from flash device.\n\nSince AHB bus is 64 bit width, we can not set MCR register using 32bit. In\norder to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little\nendian but not 32bit Little endia.\n\nIntroduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to\nuse AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it.\nActually if Vybrid is migrated to use AHB read, this option can be removed and\nIP read function can be discared. The reason to introduce this option\nis that only i.MX SOC is tested in my side, no Vybrid platform for me.\n\nIn spi_setup_slave, the original piece code to set AHB is deleted, since\nVybrid platform does not use this to intiate AHB read. Instead, add\nqspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB.\n\nSigned-off-by: Peng Fan <Peng.Fan@freescale.com>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/5f7f70c1718b74df12724724f6ec72fa1894d49c"},{"sha":"adc0fabfd9662fa690e866332cd4277351f991c4","author":{"email":"119ee8bfe841f60ca03ea257caa03354d3059526@freescale.com","name":"Peng Fan"},"message":"imx:mx6sxsabresd support qspi AHB read\n\nAdd CONFIG_SYS_FSL_QSPI_AHB in header file to enable AHB in driver.\nIn order to count the time, add CONFIG_CMD_TIME.\n\nUsing AHB read can improve the the read speed about 30%.\n\nAHB read:\n=> time sf read 0x8f800000 0 100000\nSF: 1048576 bytes @ 0x0 Read: OK\ntime: 0.174 seconds\n\n=> time sf read 0x8f800000 1000000 100000\nSF: 1048576 bytes @ 0x1000000 Read: OK\ntime: 0.174 seconds\n\nIP read:\n=> time sf read 0x8f800000 0 100000\nSF: 1048576 bytes @ 0x0 Read: OK\ntime: 0.227 seconds\n\n=> time sf read 0x8f800000 1000000 100000\nSF: 1048576 bytes @ 0x1000000 Read: OK\ntime: 0.227 seconds\n\nNote:\nQuad read is not supported in driver, now. In my side, using AHB and Quad read\ncan achieve about 16MB/s. Anyway, I have plan to reimplement the driver using\nDTB and DM, then make the code cleaner and more feature can be added.\n\nSigned-off-by: Peng Fan <Peng.Fan@freescale.com>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/adc0fabfd9662fa690e866332cd4277351f991c4"},{"sha":"906d6fe3033910a5eca72ef6fc9b47a957b113e5","author":{"email":"679188261afeb60eb822cd934fd7b46a48ddd743@freescale.com","name":"Fabio Estevam"},"message":"mx25: Fix boot hang by avoiding vector relocation\n\nSince commit 3ff46cc42b9d73d0 (\"arm: relocate the exception vectors\") mx25pdk\nhangs like this:\n\nCPU:   Freescale i.MX25 rev1.2 at 399 MHz\nReset cause: WDOG\nBoard: MX25PDK\nI2C:   ready\nDRAM:  64 MiB\n(hangs)\n\nAdd a specific relocate_vectors macro that skips the vector relocation, as the\ni.MX25 SoC does not provide RAM at the high vectors address (0xFFFF0000), and\n(0x00000000) maps to ROM.\n\nThis allows mx25 to boot again.\n\nAcked-By: Bill Pringlemeir <bpringlemeir@nbsps.com>\nSigned-off-by: Fabio Estevam <fabio.estevam@freescale.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/906d6fe3033910a5eca72ef6fc9b47a957b113e5"}]}