{"push_id":728839303,"size":87,"distinct_size":70,"ref":"refs/heads/wip/siglesias/ARB_shader_storage_buffer_object-v3.3","head":"0ebc55f39aed838734783e4378af648b836ce774","before":"c96805eb99fc497d92a0f755c86cc11283658f9c","commits":[{"sha":"7b9ebf879b6f35038996805a641667f00d93c4b7","author":{"email":"81ef2ef7cd3a859923573a7bb84652871c617f7d@lse.epita.fr","name":"Renaud Gaubert"},"message":"glsl: avoid compiler's segfault when processing operators with void arguments\n\nThis is done by returning an rvalue of type void in the\nast_function_expression::hir function instead of a void expression.\n\nThis produces (in the case of the ternary) an hir with a call\nto the void returning function and an assignment of a void variable\nwhich will be optimized out (the assignment) during the optimization\npass.\n\nThis fix results in having a valid subexpression in the many\ndifferent cases where the subexpressions are functions whose\nreturn values are void.\n\nThus preventing to dereference NULL in the following cases:\n  * binary operator\n  * unary operators\n  * ternary operator\n  * comparison operators (except equal and nequal operator)\n\nEqual and nequal had to be handled as a special case because\ninstead of segfaulting on a forbidden syntax it was now accepting\nexpressions with a void return value on either (or both) side of\nthe expression.\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85252\n\nSigned-off-by: Renaud Gaubert <renaud@lse.epita.fr>\nReviewed-by: Gabriel Laskar <gabriel@lse.epita.fr>\nReviewed-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/7b9ebf879b6f35038996805a641667f00d93c4b7"},{"sha":"7e0180d57d330bd8d3047e841086712376b2a1cc","author":{"email":"bbac3597f01acc7d927683e64659598a4321d5b2@sigluy.net","name":"EdB"},"message":"clover: little OpenCL status code logging clean\n\ns/build_error/compile_error in order to match the stored OpenCL status code.\nMake program::build catch and log every OpenCL error.\nMake tgsi error triggering uniform with the llvm one.\n\nReviewed-by: Francisco Jerez <currojerez@riseup.net>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/7e0180d57d330bd8d3047e841086712376b2a1cc"},{"sha":"af768922cafa3eb3e78a2fdfee90380a74c79460","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/gen9: Use custom MOCS entries set up by the kernel.\n\nInstead of relying on hardware defaults the i915 kernel driver is\ngoing program custom MOCS tables system-wide on Gen9 hardware.  The\n\"WT\" entry previously used for renderbuffers had a number of problems:\nIt disabled caching on eLLC, it used a reserved L3 cacheability\nsetting, and it used to override the PTE controls making renderbuffers\nalways WT on LLC regardless of the kernel's setting.  Instead use an\nentry from the new MOCS tables with parameters: TC=LLC/eLLC, LeCC=PTE,\nL3CC=WB.\n\nThe \"WB\" entry previously used for anything other than renderbuffers\nhas moved to a different index in the new MOCS tables but it should\nhave the same caching semantics as the old entry.\n\nEven though the corresponding kernel change (\"drm/i915: Added\nProgramming of the MOCS\") is in a way an ABI break it doesn't seem\nnecessary to check that the kernel is recent enough because the change\nshould only affect Gen9 which is still unreleased hardware.\n\nv2: Update MOCS values for the new Android-incompatible tables\n    introduced in v7 of the kernel patch.\n\nCc: 10.6 <mesa-stable@lists.freedesktop.org>\nReference: http://lists.freedesktop.org/archives/intel-gfx/2015-July/071080.html\nReviewed-by: Ben Widawsky <ben@bwidawsk.net>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/af768922cafa3eb3e78a2fdfee90380a74c79460"},{"sha":"26222932c013da3688e39dc831179659cc65c39a","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"gallium: add PIPE_CAP_MAX_SHADER_PATCH_VARYINGS\n\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/26222932c013da3688e39dc831179659cc65c39a"},{"sha":"f9f79d29ce75c681c46bdbac5aa3f19ee1adb93b","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"gallium: add BIND flags for R/W buffers and images\n\nPIPE_CAPs and TGSI support will be added later. The TGSI support should be\nstraightforward. We only need to split TGSI_FILE_RESOURCE into TGSI_FILE_IMAGE\nand TGSI_FILE_BUFFER, though duplicating all opcodes shouldn't be necessary.\n\nThe idea is:\n* ARB_shader_image_load_store should use set_shader_images.\n* ARB_shader_storage_buffer_object should use set_shader_buffers(slots 0..M-1)\n  if M shader storage buffers are supported.\n* ARB_shader_atomic_counters should use set_shader_buffers(slots M..N)\n  if N-M+1 atomic counter buffers are supported.\n\nPIPE_CAPs can describe various constraints for early DX11 hardware.\n\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/f9f79d29ce75c681c46bdbac5aa3f19ee1adb93b"},{"sha":"b73bec0ecd43861337daf9663e242d2b44f36dbd","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"gallium: add new limits for shader buffers and images\n\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/b73bec0ecd43861337daf9663e242d2b44f36dbd"},{"sha":"05a12c53a308965aba1c00f0caf36d8e0f32e035","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"gallium: add interface for writable shader images\n\nPIPE_CAPs will be added some other time.\n\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/05a12c53a308965aba1c00f0caf36d8e0f32e035"},{"sha":"8fba933ca2dd3c3487281135a9063b6ca9bed359","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"gallium: add interface for writable shader buffers\n\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/8fba933ca2dd3c3487281135a9063b6ca9bed359"},{"sha":"3ee2daf23dc91b8dfc017b5c89c10ab1376ba4df","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965: Implement b2f and b2i using negation.\n\nBooleans are represented as 0/-1 on modern hardware which means we can\njust negate them to convert them into a numeric type.  Negation has\nthe benefit that it can be implemented using a source modifier which\ncan easily be propagated into some other instruction.  shader-db\nresults on HSW:\n\ntotal instructions in shared programs: 6349082 -> 6346693 (-0.04%)\ninstructions in affected programs:     40948 -> 38559 (-5.83%)\nhelped:                                123\nHURT:                                  1\nGAINED:                                1\nLOST:                                  0\n\nReviewed-by: Matt Turner <mattst88@gmail.com>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/3ee2daf23dc91b8dfc017b5c89c10ab1376ba4df"},{"sha":"b00cd6e4a0f9a84d514f428428be348900236e2e","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965: Implement nir_op_uadd_carry and _usub_borrow without accumulator.\n\nThis gets rid of two no16() fall-backs and should allow better\nscheduling of the generated IR.  There are no uses of usubBorrow() or\nuaddCarry() in shader-db so no changes are expected.  However the\n\"arb_gpu_shader5/execution/built-in-functions/fs-usubBorrow\" and\n\"arb_gpu_shader5/execution/built-in-functions/fs-uaddCarry\" piglit\ntests go from 40 to 28 instructions.  The reason is that the plain ADD\ninstruction can easily be CSE'ed with the original addition, and the\nb2i negation can easily be propagated into the source modifier of\nanother instruction, so effectively both operations are performed with\njust one instruction.\n\nv2: Rely on carry_to_arith() and borrow_to_arith() to lower these\n    (Ilia Mirkin).\n\nReviewed-by: Matt Turner <mattst88@gmail.com>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/b00cd6e4a0f9a84d514f428428be348900236e2e"},{"sha":"4bddd82bf3dae44c2b75cef34e9e85e15d63df7f","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/fs: Factor out universally broken calculation of the register component size.\n\nThis in principle simple calculation was being open-coded in a number\nof places (in a series I haven't yet sent for review there will be a\ncouple more), all of them were subtly broken in one way or another:\nNone of them were handling the HW_REG case correctly as pointed out by\nConnor, and fs_inst::regs_read() was handling the stride=0 case rather\nnaively.  This patch solves both problems and factors out the\ncalculation as a new fs_reg method.\n\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/4bddd82bf3dae44c2b75cef34e9e85e15d63df7f"},{"sha":"51e8d549e110f86cb7107cf712843aebd956fb9a","author":{"email":"cf148a1c890adeeb4308e9e093ed95f3d05c8318@intel.com","name":"Ben Widawsky"},"message":"i965: Push miptree tiling request into flags\n\nWith the last few patches a way was provided to influence lower layer miptree\nlayout and allocation decisions via flags (replacing bools). For simplicity, I\nchose not to touch the tiling requests because the change was slightly less\nmechanical than replacing the bools.\n\nThe goal is to organize the code so we can continue to add new parameters and\ntiling types while minimizing risk to the existing code, and not having to\nconstantly add new function parameters.\n\nv2: Rebased on Anuj's recent Yf/Ys changes\nFix non-msrt MCS allocation (was only happening in gen8 case before)\n\nv3: small fix in assertion requested by Chad\n\nSigned-off-by: Ben Widawsky <ben@bwidawsk.net>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v2)\nReviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (v2)\nReviewed-by: Chad Versace <chad.versace@intel.com> (v2)","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/51e8d549e110f86cb7107cf712843aebd956fb9a"},{"sha":"ef42352ff4e1feeea7338db73f540038c6755472","author":{"email":"cf148a1c890adeeb4308e9e093ed95f3d05c8318@intel.com","name":"Ben Widawsky"},"message":"Revert \"i965: Push miptree tiling request into flags\"\n\nThis reverts commit 51e8d549e110f86cb7107cf712843aebd956fb9a.","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/ef42352ff4e1feeea7338db73f540038c6755472"},{"sha":"3a31876600cb5c4d90c998ecb5635c602eeb2bd1","author":{"email":"cf148a1c890adeeb4308e9e093ed95f3d05c8318@intel.com","name":"Ben Widawsky"},"message":"i965: Push miptree tiling request into flags\n\nWith the last few patches a way was provided to influence lower layer miptree\nlayout and allocation decisions via flags (replacing bools). For simplicity, I\nchose not to touch the tiling requests because the change was slightly less\nmechanical than replacing the bools.\n\nThe goal is to organize the code so we can continue to add new parameters and\ntiling types while minimizing risk to the existing code, and not having to\nconstantly add new function parameters.\n\nv2: Rebased on Anuj's recent Yf/Ys changes\nFix non-msrt MCS allocation (was only happening in gen8 case before)\n\nv3: small fix in assertion requested by Chad\n\nv4: Use parens to get the order right from v3.\n\nSigned-off-by: Ben Widawsky <ben@bwidawsk.net>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/3a31876600cb5c4d90c998ecb5635c602eeb2bd1"},{"sha":"4b17f0d9f58637300b0748d1fb702a7e4d51979f","author":{"email":"bd2562f754ec92342f93f61c25d731e290a2ffa8@whitecape.org","name":"Kenneth Graunke"},"message":"program: Allow redundant OPTION ARB_fog_* directives.\n\nA fragment program from \"Pixel Piracy\" contains redundant OPTION\ndirectives:\n\n!!ARBfp1.0\nOPTION ARB_precision_hint_fastest;\nOPTION ARB_fog_exp2;\nOPTION ARB_precision_hint_fastest;\nOPTION ARB_fog_exp2;\n...\n\nWe already allow redundant ARB_precision_hint_fastest directives, but\ndisallow the redundant (yet consistent) ARB_fog_exp2 directives, failing\nto compile the program.\n\nThe specification seems to contradict itself - the main text says that\nonly one fog application option may be specified, but then backpedals,\nindicating the intent is to disallow /contradictory/ flags.  One of the\nissues suggests that specifying contradictory ones is stupid, but\nallowed, and only the last one should take effect.\n\nAccepting multiple redundant (but consistent) directives seems harmless,\nand like a reasonable interpretation of the specification.  It also\nfixes a fragment program found in the wild.\n\nCc: mesa-stable@lists.freedesktop.org\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/4b17f0d9f58637300b0748d1fb702a7e4d51979f"},{"sha":"7e337859ff98a0caf00fd201a5389933d42d0baa","author":{"email":"a79006884ba9cf5f4f7fcbb92a15b208780d8c97@intel.com","name":"Jordan Justen"},"message":"i965/cs: Return 1 for regs_read on CS_OPCODE_CS_TERMINATE\n\nThis prevents an assertion failure in brw_fs_live_variables.cpp,\nfs_live_variables::setup_one_read: Assertion `var < num_vars' failed.\n\nSigned-off-by: Jordan Justen <jordan.l.justen@intel.com>\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/7e337859ff98a0caf00fd201a5389933d42d0baa"},{"sha":"01cdbba341b47972a743e7f192d3554010d0da84","author":{"email":"a79006884ba9cf5f4f7fcbb92a15b208780d8c97@intel.com","name":"Jordan Justen"},"message":"i965/cs: Use dispatch width of 8 for cs terminate payload setup\n\nThis prevents an assertion failure in brw_fs_live_variables.cpp,\nfs_live_variables::setup_one_write: Assertion `var < num_vars' failed.\n\nSigned-off-by: Jordan Justen <jordan.l.justen@intel.com>\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>","distinct":false,"url":"https://api.github.com/repos/samuelig/mesa/commits/01cdbba341b47972a743e7f192d3554010d0da84"},{"sha":"ca874e2811723fd3fb6dba06a1fff0d132397cb0","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/fs: Fix register coalesce not to lose track of the second half of 16-wide moves.\n\nFixes rewrite by the register coalesce pass of references to\nindividual halves of 16-wide coalesced registers.","distinct":true,"url":"https://api.github.com/repos/samuelig/mesa/commits/ca874e2811723fd3fb6dba06a1fff0d132397cb0"},{"sha":"d64210f3021f98c5ebd072546a4147f9504931c3","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965: Add register constructors taking a backend_reg as argument.\n\nThese are going to be used to convert an array_reg (chunk of the\nregister space without fancy regioning parameters) back to a normal\nFS/VEC4 register.","distinct":true,"url":"https://api.github.com/repos/samuelig/mesa/commits/d64210f3021f98c5ebd072546a4147f9504931c3"},{"sha":"e332816cc573ac09fed02318f557816d2bef7bfd","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/vec4: Make src_reg conversion constructor from dst_reg implicit.\n\nThe dst_reg to src_reg conversion is fairly safe since\n430c6bf70e48c08ba4dc9e00f2b88e2230793010.  No information is lost and\nOP(dst, src_reg(dst), src1) does what one would expect -- This seems\njust annoying now.  The implicit conversion allows you to declare\ntemporaries that are both written and read from as dst_reg and have\nthem conveniently converted to src_reg when they are used.  They also\navoid redundant expressions like 'negate(src_reg(tmp))',\n'swizzle(src_reg(tmp), ...)' or 'src_vector(src_reg(tmp), ...)' (the\nlatter function will be defined in a future commit).\n\nThe src_reg to dst_reg conversion is kept explicit because it does\nlose component ordering information.","distinct":true,"url":"https://api.github.com/repos/samuelig/mesa/commits/e332816cc573ac09fed02318f557816d2bef7bfd"}]}