{"push_id":638563854,"size":18,"distinct_size":0,"ref":"refs/heads/master","head":"e71aa3d8d0dcc3413be9d624c38bd6d2233a5bb6","before":"49ad9b7dd401fbc5f8e63bf87a39fa80096e5c6a","commits":[{"sha":"0df83adc377d3bacc602f9b48ef1dd527e729e19","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[DOCS] Add release notes v0.2.6 release\n\nThis patch is part of v0.2.6 release preparation.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/0df83adc377d3bacc602f9b48ef1dd527e729e19"},{"sha":"6615f3c991a5e494c245e8903bfeda59ea507ccb","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[DOCS] Prefer Linaro toolchain over kernel.org toolchain\n\nThe kernel.org is vanilla GCC without libc but its not actively\nmaintained hence currently it is stuck at GCC 4.6 for ARM\ncross-toolchain. The GCC 4.6 does not have support for newer\nARM CPUs with virtualization extension and for Cortex-A15 we\nhave to use -mcpu=cortex-a15 switch to enable newer instruction\non ARMv7ve.\n\nThe Linaro toolchains are not excatly proprietary because its\nmostly vanilla GCC with few additional patches from mainline\nGCC. The good part about Linaro toolchains is that generally\nits quite latest GCC with variety of flavours aarch64-linux,\narm-linux-gnueabi, arm-linux-gnueabihf, arm-none-eabi, etc.\nCurrently, the latest Linaro toolchain binary release 14.11\nprovides cross-toolchains based on GCC 4.9. The GCC 4.9 defines\nnew -march=armv7ve switch for ARM CPUs with virtualization\nextensions (i.e. ARMv7ve).\n\nThis patch updates our documentation to prefer Linaro toolchain\n(particularly arm-linux-gnueabi flavour) wherever possible.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/6615f3c991a5e494c245e8903bfeda59ea507ccb"},{"sha":"9f800d7cff6801f8e94f6fa84d8bcacf7e4d4c18","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[CORE] vmm_scheduler: Skip PAUSED->PAUSED state transitions\n\nOn SMP host, some VCPU running on Host CPU A might try to\nPAUSE another VCPU running on Host CPU B multiple times (e.g.\nsomeone trying run \"vcpu pause\" command multiple times). This\nshould be allowed because PAUSED->PAUSED transition means\nVCPU is already PAUSED and we dont need to do anything except\nignoring the request.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/9f800d7cff6801f8e94f6fa84d8bcacf7e4d4c18"},{"sha":"13b4a5160a0f9fa085e7b870a157ef4c174444a8","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[TESTS] arm32: Disable build-id at linktime for basic firmware\n\nMany ARM toolchains by default insert build-id in .note section\nat linktime hence disable build-id explicitly.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/13b4a5160a0f9fa085e7b870a157ef4c174444a8"},{"sha":"d49761fd80f06f790fa214f3780149d9c9622dee","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[DRIVERS] sdhci: Fix card hot-plugging for PIO mode\n\nThis patch fixes card hot-plugging for PIO mode and it also\nfixes sdhci_get_cd() for broken card-detection case.\n\nThe patch is primarily aimed at fixing SDHCI for BCM2835\nSOC (i.e. Raspberry Pi).\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/d49761fd80f06f790fa214f3780149d9c9622dee"},{"sha":"ba1e52c9d2f276928c3e903e923a7a0b9e781fd5","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[CORE] vmm_scheduler: Skip RESET->RESET state transitions\n\nJust like PAUSED->PAUSED, we also skip RESET->RESET state\ntransition.\n\nThe rational here is that we can have SMP Guest that allows\nsecondary VCPUs to remain in RESET state until explicitly\nkicked by Guest Linux (using PSCI call on ARM or using some\nBIOS call on x86). If such a Guest is resetted without\nkicking secondary VCPUs then we have RESET->RESET state\ntransition for secondary VCPUs. The Virt-v7 or Virt-v8\nguest of arm32ve and arm64 port are good example of such\nSMP Guest.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/ba1e52c9d2f276928c3e903e923a7a0b9e781fd5"},{"sha":"a6c4fcf652accbf52d731ad6a4c14de0bcdd0d64","author":{"email":"701a6aa18e04e30404e33567b7d56afa602fabad@openwide.fr","name":"Julien Viard de Galbert"},"message":"[CORE] witespace & comment fix\n\nOnly some rewriting useful for next patches but not merged\nin for better readability.\n\nSigned-off-by: Julien Viard de Galbert <julien.viarddegalbert@openwide.fr>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/a6c4fcf652accbf52d731ad6a4c14de0bcdd0d64"},{"sha":"0109954223d284f2fd8999b72001e221bcb4691e","author":{"email":"701a6aa18e04e30404e33567b7d56afa602fabad@openwide.fr","name":"Julien Viard de Galbert"},"message":"[CORE] balancing PAUSE<->READY transitions\n\nThis patch is about balancing PAUSE->READY and\nREADY->PAUSE transitions using signed counter\nin VCPU. This counter is not required to be atomic\nbecause its protected by vcpu->sched_lock.\n\nSigned-off-by: Julien Viard de Galbert <julien.viarddegalbert@openwide.fr>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/0109954223d284f2fd8999b72001e221bcb4691e"},{"sha":"7aa7cff3c21996d8f0ba35c77cd650dd7d8c1ea0","author":{"email":"701a6aa18e04e30404e33567b7d56afa602fabad@openwide.fr","name":"Julien Viard de Galbert"},"message":"[CORE] Refactor vmm_waitqueue\n\nCall vmm_manager_vcpu_resume from one place and always with\nirq disabled and lock taken.\n\nSigned-off-by: Julien Viard de Galbert <julien.viarddegalbert@openwide.fr>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/7aa7cff3c21996d8f0ba35c77cd650dd7d8c1ea0"},{"sha":"007283d4283cff42b065452778cc69290abd2c03","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[CORE] vmm_devdrv: Fix deferred_probe_work_func() and deferred_probe_invoke()\n\nThis patch does following fixes to deferred probing:\n1. The deferred_probe_work_func() should only probe a device once\n   in because it is possible that a device again deferred in while\n   probing from deferred_probe_work_func().\n2. The deferred_probe_invoke() should only schedule work if its not\n   in-progress. Latest vmm_workqueue implementation allows vmm_work\n   to be re-scheduled while it's running.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/007283d4283cff42b065452778cc69290abd2c03"},{"sha":"539aee71260aa2e6deee463c4ffeab6962d3efba","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[CORE] Don't BUG_ON() irqs disabled for sleepable locking primitives\n\nThe Linux drivers freely call mutex lock API with irqs disabled,\nas example consider below stack trace from hackberry:\nethernet@01c0b000: could not find pctldev for node emac0@0, deferring probe\nBug in mutex_lock_common() at /home/anup/Development/xvisor-next/core/vmm_mutex.c:108\n0xFF02B488 mutex_lock_common+0xc8/0xfc\n0xFF0671C4 pinctrl_remove_gpio_range+0x1c/0x50\n0xFF0A3548 gpiochip_remove_pin_ranges+0x50/0x6c\n0xFF0A3594 gpiochip_remove+0x30/0x138\n0xFF06B9E4 sunxi_pinctrl_probe+0x494/0x784\n0xFF01BD64 __bus_probe_device_driver+0x98/0xe4\n0xFF01C080 __bus_probe_this_device+0x54/0x7c\n0xFF01D5AC vmm_devdrv_register_device+0x218/0x228\n0xFF01D634 devdrv_probe+0x78/0xe0\n0xFF01D64C devdrv_probe+0x90/0xe0\n0xFF1017C4 arch_board_final_init+0x2c/0xa8\n0xFF015BE8 system_init_work+0x250/0x2e0\nPlease reset the system ...\n\nFor now, we just remove BUG_ON() from all sleepable locking primitives.\n\nIn future, we might allow threads (or Orphan VCPUs) to be preempted with\nirqs disabled.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/539aee71260aa2e6deee463c4ffeab6962d3efba"},{"sha":"df09f81d477979fd7c0d0bae29637b718bfbcd5d","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[ARM] arm32: Even ARMv6 CPUs can support security extensions\n\nThe ARMv6 CPUs can also support security extensions. If we have\nARMv6 CPU with security extension then we will have to programme\nVBAR register for using low exception vector.\n\nThis patch is primarily targeted to fix Xvisor for latest u-boot\non Raspberry Pi.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/df09f81d477979fd7c0d0bae29637b718bfbcd5d"},{"sha":"a748bf747400192646ed4697f55ffe25d02c8e15","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[CORE] vmm_guest_aspace: Zero-out alloced ROM regions at creation time\n\nROM regions are persistent memory from guest perspective (e.g. NOR\nflash). This means ROM regions should have predictable contents\neven if they are created at runtime. If a user creates ROM region\nover reserved host memory then it is his/her responsiblity to make\nsure unused parts or ROM region are zeroed. On the other hand, if\na user creates alloced ROM region then it is responsiblity of guest\naspace to zero-out alloced ROM region.\n\nThis patch make sures that we zero-out alloced ROM regions at guest\ncreation time. As a result of this patch, initramfs loading for Guest\nLinux on ARM fast model and ARM Foundation v8 model is fixed. With this\npatch, its not mandatory to use initrd for Guest Linux on Xvisor.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/a748bf747400192646ed4697f55ffe25d02c8e15"},{"sha":"831bf61c36161dc070d0ff687dd4d8f14df529c9","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[TESTS] arm32: arm64: Update busybox READMEs for using CPIO based RootFS\n\nUsing CPIO based RootFS has following advantages over EXT2 INITRD:\n1. The CPIO RootFS image is generally smaller than EXT2 RootFS image\n2. It boots faster compared to EXT2 RootFS image\n3. The EXT2 RootFS image cannot grow at runtime where as CPIO based\nRootFS can grow because its basically initramfs\n4. Most folks in Linux user community prefer CPIO initramfs over\nfilesystem based INITRD.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/831bf61c36161dc070d0ff687dd4d8f14df529c9"},{"sha":"f2a2dcad07c80f90b472eeb186a41135a59473c9","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[CORE] Fix vmm_devtree_extirq_xxx() APIs\n\nThis patch fixes vmm_devtree_extirq_xxx() APIs to make them more\ngeneric and also consider host interrupts.\n\nThe patch also renames all vmm_devtree_extirq_xxx() APIs to\nvmm_devtree_irq_xxx(). This indicates that APIs should eventually\nwork for both host irqs and host extended irqs.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/f2a2dcad07c80f90b472eeb186a41135a59473c9"},{"sha":"5ed1363ee715182680c0e35468748b651c819702","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[ARM] arm32: Fix irq_of_parse_map() for sunxi pinctrl driver\n\nThe sunxi pinctrl driver uses irq_of_parse_map() to determine\nhost interrupt number.\n\nThis in-turn leads to vmm_devtree_irq_parse_map() API call\nwhich looks for \"interrupt-parent\" in sunxi pinctrl node\nhence this patch.\n\nEventually, we will move all drivers to directly or indirectly\nuse vmm_devtree_irq_parse_map() API.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/5ed1363ee715182680c0e35468748b651c819702"},{"sha":"fbfe6dca0076865242bb73389242aa1eb0e524da","author":{"email":"280aeee52cad191826121dac63d7eb9fbb2c9990@tribudubois.net","name":"Jean-Christophe Dubois"},"message":"[DOCS] vexpress-a9: fix qemu command.\n\nUse Vexpress-a9 DTB tree instead of realview-pb-a8\n\nSigned-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/fbfe6dca0076865242bb73389242aa1eb0e524da"},{"sha":"e71aa3d8d0dcc3413be9d624c38bd6d2233a5bb6","author":{"email":"8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","name":"Anup Patel"},"message":"[CORE] Bind pin controller only on platform devices.\n\nSigned-off-by: Jimmy Durand Wesolowski <jimmy.durand-wesolowski@openwide.fr>\nSigned-off-by: Anup Patel <anup@brainfault.org>","distinct":false,"url":"https://api.github.com/repos/hschauhan/xvisor-x86_64/commits/e71aa3d8d0dcc3413be9d624c38bd6d2233a5bb6"}]}