{"push_id":831341724,"size":14,"distinct_size":1,"ref":"refs/heads/bsekisser-master-core-flat-inst-skip","head":"c6cf18c8f74e4649d0d0c6dd5a13b8735d8f5b44","before":"c3c29fdc1093211d28d07fffd24678daa84b246b","commits":[{"sha":"f2ebab47d69ee01d4c9f2cc04496e71665a8ab76","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: fixup missing dependancy from r16 commit\n\nseveral commits were pushed to a branch which I later split...\none commit had a dependency I missed which this fixes.\n\n\tmodified:   sim/sim_core.c\n\t\tfix missing dependance in MOVW instruction.","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/f2ebab47d69ee01d4c9f2cc04496e71665a8ab76"},{"sha":"2062c2ddea13488d8d766331c5432b5bb2ae1fea","author":{"email":"c2208abde9668e8e9815c3690855edd1e63abeac@pollet.net","name":"Michel Pollet"},"message":"Merge pull request #141 from bsekisser/bsekisser-master-core-access-r16-fixup\n\ncore: fixup missing dependancy from r16 commit","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/2062c2ddea13488d8d766331c5432b5bb2ae1fea"},{"sha":"1927cb22bf8d1db10511ad45bd7b1ec4ce8c7ebf","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: change to use 16 bit data accessor function\n\n\tmodified:   sim/sim_core.c\n\t\tadded: _avr_data_read16le\n\t\tchange: \"avr->data[addr] | (avr->data[addr + 1] << 8)\"\n\t\tto: \"_avr_data_read16le(avr, addr)\"","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/1927cb22bf8d1db10511ad45bd7b1ec4ce8c7ebf"},{"sha":"df585ad9e9c2b8ab8f5767efda08afc559ff4afd","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: ammend _avr_data_read16le and _avr_flash_read16\n\n* movw modified to use _avr_data_read16le\n\n\tmodified:   sim/sim_core.c","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/df585ad9e9c2b8ab8f5767efda08afc559ff4afd"},{"sha":"914d795fc26add600303933242f55005da1d9f45","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: separate instructions from decoder -- simple ops\n\nbegin process of flattening decoder by starting to lay out some basic\nframework and separating out instruction code into their own functions\n\n\tmodified:   sim/sim_core.c","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/914d795fc26add600303933242f55005da1d9f45"},{"sha":"d9601e086322fffad802288229cca85fcdab9a25","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: flatten d5r5 group 0\n\ncpc, add and sbc moved out of decoder.\n\n\tmodified:   sim/sim_core.c","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/d9601e086322fffad802288229cca85fcdab9a25"},{"sha":"4c234d79806a037dce1951070cb21397ae23a12a","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: flatten d5r5 group 1\n\nadc/addc, cp, cpse brought out of decoder.\n\n* several optimizations were made, relying on dead code elimination.\n* several optimizations were made to debug statements from original submission.\n\n\tmodified:   sim/sim_core.c","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/4c234d79806a037dce1951070cb21397ae23a12a"},{"sha":"2cd6e2545cbacc691cb4777facc192d3c706128c","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: flatten d5r5 group 2\n\n* groups 1 and 2 melded together\n* debug statement modified to use existing register data\n\n\tmodified:   sim/sim_core.c","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/2cd6e2545cbacc691cb4777facc192d3c706128c"},{"sha":"5b6e1d51e46fd90b08253c7212c18028b581e160","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: flatten mul instruction\n\nshould be final commit for the d5r5 group.\n\n\tmodified:   sim/sim_core.c","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/5b6e1d51e46fd90b08253c7212c18028b581e160"},{"sha":"dfbce669d3e3567bae7899fae082338d8ec49d0b","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: flatten ld/st\n\n\tmodified:   sim/sim_core.c","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/dfbce669d3e3567bae7899fae082338d8ec49d0b"},{"sha":"f6377e140e7f48b02d1c454d2d992705ffda0233","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: flatten ldd/std\n\n\tmodified:   sim/sim_core.c","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/f6377e140e7f48b02d1c454d2d992705ffda0233"},{"sha":"15771de9c9bcd3798a3c5aaf2a313586340a3a26","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: flatten lpm0, lpm and elpm\n\n\tmodified:   sim/sim_core.c","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/15771de9c9bcd3798a3c5aaf2a313586340a3a26"},{"sha":"c4467cd54ce79d62f67c2fd5fbb90b58fa0313a3","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: flatten lds and sts\n\n\tmodified:   sim/sim_core.c","distinct":false,"url":"https://api.github.com/repos/bsekisser/simavr/commits/c4467cd54ce79d62f67c2fd5fbb90b58fa0313a3"},{"sha":"c6cf18c8f74e4649d0d0c6dd5a13b8735d8f5b44","author":{"email":"dbe2f39a8b8124367ef42b3c6ea046bd2d5bcf41@embarqmail.com","name":"bsekisser"},"message":"core: flatten rest of skip instructions\n\n\tmodified:   sim/sim_core.c","distinct":true,"url":"https://api.github.com/repos/bsekisser/simavr/commits/c6cf18c8f74e4649d0d0c6dd5a13b8735d8f5b44"}]}