{"push_id":763111107,"size":2,"distinct_size":2,"ref":"refs/heads/dev","head":"57cfb7cfb1fa3b552b7d2a0a4268e736ccf8527e","before":"10d9de39a1122807d7b0438ee8cd248fb38d39b1","commits":[{"sha":"549801cf2e9bf6d689e712371e9b21f62edaecd2","author":{"email":"63ee0ea55429b66b1576546242ad12d65bccc344@analog.com","name":"Istvan Csomortani"},"message":"library: Delete unused IP cores\n\nDelete IP \"controllerperipheralhdladi_pcore\" and \"ip_pid_controller\"","distinct":true,"url":"https://api.github.com/repos/analogdevicesinc/hdl/commits/549801cf2e9bf6d689e712371e9b21f62edaecd2"},{"sha":"57cfb7cfb1fa3b552b7d2a0a4268e736ccf8527e","author":{"email":"63ee0ea55429b66b1576546242ad12d65bccc344@analog.com","name":"Istvan Csomortani"},"message":"hdl/library: Update the IP parameters\n\nThe following IP parameters were renamed:\n\nPCORE_ID --> ID\nPCORE_DEVTYPE --> DEVICE_TYPE\nPCORE_IODELAY_GROUP --> IO_DELAY_GROUP\nCH_DW --> CHANNEL_DATA_WIDTH\nCH_CNT --> NUM_OF_CHANNELS\nPCORE_BUFTYPE --> DEVICE_TYPE\nPCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE\nCHID --> CHANNEL_ID\nPCORE_DEVICE_TYPE --> DEVICE_TYPE\nPCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N\nPCORE_SERDES_DDR_N --> SERDES_DDR_N\nPCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE\nDP_DISABLE --> DATAPATH_DISABLE\nPCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE\nC_BIG_ENDIAN --> BIG_ENDIAN\nC_M_DATA_WIDTH --> MASTER_DATA_WIDTH\nC_S_DATA_WIDTH --> SLAVE_DATA_WIDTH\nNUM_CHANNELS --> NUM_OF_CHANNELS\nCHANNELS --> NUM_OF_CHANNELS\nPCORE_4L_2L_N -->QUAD_OR_DUAL_N\nC_ADDRESS_WIDTH --> ADDRESS_WIDTH\nC_DATA_WIDTH --> DATA_WIDTH\nC_CLKS_ASYNC --> CLKS_ASYNC\nPCORE_QUAD_DUAL_N --> QUAD_DUAL_N\nNUM_CS --> NUM_OF_CS\nPCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID\nPCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID\nPCORE_CLK0_DIV --> CLK0_DIV\nPCORE_CLK1_DIV --> CLK1_DIV\nPCORE_CLKIN_PERIOD --> CLKIN_PERIOD\nPCORE_VCO_DIV --> VCO_DIV\nPCORE_Cr_Cb_N --> CR_CB_N\nPCORE_VCO_MUL --> VCO_MUL\nPCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC\nPCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH\nPCORE_ADDR_WIDTH --> ADDRESS_WIDTH\nDADATA_WIDTH --> DATA_WIDTH\nNUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS\nDEBOUNCER_LEN --> DEBOUNCER_LENGTH\nADDR_WIDTH --> ADDRESS_WIDTH\nC_S_AXIS_REGISTERED --> S_AXIS_REGISTERED\nCr_Cb_N --> CR_CB_N\nADDATA_WIDTH --> ADC_DATA_WIDTH\nBUFTYPE --> DEVICE_TYPE\nNUM_BITS --> NUM_OF_BITS\nWIDTH_A --> A_DATA_WIDTH\nWIDTH_B --> B_DATA_WIDTH\nCH_OCNT --> NUM_OF_CHANNELS_O\nM_CNT --> NUM_OF_CHANNELS_M\nP_CNT --> NUM_OF_CHANNELS_P\nCH_ICNT --> NUM_OF_CHANNELS_I\nCH_MCNT --> NUM_OF_CHANNELS_M\n4L_2L_N --> QUAD_OR_DUAL_N\nSPI_CLK_ASYNC --> ASYNC_SPI_CLK\nMMCM_BUFIO_N --> MMCM_OR_BUFIO_N\nSERDES_DDR_N --> SERDES_OR_DDR_N\nCLK_ASYNC --> ASYNC_CLK\nCLKS_ASYNC --> ASYNC_CLK\nSERDES --> SERDES_OR_DDR_N\nGTH_GTX_N --> GTH_OR_GTX_N\nIF_TYPE --> DDR_OR_SDR_N\nPARALLEL_WIDTH --> DATA_WIDTH\nADD_SUB --> ADD_OR_SUB_N\nA_WIDTH --> A_DATA_WIDTH\nCONST_VALUE --> B_DATA_VALUE\nIO_BASEADDR --> BASE_ADDRESS\nIO_WIDTH --> DATA_WIDTH\nQUAD_DUAL_N --> QUAD_OR_DUAL_N\nAXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT\nADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH\nADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH\nMODE_OF_ENABLE --> CONTROL_TYPE\nCONTROL_TYPE --> LEVEL_OR_PULSE_N\nIQSEL --> Q_OR_I_N\nMMCM --> MMCM_OR_BUFR_N","distinct":true,"url":"https://api.github.com/repos/analogdevicesinc/hdl/commits/57cfb7cfb1fa3b552b7d2a0a4268e736ccf8527e"}]}