{"action":"created","comment":{"url":"https://api.github.com/repos/ARM-software/arm-trusted-firmware/pulls/comments/31307736","id":31307736,"diff_hunk":"@@ -0,0 +1,344 @@\n+/*\n+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * Redistributions of source code must retain the above copyright notice, this\n+ * list of conditions and the following disclaimer.\n+ *\n+ * Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ *\n+ * Neither the name of ARM nor the names of its contributors may be used\n+ * to endorse or promote products derived from this software without specific\n+ * prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <arch.h>\n+#include <asm_macros.S>\n+#include <assert_macros.S>\n+#include <cpu_macros.S>\n+#include <cortex_a57.h>\n+#include <cortex_a53.h>\n+#include <cortex_a_common.h>\n+#include <tegra_def.h>\n+\n+\t/* Global functions */\n+\t.globl\tplatform_is_primary_cpu\n+\t.globl\tplatform_get_core_pos\n+\t.globl\tplatform_get_entrypoint\n+\t.globl\tplat_secondary_cold_boot_setup\n+\t.globl\tplatform_mem_init\n+\t.globl\tplat_crash_console_init\n+\t.globl\tplat_crash_console_putc\n+\t.globl\ttegra_secure_entrypoint\n+\t.globl\tplat_reset_handler\n+\n+\t/* Global variables */\n+\t.globl\tsec_entry_point\n+\t.globl\tns_image_entrypoint\n+\t.globl\ttegra_bl31_phys_base\n+\n+\t/* ---------------------\n+\t * Common CPU init code\n+\t * ---------------------\n+\t */\n+.macro\tcpu_init_common\n+\n+\t/* -------------------------------------------------------\n+\t * Enable L2 and CPU ECTLR RW access from non-secure world\n+\t * -------------------------------------------------------\n+\t*/\n+\tmov\tx0, #ACTLR_ACCESS_CTRL\n+\tmsr\tactlr_el3, x0\n+\tmsr\tactlr_el2, x0\n+\tisb\n+\n+\t/* --------------------------------\n+\t * Enable the cycle count register\n+\t * --------------------------------\n+\t */\n+\tmrs\tx0, pmcr_el0\n+\tubfx\tx0, x0, #11, #5\t\t// read PMCR.N field\n+\tmov\tx1, #1\n+\tlsl\tx0, x1, x0\n+\tsub\tx0, x0, #1\t\t// mask of event counters\n+\torr\tx0, x0, #0x80000000\t// disable overflow intrs\n+\tmsr\tpmintenclr_el1, x0\n+\tmsr\tpmuserenr_el0, x1\t// enable user mode access\n+\n+\t/* ----------------------------------------------------------------\n+\t * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count\n+\t * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ\n+\t * registers from EL0.\n+\t * ----------------------------------------------------------------\n+\t */\n+\tmrs\tx0, cntkctl_el1\n+\torr\tx0, x0, #EL0VCTEN_BIT\n+\tmsr\tcntkctl_el1, x0\n+.endm\n+\n+\t/* -----------------------------------------------------\n+\t * int platform_is_primary_cpu(int mpidr);\n+\t *\n+\t * This function checks if this is the Primary CPU\n+\t * -----------------------------------------------------\n+\t */\n+func platform_is_primary_cpu\n+\tand\tx0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)\n+\tcmp\tx0, #TEGRA_PRIMARY_CPU\n+\tcset\tx0, eq\n+\tret\n+endfunc platform_is_primary_cpu\n+\n+\t/* -----------------------------------------------------\n+\t * int platform_get_core_pos(int mpidr);\n+\t *\n+\t * With this function: CorePos = CoreId\n+\t * -----------------------------------------------------\n+\t */\n+func platform_get_core_pos\n+\tand\tx0, x0, #MPIDR_CPU_MASK\n+\tret\n+endfunc platform_get_core_pos\n+\n+\t/* -----------------------------------------------------\n+\t * void plat_secondary_cold_boot_setup (void);\n+\t *\n+\t * This function performs any platform specific actions\n+\t * needed for a secondary cpu after a cold reset. Right\n+\t * now this is a stub function.\n+\t * -----------------------------------------------------\n+\t */\n+func plat_secondary_cold_boot_setup\n+\tmov\tx0, #0\n+\tret\n+endfunc plat_secondary_cold_boot_setup\n+\n+\t/* -----------------------------------------------------\n+\t * void platform_get_entrypoint (unsigned int mpidr);\n+\t *\n+\t * Main job of this routine is to distinguish between\n+\t * a cold and warm boot. If the sec_entry_point for\n+\t * this CPU is present, then it's a warm boot.\n+\t *\n+\t * -----------------------------------------------------\n+\t */\n+func platform_get_entrypoint\n+\tand\tx0, x0, #MPIDR_CPU_MASK\n+\tadr\tx1, sec_entry_point\n+\tldr\tx0, [x1, x0, lsl #3]\n+\tret\n+endfunc platform_get_entrypoint\n+\n+\t/* --------------------------------------------------------\n+\t * void platform_mem_init (void);\n+\t *\n+\t * Any memory init, relocation to be done before the\n+\t * platform boots. Called very early in the boot process.\n+\t * --------------------------------------------------------\n+\t */\n+func platform_mem_init\n+\tmov\tx0, #0\n+\tret\n+endfunc platform_mem_init\n+\n+\t/* ---------------------------------------------\n+\t * int plat_crash_console_init(void)\n+\t * Function to initialize the crash console\n+\t * without a C Runtime to print crash report.\n+\t * Clobber list : x0, x1, x2\n+\t * ---------------------------------------------\n+\t */\n+func plat_crash_console_init\n+\tmov_imm\tx0, TEGRA_BOOT_UART_BASE\n+\tmov_imm\tx1, TEGRA_BOOT_UART_CLK_IN_HZ\n+\tmov_imm\tx2, TEGRA_CONSOLE_BAUDRATE\n+\tb\tconsole_core_init\n+endfunc plat_crash_console_init\n+\n+\t/* ---------------------------------------------\n+\t * int plat_crash_console_putc(void)\n+\t * Function to print a character on the crash\n+\t * console without a C Runtime.\n+\t * Clobber list : x1, x2\n+\t * ---------------------------------------------\n+\t */\n+func plat_crash_console_putc\n+\tmov_imm\tx1, TEGRA_BOOT_UART_BASE\n+\tb\tconsole_core_putc\n+endfunc plat_crash_console_putc\n+\n+\t/* ---------------------------------------------------\n+\t * Function to handle a platform reset and store\n+\t * input parameters passed by BL2.\n+\t * ---------------------------------------------------\n+\t */\n+func plat_reset_handler\n+\n+\t/* -----------------------------------\n+\t * derive and save the phys_base addr\n+\t * -----------------------------------\n+\t */\n+\tadr\tx17, tegra_bl31_phys_base\n+\tldr\tx18, [x17]\n+\tcbnz\tx18, 1f\n+\tadr\tx18, bl31_entrypoint\n+\tstr\tx18, [x17]\n+\n+1:\tcpu_init_common\n+\n+\tret\n+endfunc plat_reset_handler\n+\n+\t/* ----------------------------------------\n+\t * Secure entrypoint function for CPU boot\n+\t * ----------------------------------------\n+\t */\n+\t.align 6\n+func tegra_secure_entrypoint\n+\n+#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT\n+\n+\t/* -------------------------------------------------------\n+\t * Invalidate BTB along with I$ to remove any stale\n+\t * entries from the branch predictor array.\n+\t * -------------------------------------------------------\n+\t */\n+\tmrs\tx0, CPUACTLR_EL1\n+\torr\tx0, x0, #1\n+\tmsr\tCPUACTLR_EL1, x0\t/* invalidate BTB and I$ together */\n+\tdsb\tsy\n+\tisb\n+\tic\tiallu\t\t\t/* actual invalidate */\n+\tdsb\tsy\n+\tisb\n+\n+\tmrs\tx0, CPUACTLR_EL1\n+\tbic\tx0, x0, #1\n+\tmsr\tCPUACTLR_EL1, X0\t/* restore original CPUACTLR_EL1 */\n+\tdsb\tsy\n+\tisb\n+\n+\t.rept\t7\n+\tnop\t\t\t\t/* wait */\n+\t.endr\n+\n+\t/* -----------------------------------------------\n+\t * Extract OSLK bit and check if it is '1'. This\n+\t * bit remains '0' for A53 on warm-resets. If '1',\n+\t * turn off regional clock gating and request warm\n+\t * reset.\n+\t * -----------------------------------------------\n+\t */\n+\tmrs\tx0, oslsr_el1\n+\tand\tx0, x0, #2\n+\tmrs\tx1, mpidr_el1\n+\tbics\txzr, x0, x1, lsr #7\t/* 0 = slow cluster or warm reset */\n+\tb.eq\trestore_oslock\n+\tmov\tx0, xzr\n+\tmsr\toslar_el1, x0\t\t/* os lock stays 0 across warm reset */\n+\tmov\tx3, #3\n+\tmovz\tx4, #0x8000, lsl #48\n+\tmsr\tCPUACTLR_EL1, x4\t/* turn off RCG */\n+\tisb\n+\tmsr\trmr_el3, x3\t\t/* request warm reset */\n+\tisb\n+\tdsb\tsy\n+\twfi\n+\n+\t/* --------------------------------------------------","path":"plat/nvidia/tegra/common/aarch64/tegra_helpers.S","position":263,"original_position":263,"commit_id":"0cb660e3cb2eacaaa2cc829fbc23e0a0f5591531","original_commit_id":"0cb660e3cb2eacaaa2cc829fbc23e0a0f5591531","user":{"login":"achingupta","id":5773549,"avatar_url":"https://avatars.githubusercontent.com/u/5773549?v=3","gravatar_id":"","url":"https://api.github.com/users/achingupta","html_url":"https://github.com/achingupta","followers_url":"https://api.github.com/users/achingupta/followers","following_url":"https://api.github.com/users/achingupta/following{/other_user}","gists_url":"https://api.github.com/users/achingupta/gists{/gist_id}","starred_url":"https://api.github.com/users/achingupta/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/achingupta/subscriptions","organizations_url":"https://api.github.com/users/achingupta/orgs","repos_url":"https://api.github.com/users/achingupta/repos","events_url":"https://api.github.com/users/achingupta/events{/privacy}","received_events_url":"https://api.github.com/users/achingupta/received_events","type":"User","site_admin":false},"body":"It surely is not a deal breaker. The patch can be merged. I just wanted to flag it.","created_at":"2015-05-29T08:39:30Z","updated_at":"2015-05-29T08:39:30Z","html_url":"https://github.com/ARM-software/arm-trusted-firmware/pull/304#discussion_r31307736","pull_request_url":"https://api.github.com/repos/ARM-software/arm-trusted-firmware/pulls/304","_links":{"self":{"href":"https://api.github.com/repos/ARM-software/arm-trusted-firmware/pulls/comments/31307736"},"html":{"href":"https://github.com/ARM-software/arm-trusted-firmware/pull/304#discussion_r31307736"},"pull_request":{"href":"https://api.github.com/repos/ARM-software/arm-trusted-firmware/pulls/304"}}},"pull_request":{"url":"https://api.github.com/repos/ARM-software/arm-trusted-firmware/pulls/304","id":35720270,"html_url":"https://github.com/ARM-software/arm-trusted-firmware/pull/304","diff_url":"https://github.com/ARM-software/arm-trusted-firmware/pull/304.diff","patch_url":"https://github.com/ARM-software/arm-trusted-firmware/pull/304.patch","issue_url":"https://api.github.com/repos/ARM-software/arm-trusted-firmware/issues/304","number":304,"state":"closed","locked":false,"title":"Tegra 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