{"push_id":566199975,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"02eb403d89837c0aa0bba502c369fbd087feaf41","before":"f1145d211c2858b1bfa4c6feb054f10e78a7f01b","commits":[{"sha":"f2e3dcd0390a79a043d8956b778e5ab5009f351b","author":{"email":"6b31706989f3cf9466bfddbf48eab0c43e646ba8@gmail.com","name":"Rafael Espindola"},"message":"Add a FIXME.\n\nThanks to Eric for the suggestion.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228300 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/f2e3dcd0390a79a043d8956b778e5ab5009f351b"},{"sha":"02eb403d89837c0aa0bba502c369fbd087feaf41","author":{"email":"226409dbd0f8f7302b911c342b723f8b80eeb87d@linux.vnet.ibm.com","name":"Bill Schmidt"},"message":"[PowerPC] Implement the vclz instructions for PWR8\n\nPatch by Kit Barton.\n\nAdd the vector count leading zeros instruction for byte, halfword,\nword, and doubleword sizes.  This is a fairly straightforward addition\nafter the changes made for vpopcnt:\n\n 1. Add the correct definitions for the various instructions in\n    PPCInstrAltivec.td\n 2. Make the CTLZ operation legal on vector types when using P8Altivec\n    in PPCISelLowering.cpp \n\nTest Plan\n\nCreated new test case in test/CodeGen/PowerPC/vec_clz.ll to check the\ninstructions are being generated when the CTLZ operation is used in\nLLVM.\n\nCheck the encoding and decoding in test/MC/PowerPC/ppc_encoding_vmx.s\nand test/Disassembler/PowerPC/ppc_encoding_vmx.txt respectively.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228301 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/02eb403d89837c0aa0bba502c369fbd087feaf41"}]}