{"push_id":727706967,"size":53,"distinct_size":53,"ref":"refs/heads/master","head":"e03f4bd255be67334fcc26915e666a25abcb648a","before":"368de4c9d658348b2a88e588a5a8d2c073d4e7ff","commits":[{"sha":"ccadf0b1b4bcf244f85e0844c67ed50a37221422","author":{"email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk","name":"Simon Pilgrim"},"message":"[X86][SSE] Added i686/SSE2 vector shift tests.\n\nWe were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242273 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/ccadf0b1b4bcf244f85e0844c67ed50a37221422"},{"sha":"d2e1e42c1a10d05067832eae990ddc1fa55c9c34","author":{"email":"9dd349949fa0498552275ea167f1cd173630a307@arm.com","name":"Petr Pavlu"},"message":"[TableGen] Improve decoding options for non-orthogonal instructions\n\nWhen FixedLenDecoder matches an input bitpattern of form [01]+ with an\ninstruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are\nmixed/variable bits) it passes the input bitpattern to a specific instruction\ndecoder method which then makes a final decision whether the bitpattern is a\nvalid instruction or not. This means the decoder must handle all possible\nvalues of the variable bits which sometimes leads to opcode rewrites in the\ndecoder method when the instructions are not fully orthogonal.\n\nThe patch provides a way for the decoder method to say that when it returns\nFail it does not necessarily mean the bitpattern is invalid, but rather that\nthe bitpattern is definitely not an instruction that is recognized by the\ndecoder method. The decoder can then try to match the input bitpattern with\nother possible instruction bitpatterns.\n\nFor example, this allows to solve a situation on AArch64 where the `MSR\n(immediate)` instruction has form:\n1101 0101 0000 0??? 0100 ???? ???1 1111\nbut not all values of the ? bits are allowed. The rejected values should be\nhandled by the `extended MSR (register)` instruction:\n1101 0101 000? ???? ???? ???? ???? ????\n\nThe decoder will first try to decode an input bitpattern that matches both\nbitpatterns as `MSR (immediate)` but currently this puts the decoder method of\n`MSR (immediate)` into a situation when it must be able to decode all possible\nvalues of the ? bits, i.e. it would need to rewrite the instruction to `MSR\n(register)` when it is not `MSR (immediate)`.\n\nThe patch allows to specify that the decoder method cannot determine if the\ninstruction is valid for all variable values. The decoder method can simply\nreturn Fail when it knows it is definitely not `MSR (immediate)`. The decoder\nwill then backtrack the decoding and find that it can match the input\nbitpattern with the more generic `MSR (register)` bitpattern too.\n\nDifferential Revision: http://reviews.llvm.org/D7174\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242274 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/d2e1e42c1a10d05067832eae990ddc1fa55c9c34"},{"sha":"f31b1ec106799f9461d8ed21a2e67da3d9ac798b","author":{"email":"420c9fb3407b8e11ac322a0e7703f7b1f526df04@gmail.com","name":"Chandler Carruth"},"message":"[PM/AA] Cleanup some loops to be range-based. NFC.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242275 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/f31b1ec106799f9461d8ed21a2e67da3d9ac798b"},{"sha":"ec223f1217da16079ae6691c86b2e1e90ef130a8","author":{"email":"9dd349949fa0498552275ea167f1cd173630a307@arm.com","name":"Petr Pavlu"},"message":"[AArch64] Fix problems in decoding generic MSR instructions\n\nBitpatterns rejected by the decoder method of `MSR (immediate)` should be\ndecoded as the `extended MSR (register)` instruction.\n\nDifferential Revision: http://reviews.llvm.org/D7174\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242276 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/ec223f1217da16079ae6691c86b2e1e90ef130a8"},{"sha":"b2a353c753f9e9f527e172aa31d196d133ea8c70","author":{"email":"76a8e82c3bdc78a1f9490a34857cdee8b1b06a45@anl.gov","name":"Hal Finkel"},"message":"[MachineCombiner] Work with itineraries\n\nMachineCombiner predicated its use of scheduling-based metrics on\nhasInstrSchedModel(), but useful conclusions can be drawn from pipeline\nitineraries as well. Almost all of the logic (except for resource tracking in\npreservesResourceLen) can be used if we have an itinerary, so enable it in that\ncase as well.\n\nThis will be used by the PowerPC backend in an upcoming commit.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242277 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/b2a353c753f9e9f527e172aa31d196d133ea8c70"},{"sha":"e4edd6cd8e21e3cc196a7310c3c6bf2826351c3f","author":{"email":"76a8e82c3bdc78a1f9490a34857cdee8b1b06a45@anl.gov","name":"Hal Finkel"},"message":"[PowerPC] Extend physical register live range in PPCVSXFMAMutate\n\nIf the source of the copy that defines the addend is a physical register, then\nits existing live range may not extend to the FMA being mutated. Make sure we\nextend the live range of the register to meet the FMA because it will become\nits operand in this case.\n\nI don't have an independent test case, but it will be exposed by change to be\ncommitted shortly enabling the use of the machine combiner to do fadd/fmul\nreassociation, and will be covered by one of the associated regression tests.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242278 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/e4edd6cd8e21e3cc196a7310c3c6bf2826351c3f"},{"sha":"8913d18fb1f694c7ea363a8f2ea002673d025202","author":{"email":"76a8e82c3bdc78a1f9490a34857cdee8b1b06a45@anl.gov","name":"Hal Finkel"},"message":"[PowerPC] Use the MachineCombiner to reassociate fadd/fmul\n\nThis is a direct port of the code from the X86 backend (r239486/r240361), which\nuses the MachineCombiner to reassociate (floating-point) adds/muls to increase\nILP, to the PowerPC backend. The rationale is the same.\n\nThere is a lot of copy-and-paste here between the X86 code and the PowerPC\ncode, and we should extract at least some of this into CodeGen somewhere.\nHowever, I don't want to do that until this code is enhanced to handle FMAs as\nwell. After that, we'll be in a better position to extract the common parts.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242279 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/8913d18fb1f694c7ea363a8f2ea002673d025202"},{"sha":"a01809966911a7614e877c0a7e08a5ab507e2f60","author":{"email":"42c60520d22f29ab4fbd7ab379c1a50cda8b3dfa@hotmail.com","name":"Alexey Bataev"},"message":"[SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)\n\nCurrent implementation handles unordered comparison poorly in soft-float mode. \nConsider (a ULE b) which is a <= b. It is lowered to (ledf2(a, b) <= 0 || unorddf2(a, b) != 0) (in general). We can do better job by lowering it to (__gtdf2(a, b) <= 0). \nSuch replacement is true for other CMP's (ult, ugt, uge). In general, we just call same function as for ordered case but negate comparison against zero.\nDifferential Revision: http://reviews.llvm.org/D10804\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242280 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/a01809966911a7614e877c0a7e08a5ab507e2f60"},{"sha":"7d51923226a143084b6555a2db275f9c99025acc","author":{"email":"420c9fb3407b8e11ac322a0e7703f7b1f526df04@gmail.com","name":"Chandler Carruth"},"message":"[PM/AA] Fix *numerous* serious bugs in GlobalsModRef found by\ninspection.\n\nWhile we want to handle calls specially in this code because they should\nhave been modeled by the call graph analysis that precedes it, we should\n*not* be re-implementing the predicates for whether an instruction reads\nor writes memory. Those are well defined already. Notably, at least the\nfollowing issues seem to be clearly missed before:\n- Ordered atomic loads can \"write\" to memory by causing writes from other\n  threads to become visible. Similarly for ordered atomic stores.\n- AtomicRMW instructions quite obviously both read and write to memory.\n- AtomicCmpXchg instructions also read and write to memory.\n- Fences read and write to memory.\n- Invokes of intrinsics or memory allocation functions.\n\nI don't have any test cases, and I suspect this has never really come up\nin the real world. But there is no reason why it wouldn't, and it makes\nthe code simpler to do this the right way.\n\nWhile here, I've tried to make the loops significantly simpler as well\nand added helpful comments as to what is going on.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242281 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/7d51923226a143084b6555a2db275f9c99025acc"},{"sha":"4aa2f4514ccb6f5ee87328559d91b93a7cb78735","author":{"email":"673d30659c31b8ee13263df947c97b031b67e4ff@arm.com","name":"Alexandros Lamprineas"},"message":"-Added API for retrieving the default FPU of a CPU from TargetParser.\n-Implemented as a table lookup.\n\nChange-Id: Iaad0eaf4b29b06827e6700269496dc1ba20e9018\nPhabricator: http://reviews.llvm.org/D11100\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242284 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/4aa2f4514ccb6f5ee87328559d91b93a7cb78735"},{"sha":"17351cfb43e320129b854fff774cd81a6154fcb9","author":{"email":"ea91796269c7842d401af30276638d4aaa593379@googlemail.com","name":"Benjamin Kramer"},"message":"[PPC] Disassemble little endian ppc instructions in the right byte order\n\nPR24122. The test is simply a byte swapped version of ppc64-encoding.txt.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242288 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/17351cfb43e320129b854fff774cd81a6154fcb9"},{"sha":"9226c071b0065918ce487872895f7dae35ce2382","author":{"email":"3238936ca5ea88ccfaa614757c77dee08fa495f5@gmail.com","name":"Andrew Wilkins"},"message":"Expose setPersonalityFn to Go\n\nSummary:\nAdd Value.SetPersonality to the Go bindings. The Go\nbindings' Builder.CreateLandingPad has been updated,\nremoving the obsolete personality argument.\n\nBackground\n\nThe personality attribute was removed from LandingPadInst\nin r239940, and llvm::Function::setPersonalityFn introduced.\n\nThere was no corresponding change to either the C API or\nGo bindings. The Go bindings were broken until r239940, but\nthat change was just to ignore the personality argument.\nThis broke llgo.\n\nReviewers: majnemer, pcc\n\nSubscribers: deadalnix, llvm-commits, axw\n\nDifferential Revision: http://reviews.llvm.org/D11116\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242289 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/9226c071b0065918ce487872895f7dae35ce2382"},{"sha":"7c72a2254c47f576a40dd456521a969f0ec76f92","author":{"email":"2ca028346d1d172bdf6d5bd55544812ec8ee16e2@gmail.com","name":"Bruno Cardoso Lopes"},"message":"Refactor optimizeUncoalescable logic\n\n- Create a new CopyRewriter for Uncoalescable copy-like instructions\n- Change the ValueTracker to return a ValueTrackerResult\n\nThis makes optimizeUncoalescable looks more like optimizeCoalescable and\nuse the CopyRewritter infrastructure.\n\nThis is also the preparation for looking up into PHI nodes in the\nValueTracker.\n\nDifferential Revision: http://reviews.llvm.org/D11195\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242294 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/7c72a2254c47f576a40dd456521a969f0ec76f92"},{"sha":"b11d8102cfb0bbe2480ea239393cfa261e55a1d6","author":{"email":"2ca028346d1d172bdf6d5bd55544812ec8ee16e2@gmail.com","name":"Bruno Cardoso Lopes"},"message":"Look through PHIs to find additional register sources\n\n- Teaches the ValueTracker in the PeepholeOptimizer to look through PHI\ninstructions.\n- Add findNextSourceAndRewritePHI method to lookup into multiple sources\nreturnted by the ValueTracker and rewrite PHIs with new sources.\n\nWith these changes we can find more register sources and rewrite more\ncopies to allow coaslescing of bitcast instructions. Hence, we eliminate\nunnecessary VR64 <-> GR64 copies in x86, but it could be extended to\nother archs by marking \"isBitcast\" on target specific instructions. The\nx86 example follows:\n\nA:\n  psllq %mm1, %mm0\n  movd  %mm0, %r9\n  jmp C\n\nB:\n  por %mm1, %mm0\n  movd  %mm0, %r9\n  jmp C\n\nC:\n  movd  %r9, %mm0\n  pshufw  $238, %mm0, %mm0\n\nBecomes:\n\nA:\n  psllq %mm1, %mm0\n  jmp C\n\nB:\n  por %mm1, %mm0\n  jmp C\n\nC:\n  pshufw  $238, %mm0, %mm0\n\nDifferential Revision: http://reviews.llvm.org/D11197\n\nrdar://problem/20404526\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242295 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/b11d8102cfb0bbe2480ea239393cfa261e55a1d6"},{"sha":"aa2200c5fa13b6e8712ee694cabbdfe9800d9067","author":{"email":"226409dbd0f8f7302b911c342b723f8b80eeb87d@linux.vnet.ibm.com","name":"Bill Schmidt"},"message":"[PPC64LE] Fix vec_sld semantics for little endian\n\nThe vec_sld interface provides access to the vsldoi instruction.\nUnlike most of the vec_* interfaces, we do not attempt to change the\ngenerated code for vec_sld based on the endian mode.  It is too\ndifficult to correctly infer the desired semantics because of\ndifferent element types, and the corrected instruction sequence is\nexpensive, involving loading a permute control vector and performing a\ngeneralized permute.\n\nFor GCC, this was implemented as \"Don't touch the vec_sld\"\nimplementation.  When it came time for the LLVM implementation, I did\nthe same thing.  However, this was hasty and incorrect.  In LLVM's\nversion of altivec.h, vec_sld was previously defined in terms of the\nvec_perm interface.  Because vec_perm semantics are adjusted for\nlittle endian, this means that leaving vec_sld untouched causes it to\ngenerate something different for LE than for BE.  Not good.\n\nThis back-end patch accompanies the changes to altivec.h that change\nvec_sld's behavior for little endian.  Those changes mean that we see\nslightly different code in the back end when trying to recognize a\nVSLDOI instruction in isVSLDOIShuffleMask.  In particular, a\nShuffleKind of 1 (where the two inputs are identical) must now be\ntreated the same way as a ShuffleKind of 2 (little endian with\ndifferent inputs) when little endian mode is in force.  This is\nbecause ShuffleKind of 1 is defined using big-endian numbering.\n\nThis has a ripple effect on LowerBUILD_VECTOR, where we create our own\ninternal VSLDOI instructions.  Because these are a ShuffleKind of 1,\nthey will now have their shift amounts subtracted from 16 when\nrecognizing the shuffle mask.  To avoid problems we have to subtract\nthem from 16 again before creating the VSLDOI instructions.\n\nThere are a couple of other uses of BuildVSLDOI, but these do not need\nto be modified because the shift amount is 8, which is unchanged when\nsubtracted from 16.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242296 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/aa2200c5fa13b6e8712ee694cabbdfe9800d9067"},{"sha":"745b733071817b577f416be0e55e422f69dd9011","author":{"email":"607a4aeae37c8a26eb86f95c436fb926ad94d55c@apple.com","name":"Pete Cooper"},"message":"Add missing load/store flags to thumb2 instructions.\n\nThese were the cause of a verifier error when building 7zip with\n-verify-machineinstrs.  Running 'make check' with the verifier\ntriggered the same error on the test here so i've updated the test\nto run the verifier on one of its runs instead of adding a new one.\n\nWhile looking at this code, there was a stale comment that these\ninstructions were only used for disassembly.  This probably used to\nbe the case, but they are now used in the 'ARM load / store optimization pass' too.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242300 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/745b733071817b577f416be0e55e422f69dd9011"},{"sha":"bd584159e1aec355b3a678a280a0ae4ee755d188","author":{"email":"da230f0243ee2df490cee3ca2c04c1ee8891c8ea@apple.com","name":"Adrian Prantl"},"message":"Debug Info: Add basic support for external types references.\nThis is a necessary prerequisite for bootstrapping the emission\nof debug info inside modules.\n\n- Adds a FlagExternalTypeRef to DICompositeType.\n  External types must have a unique identifier.\n- External type references are emitted using a forward declaration\n  with a DW_AT_signature([DW_FORM_ref_sig8]) based on the UID.\n\nhttp://reviews.llvm.org/D9612\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242302 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/bd584159e1aec355b3a678a280a0ae4ee755d188"},{"sha":"b7faac8a2e320b0f357d82833a8bb9f67b869565","author":{"email":"6b31706989f3cf9466bfddbf48eab0c43e646ba8@gmail.com","name":"Rafael Espindola"},"message":"Delete declared but not implemented functions.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242304 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/b7faac8a2e320b0f357d82833a8bb9f67b869565"},{"sha":"15afc3140e596b69993c37db0cd0f08a55a46fe9","author":{"email":"4205e0b10aeac2e402f2f26cf2728ee8acfd11e6@google.com","name":"Cong Hou"},"message":"Test commit.\n\nThis is a test commit (one blank line deleted).\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242308 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/15afc3140e596b69993c37db0cd0f08a55a46fe9"},{"sha":"ae1ebf6cf78c822ceeaea2a1a2acd3b33ebd19a8","author":{"email":"2ca028346d1d172bdf6d5bd55544812ec8ee16e2@gmail.com","name":"Bruno Cardoso Lopes"},"message":"Revert \"Look through PHIs to find additional register sources\"\n\nLikely broke compilation on ARM:\n\nhttp://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/13054\n\nThis reverts commit 131ce4a838c081516cbfed039fc986b33e3979d6.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242310 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/ae1ebf6cf78c822ceeaea2a1a2acd3b33ebd19a8"}]}