{"push_id":736423509,"size":12,"distinct_size":7,"ref":"refs/heads/tcg-next","head":"53bf1898b41ecc427dda855912202a3da0958f63","before":"bf7efd6e3be8311d7f243dcdea7df0e0cf6346ec","commits":[{"sha":"69970fcef937bddd7f745efe39501c7716fdfe56","author":{"email":"7469de9b95ba379e2656fa9677689657c47a7690@redhat.com","name":"Alex Williamson"},"message":"vfio/pci: Fix RTL8168 NIC quirks\n\nThe RTL8168 quirk correctly describes using bit 31 as a signal to\nmark a latch/completion, but the code mistakenly uses bit 28.  This\ncauses the Realtek driver to spin on this register for quite a while,\n20k cycles on Windows 7 v7.092 driver.  Then it gets frustrated and\ntries to set the bit itself and spins for another 20k cycles.  For\nsome this still results in a working driver, for others not.  About\nthe only thing the code really does in its current form is protect\nthe guest from sneaking in writes to the real hardware MSI-X table.\nThe fix is obviously to use bit 31 as we document that we should.\n\nThe other problem doesn't seem to affect current drivers as nobody\nseems to use these window registers for writes to the MSI-X table, but\nwe need to use the stored data when a write is triggered, not the\nvalue of the current write, which only provides the offset.\n\nNote that only the Windows drivers from Realtek seem to use these\nregisters, the Microsoft drivers provided with Windows 8.1 do not\naccess them, nor do Linux in-kernel drivers.\n\nLink: https://bugs.launchpad.net/qemu/+bug/1384892\nSigned-off-by: Alex Williamson <alex.williamson@redhat.com>\nCc: qemu-stable@nongnu.org # v2.1+","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/69970fcef937bddd7f745efe39501c7716fdfe56"},{"sha":"759b484c5d7f92bd01f98797c07e8543ee187888","author":{"email":"7469de9b95ba379e2656fa9677689657c47a7690@redhat.com","name":"Alex Williamson"},"message":"vfio/pci: Fix bootindex\n\nbootindex was incorrectly changed to a device Property during the\nplatform code split, resulting in it no longer working.  Remove it.\n\nSigned-off-by: Alex Williamson <alex.williamson@redhat.com>\nCc: qemu-stable@nongnu.org # v2.3+","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/759b484c5d7f92bd01f98797c07e8543ee187888"},{"sha":"ee8ba9e4d8458b8bba5455a7ae704620c4f2ef4b","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg/i386: Extend addresses for 32-bit guests\n\nRemoving the ??? comment explaining why it (mostly) worked.\n\nReviewed-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\nMessage-Id: <1437081950-7206-2-git-send-email-rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/ee8ba9e4d8458b8bba5455a7ae704620c4f2ef4b"},{"sha":"6c0f0c0f124718650a8d682ba275044fc02f6fe2","author":{"email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com","name":"Paolo Bonzini"},"message":"tcg/aarch64: add ext argument to tcg_out_insn_3310\n\nThe new argument lets you pick uxtw or uxtx mode for the offset\nregister.  For now, all callers pass TCG_TYPE_I64 so that uxtx\nis generated.  The bits for uxtx are removed from I3312_TO_I3310.\n\nReported-by: Leon Alrae <leon.alrae@imgtec.com>\nReviewed-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>\nMessage-Id: <1436974021-28978-2-git-send-email-pbonzini@redhat.com>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/6c0f0c0f124718650a8d682ba275044fc02f6fe2"},{"sha":"ffc6372851d8631a9f9fa56ec613b3244dc635b9","author":{"email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com","name":"Paolo Bonzini"},"message":"tcg/aarch64: use 32-bit offset for 32-bit user-mode emulation\n\nThanks to the previous patch, it is now easy for tcg_out_qemu_ld and\ntcg_out_qemu_st to use a 32-bit zero extended offset.  However, the\nguest base register x28 must be the base and addr_reg must be the\nindex.\n\nReported-by: Leon Alrae <leon.alrae@imgtec.com>\nReviewed-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>\nMessage-Id: <1436974021-28978-3-git-send-email-pbonzini@redhat.com>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/ffc6372851d8631a9f9fa56ec613b3244dc635b9"},{"sha":"80adb8fcad4778376a11d394a9e01516819e2327","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg/aarch64: use 32-bit offset for 32-bit softmmu emulation\n\nSimilar to the same fix for user-mode, except this instance\noccurs on the softmmu path.  Again, the tlb addend must be\nthe base register, while the guest address is the index.\n\nReviewed-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/80adb8fcad4778376a11d394a9e01516819e2327"},{"sha":"961521261a3d600b0695b2e6d2b0f490076f7e90","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg/optimize: fix tcg_opt_gen_movi\n\nDue to a copy&paste, the new op value is tested against mov_i32 instead\nof movi_i32. The test is therefore always false. Fix that.\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nMessage-Id: <1436544211-2769-1-git-send-email-aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/961521261a3d600b0695b2e6d2b0f490076f7e90"},{"sha":"f75b709853d2b2b0f2a8e149229aa1c7c1ee1c60","author":{"email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org","name":"Peter Maydell"},"message":"Merge remote-tracking branch 'remotes/awilliam/tags/vfio-fixes-20150723.0' into staging\n\nVFIO fixes for v2.4.0-rc3\n- Fix Realtek NIC quirk (Alex Williamson)\n- Restore bootindex functionality (Alex Williamson)\n\n# gpg: Signature made Thu Jul 23 19:51:23 2015 BST using RSA key ID 3BB08B22\n# gpg: Good signature from \"Alex Williamson <alex.williamson@redhat.com>\"\n# gpg:                 aka \"Alex Williamson <alex@shazbot.org>\"\n# gpg:                 aka \"Alex Williamson <alwillia@redhat.com>\"\n# gpg:                 aka \"Alex Williamson <alex.l.williamson@gmail.com>\"\n\n* remotes/awilliam/tags/vfio-fixes-20150723.0:\n  vfio/pci: Fix bootindex\n  vfio/pci: Fix RTL8168 NIC quirks\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/f75b709853d2b2b0f2a8e149229aa1c7c1ee1c60"},{"sha":"30fdfae49d53cfc678859095e49ac60b79562d6f","author":{"email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org","name":"Peter Maydell"},"message":"Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150723' into staging\n\nLast minute fixes for 2.4.\n\n# gpg: Signature made Fri Jul 24 04:42:31 2015 BST using RSA key ID 4DD0279B\n# gpg: Good signature from \"Richard Henderson <rth7680@gmail.com>\"\n# gpg:                 aka \"Richard Henderson <rth@redhat.com>\"\n# gpg:                 aka \"Richard Henderson <rth@twiddle.net>\"\n\n* remotes/rth/tags/pull-tcg-20150723:\n  tcg/optimize: fix tcg_opt_gen_movi\n  tcg/aarch64: use 32-bit offset for 32-bit softmmu emulation\n  tcg/aarch64: use 32-bit offset for 32-bit user-mode emulation\n  tcg/aarch64: add ext argument to tcg_out_insn_3310\n  tcg/i386: Extend addresses for 32-bit guests\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/30fdfae49d53cfc678859095e49ac60b79562d6f"},{"sha":"9006ce2a13ae03d1fa99b2a28a80310c28fcbaad","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg/i386: use softmmu fast path for unaligned accesses\n\nSoftmmu unaligned load/stores currently goes through through the slow\npath for two reasons:\n  - to support unaligned access on host with strict alignement\n  - to correctly handle accesses crossing pages\n\nx86 is only concerned by the second reason. Unaligned accesses are\navoided by compilers, but are not uncommon. We therefore would like\nto see them going through the fast path, if they don't cross pages.\n\nFor that we can use the fact that two adjacent TLB entries can't contain\nthe same page. Therefore accessing the TLB entry corresponding to the\nfirst byte, but comparing its content to page address of the last byte\nensures that we don't cross pages. We can do this check without adding\nmore instructions in the TLB code (but increasing its length by one\nbyte) by using the LEA instruction to combine the existing move with the\nsize addition.\n\nOn an x86-64 host, this gives a 3% boot time improvement for a powerpc\nguest and 4% for an x86-64 guest.\n\n[rth: Tidied calculation of the offset mask]\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nMessage-Id: <1436467197-2183-1-git-send-email-aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/9006ce2a13ae03d1fa99b2a28a80310c28fcbaad"},{"sha":"481eef8c87cf699d5a5d27038330b1bc3062968d","author":{"email":"a7089bb6e7e92505d88aaff006cbdd60cc9120b6@kernel.crashing.org","name":"Benjamin Herrenschmidt"},"message":"tcg/ppc: Improve unaligned load/store handling on 64-bit backend\n\nCurrently, we get to the slow path for any unaligned access in the\nbackend, because we effectively preserve the bottom address bits\nbelow the alignment requirement when comparing with the TLB entry,\nso any non-0 bit there will cause the compare to fail.\n\nFor the same number of instructions, we can instead add the access\nsize - 1 to the address and stick to clearing all the bottom bits.\n\nThat means that normal unaligned accesses will not fallback (the HW\nwill handle them fine). Only when crossing a page boundary well we\nend up having a mismatch because we'll end up pointing to the next\npage which cannot possibly be in that same TLB entry.\n\nReviewed-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>\nMessage-Id: <1437455978.5809.2.camel@kernel.crashing.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/481eef8c87cf699d5a5d27038330b1bc3062968d"},{"sha":"53bf1898b41ecc427dda855912202a3da0958f63","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg/s390: Use softmmu fast path for unaligned accesses\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/53bf1898b41ecc427dda855912202a3da0958f63"}]}