{"push_id":693459309,"size":255,"distinct_size":87,"ref":"refs/heads/net","head":"f471bc680d3a8b6251242a1fd84a0c456cc99eed","before":"73e47f4bc1a1aac59dba3f3a5feb27fbcb1cde50","commits":[{"sha":"07e415f2398d9cfb21cdd5ef902445032ba54556","author":{"email":"b75d81c03bd01637475de8fdfe57bd6e8b41a08d@redhat.com","name":"Kevin Wolf"},"message":"fdc: Rename fdctrl_reset_fifo() to fdctrl_to_command_phase()\n\nWhat all callers of fdctrl_reset_fifo() really want to do is to start\nthe command phase, where writes to the data port initiate a new command.\n\nThe function doesn't only clear the FIFO, but also sets up the state so\nthat a new command can be received. Rename it to reflect this.\n\nSigned-off-by: Kevin Wolf <kwolf@redhat.com>\nReviewed-by: John Snow <jsnow@redhat.com>\nMessage-id: 1432214378-31891-2-git-send-email-kwolf@redhat.com\nSigned-off-by: John Snow <jsnow@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/07e415f2398d9cfb21cdd5ef902445032ba54556"},{"sha":"83a260135f13db8b5d7df72090864a5ebcef2845","author":{"email":"b75d81c03bd01637475de8fdfe57bd6e8b41a08d@redhat.com","name":"Kevin Wolf"},"message":"fdc: Rename fdctrl_set_fifo() to fdctrl_to_result_phase()\n\nWhat callers really do with this function is to switch from execution\nphase (including data transfers) to result phase where the guest can\nread out one or more status bytes from the FIFO (the number depends on\nthe command).\n\nRename the function accordingly.\n\nSigned-off-by: Kevin Wolf <kwolf@redhat.com>\nReviewed-by: John Snow <jsnow@redhat.com>\nMessage-id: 1432214378-31891-3-git-send-email-kwolf@redhat.com\nSigned-off-by: John Snow <jsnow@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/83a260135f13db8b5d7df72090864a5ebcef2845"},{"sha":"85d291a08c91c07927bbbd29f72a27d3ad7478f3","author":{"email":"b75d81c03bd01637475de8fdfe57bd6e8b41a08d@redhat.com","name":"Kevin Wolf"},"message":"fdc: Introduce fdctrl->phase\n\nThe floppy controller spec describes three different controller phases,\nwhich are currently not explicitly modelled in our emulation. Instead,\neach phase is represented by a combination of flags in registers.\n\nThis patch makes explicit in which phase the controller currently is.\n\nSigned-off-by: Kevin Wolf <kwolf@redhat.com>\nAcked-by: John Snow <jsnow@redhat.com>\nMessage-id: 1432214378-31891-4-git-send-email-kwolf@redhat.com\nSigned-off-by: John Snow <jsnow@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/85d291a08c91c07927bbbd29f72a27d3ad7478f3"},{"sha":"5b0a25e8d2f15f89255c745c71d297b5b24d138c","author":{"email":"b75d81c03bd01637475de8fdfe57bd6e8b41a08d@redhat.com","name":"Kevin Wolf"},"message":"fdc: Use phase in fdctrl_write_data()\n\nInstead of relying on a flag in the MSR to distinguish controller phases,\nuse the explicit phase that we store now. Assertions of the right MSR\nflags are added.\n\nSigned-off-by: Kevin Wolf <kwolf@redhat.com>\nReviewed-by: John Snow <jsnow@redhat.com>\nMessage-id: 1432214378-31891-5-git-send-email-kwolf@redhat.com\nSigned-off-by: John Snow <jsnow@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/5b0a25e8d2f15f89255c745c71d297b5b24d138c"},{"sha":"d275b33d76c8ed9d5a3dca22ea0fdec8d5a5c8e6","author":{"email":"b75d81c03bd01637475de8fdfe57bd6e8b41a08d@redhat.com","name":"Kevin Wolf"},"message":"fdc: Code cleanup in fdctrl_write_data()\n\nFactor out a few common lines of code, reformat, improve comments.\n\nSigned-off-by: Kevin Wolf <kwolf@redhat.com>\nReviewed-by: John Snow <jsnow@redhat.com>\nMessage-id: 1432214378-31891-6-git-send-email-kwolf@redhat.com\nSigned-off-by: John Snow <jsnow@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/d275b33d76c8ed9d5a3dca22ea0fdec8d5a5c8e6"},{"sha":"f6c2d1d8425fd0ca450d515b06821e2224d4b43c","author":{"email":"b75d81c03bd01637475de8fdfe57bd6e8b41a08d@redhat.com","name":"Kevin Wolf"},"message":"fdc: Disentangle phases in fdctrl_read_data()\n\nThis commit makes similar improvements as have already been made to the\nwrite function: Instead of relying on a flag in the MSR to distinguish\ncontroller phases, use the explicit phase that we store now. Assertions\nof the right MSR flags are added.\n\nSigned-off-by: Kevin Wolf <kwolf@redhat.com>\nReviewed-by: John Snow <jsnow@redhat.com>\nMessage-id: 1432214378-31891-7-git-send-email-kwolf@redhat.com\nSigned-off-by: John Snow <jsnow@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/f6c2d1d8425fd0ca450d515b06821e2224d4b43c"},{"sha":"6cc8a11c84ddc18c64fc88d54c8e9dca24ada489","author":{"email":"b75d81c03bd01637475de8fdfe57bd6e8b41a08d@redhat.com","name":"Kevin Wolf"},"message":"fdc: Fix MSR.RQM flag\n\nThe RQM bit in MSR should be set whenever the guest is supposed to\naccess the FIFO, and it should be cleared in all other cases. This is\nimportant so the guest can't continue writing/reading the FIFO beyond\nthe length that it's suppossed to access (see CVE-2015-3456).\n\nCommit e9077462 fixed the CVE by adding code that avoids the buffer\noverflow; however it doesn't correct the wrong behaviour of the floppy\ncontroller which should already have cleared RQM.\n\nCurrently, RQM stays set all the time and during all phases while a\ncommand is being processed. This is error-prone because the command has\nto explicitly clear the flag if it doesn't need data (and indeed, the\ntwo buggy commands that are the culprits for the CVE just forgot to do\nthat).\n\nThis patch clears RQM immediately as soon as all bytes that are expected\nhave been received. If the the FIFO is used in the next phase, the flag\nhas to be set explicitly there.\n\nIt also clear RQM after receiving all bytes even if the phase transition\nimmediately sets it again. While it's technically not necessary at the\nmoment because the state between clearing and setting RQM is not\nobservable by the guest, this is more explicit and matches how real\nhardware works. It will actually become necessary in qemu once\nasynchronous code paths are introduced.\n\nThis alone should have been enough to fix the CVE, but now we have two\nlines of defense - even better.\n\nSigned-off-by: Kevin Wolf <kwolf@redhat.com>\nReviewed-by: John Snow <jsnow@redhat.com>\nMessage-id: 1432214378-31891-8-git-send-email-kwolf@redhat.com\nSigned-off-by: John Snow <jsnow@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/6cc8a11c84ddc18c64fc88d54c8e9dca24ada489"},{"sha":"4964e18e490f3ecad35c9e4cc9b613316a98755e","author":{"email":"b75d81c03bd01637475de8fdfe57bd6e8b41a08d@redhat.com","name":"Kevin Wolf"},"message":"fdc-test: Test state for existing cases more thoroughly\n\nThis just adds a few additional checks of the MSR and interrupt pin to\nthe already existing test cases.\n\nSigned-off-by: Kevin Wolf <kwolf@redhat.com>\nReviewed-by: John Snow <jsnow@redhat.com>\nMessage-id: 1432214378-31891-9-git-send-email-kwolf@redhat.com\nSigned-off-by: John Snow <jsnow@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/4964e18e490f3ecad35c9e4cc9b613316a98755e"},{"sha":"de6a92185e3ac25ba7d37f03e579b1fc72e70162","author":{"email":"d95f280a221ff712ada79312579d6df6c67a2d03@linux.vnet.ibm.com","name":"Pierre Morel"},"message":"virtio-ccw: add support for 9pfs\n\nThis patch adds 9pfs support for virtio-ccw\nby registering the virtio_ccw_9p_info type\nand adding associated callbacks.\n\nSigned-off-by: Pierre Morel <pmorel@linux.vnet.ibm.com>\nSigned-off-by: Christian Borntraeger <borntraeger@de.ibm.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/de6a92185e3ac25ba7d37f03e579b1fc72e70162"},{"sha":"2a72ea5f66b3b87a975475bdc1cabacbbb402937","author":{"email":"937084fec1b14b928d3b598c69ed20c9b59ffea8@linux.vnet.ibm.com","name":"Jason J. Herne"},"message":"virtio-ccw/migration: Migrate config vector for virtio devices\n\nvirtio_ccw_{save|load}_config are missing code to save and restore a vdev's\nconfig_vector value. This causes some virtio devices to become disabled\nfollowing a migration.\n\nThis patch fixes a bug whereby the qmp/hmp balloon command (virsh setmem)\nsilently fails to update the guest's available memory because the device was not\nproperly migrated.\n\nThis will break compatibility, but vmstate_s390_cpu was bumped from\nversion 2 to version 4 between v2.3.0 and v2.4.0 without a compat\nhandler. Furthermore, there is no production environment yet so\nmigration is fenced anyway between any relevant version of 2.3 and 2.4.\n\nSigned-off-by: Jason J. Herne <jjherne@linux.vnet.ibm.com>\nMessage-Id: <1433343843-803-1-git-send-email-jjherne@linux.vnet.ibm.com>\nReviewed-by: Michael S. Tsirkin <mst@redhat.com>\nSigned-off-by: Christian Borntraeger <borntraeger@de.ibm.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/2a72ea5f66b3b87a975475bdc1cabacbbb402937"},{"sha":"b853d4cbf2062813e84f9bb880feff8daf467e05","author":{"email":"be4224c72adedf72d459320ee497e22a37089288@linux.vnet.ibm.com","name":"Sascha Silbe"},"message":"s390x/kvm: always ignore empty vcpu interrupt state\n\nkvm_s390_vcpu_interrupt_pre_save() and\nkvm_s390_vcpu_interrupt_post_load() are essentially no-ops on hosts\nwithout KVM_CAP_S390_IRQ_STATE. Move the capability check after the\ncheck for saved IRQ state in kvm_s390_vcpu_interrupt_post_load() so that\nmigration between hosts without KVM_CAP_S390_IRQ_STATE (including save /\nrestore on the same host) continues to work.\n\nFixes: 3cda44f7bae5 (\"s390x/kvm: migrate vcpu interrupt state\")\nSigned-off-by: Sascha Silbe <silbe@linux.vnet.ibm.com>\nReviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>\nReviewed-by: Jens Freimann <jfrei@linux.vnet.ibm.com>\nSigned-off-by: Christian Borntraeger <borntraeger@de.ibm.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/b853d4cbf2062813e84f9bb880feff8daf467e05"},{"sha":"cb3d37a93cc59da400d27361fcda024d49210abd","author":{"email":"255103e50249e3d658441816e0597170ebfc16ef@redhat.com","name":"Michael S. Tsirkin"},"message":"acpi: add missing ssdt\n\ncommit 5cb18b3d7bff2a83275ee98af2a14eb9e21c93ab\n    TPM2 ACPI table support\n\nwas missing a file, so build with iasl fails\n(build without iasl works since it uses the generated\n hex files).\n\nReported-by: \"Daniel P. Berrange\" <berrange@redhat.com>\nSigned-off-by: Michael S. Tsirkin <mst@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/cb3d37a93cc59da400d27361fcda024d49210abd"},{"sha":"557772f26b361ade84acecb366fe6fdd2d55a6d9","author":{"email":"44592b4eea36663c86b994bb0ea99d15309c1c7d@redhat.com","name":"Marcel Apfelbaum"},"message":"hw/q35: fix floppy controller definition in ich9\n\nIn DSDT FDC0 declares the IO region as IO(Decode16, 0x03F2, 0x03F2, 0x00, 0x04).\nUse the same in lpc_ich9 initialization code.\nNow the floppy drive is detected correctly on Windows.\n\nSigned-off-by: Marcel Apfelbaum <marcel@redhat.com>\nReviewed-by: Michael S. Tsirkin <mst@redhat.com>\nSigned-off-by: Michael S. Tsirkin <mst@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/557772f26b361ade84acecb366fe6fdd2d55a6d9"},{"sha":"6652d0811c9463fbfb2d2d1cb2ec03f388145c5f","author":{"email":"808efd45667dbd241e4e026b5673172419ecb43e@redhat.com","name":"Jason Wang"},"message":"virtio-pci: don't try to mask or unmask vqs without notifiers\n\nWe should validate the vq index against nvqs_with_notifiers. Otherwise we may\ntry to mask or unmask vector for vqs without notifiers (e.g control vq). This\nwill lead qemu abort on kvm_irqchip_commit_routes() when trying to boot win8.1\nguest.\n\nFixes 851c2a75a6e80c8aa5e713864d98cfb512e7229b (\"virtio-pci: speedup MSI-X\nmasking and unmasking\")\n\nReported-by: Alex Williamson <alex.williamson@redhat.com>\nSigned-off-by: Jason Wang <jasowang@redhat.com>\nReviewed-by: Michael S. Tsirkin <mst@redhat.com>\nSigned-off-by: Michael S. Tsirkin <mst@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/6652d0811c9463fbfb2d2d1cb2ec03f388145c5f"},{"sha":"977ad992f14b29a7d4f18eaba42a705004545a64","author":{"email":"4eb2b4176e21acd3d234f4e32f1d523dec05716b@redhat.com","name":"Juan Quintela"},"message":"TPM: fix build with tpm disabled\n\nFailure was included on commit\n\nSigned-off-by: Juan Quintela <quintela@redhat.com>\nReviewed-by: Michael S. Tsirkin <mst@redhat.com>\nSigned-off-by: Michael S. Tsirkin <mst@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/977ad992f14b29a7d4f18eaba42a705004545a64"},{"sha":"d5aaa1b0456033fc9ff723ac881ebe1b61360cca","author":{"email":"cad73e70082427fddc9be3baaf34e698dffd21c0@redhat.com","name":"Gerd Hoffmann"},"message":"virtio: 64bit features fixups.\n\nCommit \"019a3ed virtio: make features 64bit wide\" missed a few changes,\nas I've noticed while trying to rebase the virtio-1 branch to latest\nmaster.  This patch adds them.\n\nSigned-off-by: Gerd Hoffmann <kraxel@redhat.com>\nReviewed-by: Michael S. Tsirkin <mst@redhat.com>\nSigned-off-by: Michael S. Tsirkin <mst@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/d5aaa1b0456033fc9ff723ac881ebe1b61360cca"},{"sha":"ca9b46bcecc0f06882eec1b152b71f93a066da79","author":{"email":"353a5266279d714de7e448f7bfb8ee55549e7a2c@cn.fujitsu.com","name":"Zhu Guihua"},"message":"acpi: add acpi_send_gpe_event() to rise sci for hotplug\n\nAdd a new API named acpi_send_gpe_event() to send hotplug SCI.\nThis API can be used by pci, cpu and memory hotplug.\n\nThis patch is rebased on master.\n\nSigned-off-by: Zhu Guihua <zhugh.fnst@cn.fujitsu.com>\nReviewed-by: Michael S. Tsirkin <mst@redhat.com>\nSigned-off-by: Michael S. Tsirkin <mst@redhat.com>\nReviewed-by: Igor Mammedov <imammedo@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/ca9b46bcecc0f06882eec1b152b71f93a066da79"},{"sha":"32d9ca15bac63e8a7bad6dc1a4ab624e6d6d3b0f","author":{"email":"44592b4eea36663c86b994bb0ea99d15309c1c7d@redhat.com","name":"Marcel Apfelbaum"},"message":"acpi: add implementation of aml_while() term\n\nCommit 68e6b0af7 (acpi: add aml_while() term) added\nthe definition of aml_while without the actual implementation.\nImplement the term.\n\nSigned-off-by: Marcel Apfelbaum <marcel@redhat.com>\nReviewed-by: Michael S. Tsirkin <mst@redhat.com>\nSigned-off-by: Michael S. Tsirkin <mst@redhat.com>\nAcked-by: Laszlo Ersek <lersek@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/32d9ca15bac63e8a7bad6dc1a4ab624e6d6d3b0f"},{"sha":"ce6a28ee057da3e4a587dada369e33a8486b0066","author":{"email":"ff16bdfdd9d424f6f8cd654846ab78104fe12092@redhat.com","name":"Marcel Apfelbaum"},"message":"hw/pci: made pci_bus_is_root a PCIBusClass method\n\nRefactoring it as a method of PCIBusClass will allow\ndifferent implementations for subclasses.\n\nRemoved the assumption that the root bus does not\nhave a parent device because is specific only\nto the default class implementation.\n\nSigned-off-by: Marcel Apfelbaum <marcel@redhat.com>\nReviewed-by: Michael S. Tsirkin <mst@redhat.com>\nSigned-off-by: Michael S. Tsirkin <mst@redhat.com>\nAcked-by: Laszlo Ersek <lersek@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/ce6a28ee057da3e4a587dada369e33a8486b0066"},{"sha":"602141d9974d726063907851528c89d617730156","author":{"email":"ff16bdfdd9d424f6f8cd654846ab78104fe12092@redhat.com","name":"Marcel Apfelbaum"},"message":"hw/pci: made pci_bus_num a PCIBusClass method\n\nRefactoring it as a method of PCIBusClass will allow\ndifferent implementations for subclasses.\n\nSigned-off-by: Marcel Apfelbaum <marcel@redhat.com>\nReviewed-by: Michael S. Tsirkin <mst@redhat.com>\nSigned-off-by: Michael S. Tsirkin <mst@redhat.com>\nAcked-by: Laszlo Ersek <lersek@redhat.com>","distinct":false,"url":"https://api.github.com/repos/stefanha/qemu/commits/602141d9974d726063907851528c89d617730156"}]}