{"push_id":758242735,"size":67,"distinct_size":67,"ref":"refs/heads/master","head":"d1a330d6263c41d622b610eda69644a84fb524f2","before":"6032e44fb5b37c60484e62813c254a40254b70d8","commits":[{"sha":"fe1b43725e4a9cfeaf5f8aa6b6c3ece7d695c114","author":{"email":"420c9fb3407b8e11ac322a0e7703f7b1f526df04@gmail.com","name":"Chandler Carruth"},"message":"[LIR] Handle the LoopInfo the same as all the other analyses. No utility\nreally in breaking pattern just for this analysis.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244878 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/fe1b43725e4a9cfeaf5f8aa6b6c3ece7d695c114"},{"sha":"0e593a62f657547c6a7af6dc9710fc055a9c4da0","author":{"email":"420c9fb3407b8e11ac322a0e7703f7b1f526df04@gmail.com","name":"Chandler Carruth"},"message":"[LIR] Start leveraging the fundamental guarantees of a loop in\nsimplified form to remove redundant checks and simplify the code for\npopcount recognition. We don't actually need to handle all of these\ncases.\n\nI've left a FIXME for one in particular until I finish inspecting to\nmake sure we don't actually *rely* on the predicate in any way.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244879 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/0e593a62f657547c6a7af6dc9710fc055a9c4da0"},{"sha":"8d26d44905de0eb2b521601c83b6e540a156d94d","author":{"email":"420c9fb3407b8e11ac322a0e7703f7b1f526df04@gmail.com","name":"Chandler Carruth"},"message":"[LIR] Handle access to AliasAnalysis the same way as the other analysis\nin LoopIdiomRecognize. This is what started me staring at this code. Now\nmigrating it with the new AA stuff will be trivial.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244880 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/8d26d44905de0eb2b521601c83b6e540a156d94d"},{"sha":"4d88daed013941dc52e7ddc6ee13fc94e3b0189e","author":{"email":"3f191f7e56d8235b9d4182e8a59f87e3c682b12a@arm.com","name":"John Brawn"},"message":"[ARM] Reorganise and simplify thumb-1 load/store selection\n\nOther than PC-relative loads/store the patterns that match the various\nload/store addressing modes have the same complexity, so the order that they\nare matched is the order that they appear in the .td file.\n\nRearrange the instruction definitions in ARMInstrThumb.td, and make use of\nAddedComplexity for PC-relative loads, so that the instruction matching order\nis the order that results in the simplest selection logic. This also makes\nregister-offset load/store be selected when it should, as previously it was\nonly selected for too-large immediate offsets.\n\nDifferential Revision: http://reviews.llvm.org/D11800\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244882 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/4d88daed013941dc52e7ddc6ee13fc94e3b0189e"},{"sha":"22fb0aaa3c1c466ebf722ce038d7a69067ca45d3","author":{"email":"3ff30fa4b45f04b1c232545cdfbab1a16d9463c5@gmail.com","name":"Ashutosh Nema"},"message":"Test Commit.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244883 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/22fb0aaa3c1c466ebf722ce038d7a69067ca45d3"},{"sha":"b260fa8a14e51504a11a7219fde727fc6cec0e65","author":{"email":"9b2c8b141eef38bf7753dfb1c8fa91c2be5946ad@linaro.org","name":"Renato Golin"},"message":"Revert \"[LIR] Handle access to AliasAnalysis the same way as the other analysis in LoopIdiomRecognize.\"\n\nThis reverts commit r244880, as it broke the test-suite on\nSingleSource/Regression/C/2004-03-15-IndirectGoto in AArch64.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244884 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/b260fa8a14e51504a11a7219fde727fc6cec0e65"},{"sha":"26f2b3561ceda3484a1ee2bb9396087f596db516","author":{"email":"9b2c8b141eef38bf7753dfb1c8fa91c2be5946ad@linaro.org","name":"Renato Golin"},"message":"Revert \"[LIR] Start leveraging the fundamental guarantees of a loop...\"\n\nThis reverts commit r244879, as it broke the test-suite on\nSingleSource/Regression/C/2004-03-15-IndirectGoto in AArch64.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244885 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/26f2b3561ceda3484a1ee2bb9396087f596db516"},{"sha":"99985c9fac383c3b433f15237e2761afcaef7ee3","author":{"email":"668fee4df0f19a4cdadb88bb7cf11ae1d9674c1f@arm.com","name":"Charlie Turner"},"message":"[InstCombinePHI] Partial simplification of identity operations.\n\nConsider this code:\n\nBB:\n  %i = phi i32 [ 0, %if.then ], [ %c, %if.else ]\n  %add = add nsw i32 %i, %b\n  ...\n\nIn this common case the add can be moved to the %if.else basic block, because\nadding zero is an identity operation. If we go though %if.then branch it's\nalways a win, because add is not executed; if not, the number of instructions\nstays the same.\n\nThis pattern applies also to other instructions like sub, shl, shr, ashr | 0,\nmul, sdiv, div | 1.\n\nPatch by Jakub Kuderski!\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244887 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/99985c9fac383c3b433f15237e2761afcaef7ee3"},{"sha":"e65e298541646322234f94dab3387b165e65f704","author":{"email":"666af9c7e7c44f7b1a6415c1f07084e8abb68553@gmail.com","name":"Yaron Keren"},"message":"Remove raw_svector_ostream::resync and users. It's no-op after r244870.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244888 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/e65e298541646322234f94dab3387b165e65f704"},{"sha":"69585fd51be3cf8ebeec649f1d3ba33e47759a68","author":{"email":"dfbb67861321c3a0b65599ad75850a0b877f5c0d@de.ibm.com","name":"Ulrich Weigand"},"message":"[SystemZ] Support large LLVM IR struct return values\n\nRecent mesa/llvmpipe crashes on SystemZ due to a failed assertion when\nattempting to compile a routine with a return type of\n  { <4 x float>, <4 x float>, <4 x float>, <4 x float> }\non a system without vector instruction support.\n\nThis is because after legalizing the vector type, we get a return value\nconsisting of 16 floats, which cannot all be returned in registers.\n\nUsually, what should happen in this case is that the target's CanLowerReturn\nroutine rejects the return type, in which case SelectionDAG falls back to\nimplementing a structure return in memory via implicit reference.\n\nHowever, the SystemZ target never actually implemented any CanLowerReturn\nroutine, and thus would accept any struct return type.\n\nThis patch fixes the crash by implementing CanLowerReturn.  As a side effect,\nthis also handles fp128 return values, fixing a todo that was noted in\nSystemZCallingConv.td.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244889 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/69585fd51be3cf8ebeec649f1d3ba33e47759a68"},{"sha":"ccc0cf3d8de133f2e100ae3a69d0414479ae435f","author":{"email":"25bde77e144fcca55ce01543af70cbcf516b8a17@microsoft.com","name":"Joseph Tremoulet"},"message":"[WinEHPrepare] Update demotion logic\n\nSummary:\nUpdate the demotion logic in WinEHPrepare to avoid creating new cleanups by\nwalking predecessors as necessary to insert stores for EH-pad PHIs.\n\nAlso avoid creating stores for EH-pad PHIs that have no uses.\n\nThe store/load placement is still pretty naive.  Likely future improvements\n(at least for optimized compiles) include:\n - Share loads for related uses as possible\n - Coalesce non-interfering use/def-related PHIs\n - Store at definition point rather than each PHI pred for non-interfering\n   lifetimes.\n\n\nReviewers: rnk, majnemer\n\nSubscribers: llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D11955\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244894 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/ccc0cf3d8de133f2e100ae3a69d0414479ae435f"},{"sha":"319eb435fdff72025399ed3448103aa2d22c8162","author":{"email":"15ca74a11a0ab8a7615bd8f2695eec9feb05b533@imgtec.com","name":"Petar Jovanovic"},"message":"[mips][mcjit] Calculate correct addend for HI16 and PCHI16 reloc\n\nPreviously, for O32 ABI we did not calculate correct addend for R_MIPS_HI16\nand R_MIPS_PCHI16 relocations. This patch fixes that.\n\nPatch by Vladimir Radosavljevic.\n\nDifferential Revision: http://reviews.llvm.org/D11186\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244897 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/319eb435fdff72025399ed3448103aa2d22c8162"},{"sha":"22af77d94f33359da9a26c7048e586027f4217bc","author":{"email":"f1682ebb83d0ce00b2767a78fc8ea26a8af24e40@apple.com","name":"Erik Eckstein"},"message":"[DeadStoreElimination] remove a redundant store even if the load is in a different block.\n\nDeadStoreElimination does eliminate a store if it stores a value which was loaded from the same memory location.\nSo far this worked only if the store is in the same block as the load.\nNow we can also handle stores which are in a different block than the load.\nExample:\n\ndefine i32 @test(i1, i32*) {\nentry:\n  %l2 = load i32, i32* %1, align 4\n  br i1 %0, label %bb1, label %bb2\nbb1:\n  br label %bb3\nbb2:\n  ; This store is redundant\n  store i32 %l2, i32* %1, align 4\n  br label %bb3\nbb3:\n  ret i32 0\n}\n\nDifferential Revision: http://reviews.llvm.org/D11854\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244901 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/22af77d94f33359da9a26c7048e586027f4217bc"},{"sha":"8eafed2468df19fa7968cb73d0f3390ca194acdc","author":{"email":"f4a524c472c347a18d71daaa7c4ae51db69c69da@arm.com","name":"James Molloy"},"message":"[AArch64] Small rejig of fmax tests, NFCI.\n\nThese tests relied on -enable-no-nans-fp-math, whereas soon they'll take their no-nans hint\nfrom the FCMP instruction itself, so split the no-nans stuff out into its own test.\n\nAlso do a slight rejig of instruction order. The old FMIN/MAX backend matching had to deal with looking through casts, which it never did particularly well. Now, instcombine will recognize such patterns and canonicalize the cast outside the select. So modify the test inputs to assume that instcombine has already run.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244913 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/8eafed2468df19fa7968cb73d0f3390ca194acdc"},{"sha":"a215ac72efafea763642ce51e7272811904d3899","author":{"email":"f4a524c472c347a18d71daaa7c4ae51db69c69da@arm.com","name":"James Molloy"},"message":"[ARM] Rejig vmax tests a bit\n\nThey rely on global fast-math options, but soon ISel will rely only on fast-math flags on the instructions themselves. Rip the fast checks out into their own file so we can mark their instructions as fast.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244914 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/a215ac72efafea763642ce51e7272811904d3899"},{"sha":"377a93dbc219b7fe3db09590038a3c9b55deb6cb","author":{"email":"f4a524c472c347a18d71daaa7c4ae51db69c69da@arm.com","name":"James Molloy"},"message":"[ARM] Allow vmin/vmax of scalars to be emitted without UseNEONForFP.\n\nThis overrides the default to more closely resemble the hand-crafted matching logic in ISelLowering. It makes sense, as there is no VFP equivalent of vmin or vmax, to use them when they're available even if in general VFP ops should be preferred.\n\nThis should be NFC.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244915 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/377a93dbc219b7fe3db09590038a3c9b55deb6cb"},{"sha":"1da1d0218a4a98ca639cbf0555768342e6356d78","author":{"email":"f4a524c472c347a18d71daaa7c4ae51db69c69da@arm.com","name":"James Molloy"},"message":"[ARM] FMINNAN/FMAXNAN of f64 are not legal.\n\nThis was my error. We've got f32 marked as legal because they're simulated using a v2f32 instruction, but there's no equivalent for f64.\n\nThis will get test coverage imminently when D12015 lands.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244916 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/1da1d0218a4a98ca639cbf0555768342e6356d78"},{"sha":"ea56ef761a84bb8895ad74bc8cf5fb91f6c78695","author":{"email":"9428bd23029ebfb129ce84c48692a41755707bcc@gmail.com","name":"Igor Laevsky"},"message":"Emit argmemonly attribute for intrinsics.\n\nDifferential Revision: http://reviews.llvm.org/D11352\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244920 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/ea56ef761a84bb8895ad74bc8cf5fb91f6c78695"},{"sha":"31f6eee816354985afaa63fabf61d88271627811","author":{"email":"45bf114cdd73ecde1770a9f5e3798efd6171525d@gmail.com","name":"Nemanja Ivanovic"},"message":"Scalar to vector conversions using direct moves\n\nThis patch corresponds to review:\nhttp://reviews.llvm.org/D11471\n\nIt improves the code generated for converting a scalar to a vector value. With\ndirect moves from GPRs to VSRs, we no longer require expensive stack operations\nfor this. Subsequent patches will handle the reverse case and more general\noperations between vectors and their scalar elements.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244921 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/31f6eee816354985afaa63fabf61d88271627811"},{"sha":"34509ffd82b5929133008e234c490cee8ca5d4b9","author":{"email":"3b9de09f2ff76afe9f0ad4fcae4ff68f52ec7fc4@mxc.ca","name":"Nick Lewycky"},"message":"Fix GCC warning: extra `;' [-Wpedantic].\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244924 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/clang-omp/llvm_trunk/commits/34509ffd82b5929133008e234c490cee8ca5d4b9"}]}