{"push_id":539018330,"size":79,"distinct_size":15,"ref":"refs/heads/base","head":"e016fc506f4082e9de851280dcf506cc74652a38","before":"c5ee967ad1381aed365e85c44edf825838aa2298","commits":[{"sha":"2bf48026fd5ab324f673d4b0a15c049d5d45bcd6","author":{"email":"0248c409272006b82e722911641e2bc353c9683f@gmail.com","name":"Jagannadha Sutradharudu Teki"},"message":"mtd: sf: Zap ramtron driver\n\nRemoved ramtron driver since the EMK boards are\nno longer been active, and these are the only boards\nused this flash driver.\n\nCommit details for EMK zap:\n\"ppc/arm: zap EMK boards\"\n(sha1: d58a9451e7339ed4cf2b2627e534611f427fb791)\n\nSigned-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>\nCc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/2bf48026fd5ab324f673d4b0a15c049d5d45bcd6"},{"sha":"b45a3de086fd1e1eed792970c475ca93e8bec29a","author":{"email":"1404ba22ec6d20cf6fb19ba4d38ae7b07053223f@freescale.com","name":"Shengzhou Liu"},"message":"mtd/spi: Add support for SST25WF040B\n\nAdd support for SST25WF040B-40I-SN flash.\nTested on T1024QDS board.\n\nSigned-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/b45a3de086fd1e1eed792970c475ca93e8bec29a"},{"sha":"cf156007e08c31d4f21614da87e6634e7ed98047","author":{"email":"f415fb01e2fe2ed291d1c7df9fd8d02be4e39890@codethink.co.uk","name":"Adnan Ali"},"message":"sf: sf_params: Add S25FL116K flash support\n\nAdded S25FL116K flash and tested on Marvell 88F6281 based system.\n\nSigned-off-by: Adnan Ali <adnan.ali@codethink.co.uk>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/cf156007e08c31d4f21614da87e6634e7ed98047"},{"sha":"babe6994ca28e5a354ee32b33b7a54b0276d9df1","author":{"email":"f415fb01e2fe2ed291d1c7df9fd8d02be4e39890@codethink.co.uk","name":"Adnan Ali"},"message":"sf: sf_params: Add S25FL164K flash identifier info\n\nAdd the necessary flash entry for the Spansion S25FL164K\nflash. Tested on Marvell 88F6218 based design.\n\nSigned-off-by: Ben Dooks <ben.dooks@codethink.co.uk>\nReviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/babe6994ca28e5a354ee32b33b7a54b0276d9df1"},{"sha":"839e4f7c66877ade9024d1f2adfabd727e231cbc","author":{"email":"44592b4eea36663c86b994bb0ea99d15309c1c7d@ziswiler.com","name":"Marcel Ziswiler"},"message":"ARM: tegra: colibri_t30: comment style fix\n\nSigned-off-by: Marcel Ziswiler <marcel@ziswiler.com>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/839e4f7c66877ade9024d1f2adfabd727e231cbc"},{"sha":"ed710457a52ff09880af52540c997615adbc91ee","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: Implement non-cached memory support\n\nImplement an API that can be used by drivers to allocate memory from a\npool that is mapped uncached. This is useful if drivers would otherwise\nneed to do extensive cache maintenance (or explicitly maintaining the\ncache isn't safe).\n\nThe API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.\nBoards can set this to the size to be used for the non-cached area. The\narea will typically be right below the malloc() area, but architectures\nshould take care of aligning the beginning and end of the area to honor\nany mapping restrictions. Architectures must also ensure that mappings\nestablished for this area do not overlap with the malloc() area (which\nshould remain cached for improved performance).\n\nWhile the API is currently only implemented for ARM v7, it should be\ngeneric enough to allow other architectures to implement it as well.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/ed710457a52ff09880af52540c997615adbc91ee"},{"sha":"6173c45b21ca584fd691b21dc81a44d852d4bdce","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"power: Add AMS AS3722 PMIC support\n\nThe AS3722 provides a number of DC/DC converters and LDOs as well as 8\nGPIOs.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/6173c45b21ca584fd691b21dc81a44d852d4bdce"},{"sha":"a7230745504552095594362b81caaa33b5d7da5e","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Implement tegra_plle_enable()\n\nThis function is required by PCIe and SATA. This patch implements it on\nTegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because\nit doesn't support PCIe or SATA.\n\nAcked-by: Stephen Warren <swarren@nvidia.com>\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/a7230745504552095594362b81caaa33b5d7da5e"},{"sha":"59cb3bf4c6d87448b4fb4e0fd386ac6d170a19b6","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Provide PCIEXCLK reset ID\n\nThis reset is required for PCIe and the corresponding ID therefore needs\nto be defined. The enumeration value for this was properly defined on\nsome SoCs but not on others. Similarly, some contained it in the mapping\nof peripheral IDs to clock IDs, other didn't. This patch defines it\nconsistently for all supported SoC generations.\n\nAcked-by: Stephen Warren <swarren@nvidia.com>\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/59cb3bf4c6d87448b4fb4e0fd386ac6d170a19b6"},{"sha":"48510c089b18482de36210ec3f70d8908e8daf90","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Implement powergate support\n\nImplement the powergate API that allows various power partitions to be\npower up and down.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/48510c089b18482de36210ec3f70d8908e8daf90"},{"sha":"79c7a90f6c642c27da3de5c134816be7f0405f1d","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Implement XUSB pad controller\n\nThis controller was introduced on Tegra114 to handle XUSB pads. On\nTegra124 it is also used for PCIe and SATA pin muxing and PHY control.\nOnly the Tegra124 PCIe and SATA functionality is currently implemented,\nwith weak symbols on Tegra114.\n\nTegra20 and Tegra30 also provide weak symbols for these functions so\nthat drivers can use the same API irrespective of which SoC they're\nbeing built for.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/79c7a90f6c642c27da3de5c134816be7f0405f1d"},{"sha":"78e9f1c4f3b9887cef2c5528dbe0b4f5c335eaa0","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Add XUSB pad controller on Tegra124\n\nThe XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA\nlanes.\n\nAcked-by: Stephen Warren <swarren@nvidia.com>\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/78e9f1c4f3b9887cef2c5528dbe0b4f5c335eaa0"},{"sha":"b02f3e0c2ddefd6754861f2456cf63a9d5cb64b0","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Enable XUSB pad controller on Jetson TK1\n\nAdd the PCIe and SATA lane configuration to the Jetson TK1 device tree,\nso that the XUSB pad controller can be appropriately configured.\n\nAcked-by: Stephen Warren <swarren@nvidia.com>\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/b02f3e0c2ddefd6754861f2456cf63a9d5cb64b0"},{"sha":"f315828b0d31cac2559af626f75bcb7f5a0ac524","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"pci: tegra: Add Tegra PCIe driver\n\nAdd support for the PCIe controller found on some generations of Tegra.\nTegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root\nports with a total of 6 lanes and Tegra124 has 2 root ports with a total\nof 5 lanes.\n\nThis is based on the Linux kernel driver, originally submitted upstream\nby Mike Rapoport.\n\nSigned-off-by: Mike Rapoport <mike@compulab.co.il>\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/f315828b0d31cac2559af626f75bcb7f5a0ac524"},{"sha":"65d2465d5d4cdb347506438b226b01d6ef0eec79","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Add Tegra20 PCIe device tree node\n\nAdd the device tree node for the PCIe controller found on Tegra20 SoCs.\n\nAcked-by: Stephen Warren <swarren@nvidia.com>\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/65d2465d5d4cdb347506438b226b01d6ef0eec79"},{"sha":"7dd8738f08144b01d91185f250af9ce2648cb25f","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Enable PCIe on TrimSlice\n\nThe TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the\nPCIe controller and the network driver so that the device can boot over\nthe network.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/7dd8738f08144b01d91185f250af9ce2648cb25f"},{"sha":"cd998761208f408dea678ae0f11c18f270cf9e71","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Add GIC for Tegra30\n\nAdd a device tree node for the GIC found on Tegra30. U-Boot doesn't use\nit directly but subsequent patches will add device tree nodes that\nreference it by phandle.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/cd998761208f408dea678ae0f11c18f270cf9e71"},{"sha":"a1811bc5b999998ef5f42e2312a1140eb7cf3957","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Add Tegra30 PCIe device tree node\n\nAdd the device tree node for the PCIe controller found on Tegra30 SoCs.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/a1811bc5b999998ef5f42e2312a1140eb7cf3957"},{"sha":"5a2c96a0e5d1dfc13f71b295f07be8a4b7ac8fdb","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Enable PCIe on Cardhu\n\nThe PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC\nis available on the dock over the PCIe bus. Enable the PCIe controller\nand the network device driver so that the device can boot over the\nnetwork.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/5a2c96a0e5d1dfc13f71b295f07be8a4b7ac8fdb"},{"sha":"affe026928db2f1579261ca3b80fe28b6b9f3765","author":{"email":"3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com","name":"Thierry Reding"},"message":"ARM: tegra: Enable PCIe on Beaver\n\nThe Beaver has an ethernet NIC connected to the PCIe bus. Enable the\nPCIe controller and the network device driver so that the device can\nboot over the network.\n\nIn addition the board has a mini-PCIe expansion slot.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Tom Warren <twarren@nvidia.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/u-boot-yamada/commits/affe026928db2f1579261ca3b80fe28b6b9f3765"}]}