{"push_id":602484505,"size":15,"distinct_size":15,"ref":"refs/heads/master","head":"9014bb0b1da1950599fe8f2a31be88f10832914e","before":"6ed590685cab47e85dc92283e925132e30a48217","commits":[{"sha":"b15be6308b34abde69f76c0354fd53c98e3d56cc","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" sched: reinitialize rq->next_balance when a CPU is hot-added\n\nSigned-off-by: Paul Walmsley <pwalmsley@nvidia.com>\nCc: Peter Boonstoppel <pboonstoppel@nvidia.com>\nReviewed-on: http://git-master/r/208927\nReviewed-by: Automatic_Commit_Validation_User\nReviewed-by: Peter Zu <pzu@nvidia.com>\nReviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>\nGVS: Gerrit_Virtual_Submit\nTested-by: Peter Zu <pzu@nvidia.com>\nReviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/b15be6308b34abde69f76c0354fd53c98e3d56cc"},{"sha":"c347364a95ce0fe0f758075c4bcc07cb4461ceb7","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: move VFP init to an earlier boot stage\n\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/c347364a95ce0fe0f758075c4bcc07cb4461ceb7"},{"sha":"4c893dcdfe3a4b346244315427296662df8015ad","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: be strict about FP exceptions in kernel mode\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel at linaro.org>\nAcked-by: Nicolas Pitre <nico at linaro.org>\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/4c893dcdfe3a4b346244315427296662df8015ad"},{"sha":"4597ee26372edf4d851930ad266b5003f22f4f90","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: add support for kernel mode NEON\n\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/4597ee26372edf4d851930ad266b5003f22f4f90"},{"sha":"72c2bee8e1beb8dfa2a768afcfb1183810fb42a0","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: crypto: add NEON accelerated XOR implementation\n\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nAcked-by: Nicolas Pitre <nico@linaro.org>\n\nARM: 7835/2: fix modular build of xor_blocks() with NEON enabled\n\nReported-by: Josh Boyer <jwboyer@fedoraproject.org>\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/72c2bee8e1beb8dfa2a768afcfb1183810fb42a0"},{"sha":"d0ddbcd97d25e5e700cd2e1f1e1133731e42bb39","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: only allow kernel mode neon with AEABI\n\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/d0ddbcd97d25e5e700cd2e1f1e1133731e42bb39"},{"sha":"3f02e94500ab28a97c7b1b13978012b09edbf1c3","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" arm: vfpmodule: Fix warning procfs vfp_bounce reporting failed\n\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/3f02e94500ab28a97c7b1b13978012b09edbf1c3"},{"sha":"b9ac93f72f5b5f57924ee39a831704a38aca0635","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" Asynchronous Fsync: initial extraction of Async Fsync from HTC\n\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/b9ac93f72f5b5f57924ee39a831704a38aca0635"},{"sha":"7b589f22e0927950d14bebae6d7f4ba03c996e64","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: mm: rename jump labels in v7_flush_dcache_all function\n\nThis patch renames jump labels in v7_flush_dcache_all in order to define\na specific flush cache levels entry point.\n\nTODO: factor out the level flushing loop if considered worthwhile and\n      define the input registers requirements.\n\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>\nSigned-off-by: Paul Reioux <reioux@gmail.com>\n\nConflicts:\n\tarch/arm/mm/cache-v7.S","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/7b589f22e0927950d14bebae6d7f4ba03c996e64"},{"sha":"6a07eb742fae49371ca7fac9ef702677328deddd","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: kernel: update cpu_suspend code to use cache LoUIS operations\n\nIn processors like A15/A7 L2 cache is unified and integrated within the\nprocessor cache hierarchy, so that it is not considered an outer cache\nanymore. For processors like A15/A7 flush_cache_all() ends up cleaning\nall cache levels up to Level of Coherency (LoC) that includes\nthe L2 unified cache.\n\nWhen a single CPU is suspended (CPU idle) a complete L2 clean is not\nrequired, so generic cpu_suspend code must clean the data cache using the\nnewly introduced cache LoUIS function.\n\nThe context and stack pointer (context pointer) are cleaned to main memory\nusing cache area functions that operate on MVA and guarantee that the data\nis written back to main memory (perform cache cleaning up to the Point of\nCoherency - PoC) so that the processor can fetch the context when the MMU\nis off in the cpu_resume code path.\n\nouter_cache management remains unchanged.\n\nReviewed-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/6a07eb742fae49371ca7fac9ef702677328deddd"},{"sha":"931ec4914e6be3e97f224f300db1e1f7cdb9bed9","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API\n\nWhen a CPU is hotplugged out caches that reside in its power domain\nlose their contents and so must be cleaned to the next memory level.\n\nCurrently, __cpu_disable calls flush_cache_all() that for new generation\nprocessor like A15/A7 ends up cleaning and invalidating all cache levels\nup to Level of Coherency, which includes the unified L2.\n\nThis ends up being a waste of cycles since the L2 cache contents are not\nlost on power down.\n\nThis patch updates __cpu_disable to use the new LoUIS API cache operations.\n\nReviewed-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/931ec4914e6be3e97f224f300db1e1f7cdb9bed9"},{"sha":"6d477e4d5b20f8b263cfb2cab7b5c1485d9b7a29","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API\n\nThe ARMv7 processor setup function __v7_setup() cleans and invalidates the\nCPU cache before enabling MMU to start the CPU with a clean CPU local cache.\n\nBut on ARMv7 architectures like Cortex-[A15/A8], this code will end\nup flushing the L2 caches(up to level of Coherency) which is undesirable\nand expensive. The setup functions are used in the CPU hotplug scenario too\nand hence flushing all cache levels should be avoided.\n\nThis patch replaces the cache flushing call with the newly introduced\nv7 dcache LoUIS API where only cache levels up to LoUIS are cleaned and\ninvalidated when a processors executes __v7_setup which is the expected\nbehavior.\n\nFor processors like A9 and A5 where the L2 cache is an outer one the\nbehavior should be unchanged.\n\nSigned-off-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/6d477e4d5b20f8b263cfb2cab7b5c1485d9b7a29"},{"sha":"a0d3a3a65a881b118620edca33c335d0d5adb08e","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" jiffies conversions: Use compile time constants when possible\n\nDate\tFri, 04 Jan 2013 13:15:43 -0800\n\nDo the multiplications and divisions at compile time\ninstead of runtime when the converted value is a constant.\n\nMake the calculation functions static __always_inline to jiffies.h.\n\nAdd #defines with __builtin_constant_p to test and use the\nstatic inline or the runtime functions as appropriate.\n\nPrefix the old exported symbols/functions with __\n\nSigned-off-by: Paul Reioux <reioux@gmail.com>","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/a0d3a3a65a881b118620edca33c335d0d5adb08e"},{"sha":"c00932a9634be53d30699d710d6db269ba1fd2fb","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: Add support for 64 bit register reads/writes\n\nAdd macros to read and write to 64 bit registers.\n\nSigned-off-by: Olav Haugan <ohaugan@codeaurora.org>\n\nConflicts:\n\tarch/arm/include/asm/io.h\n\nChange-Id: Ied2b38e6a3803377cd271fe7b13f6cf0fc586e70","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/c00932a9634be53d30699d710d6db269ba1fd2fb"},{"sha":"9014bb0b1da1950599fe8f2a31be88f10832914e","author":{"email":"dab1ac482cbf0c585f9ac2c32308f0f07e56569c@outlook.com","name":"Tkkg1994"},"message":" ARM: mm: implement LoUIS API for cache maintenance ops\n\nARM v7 architecture introduced the concept of cache levels and related\ncontrol registers. New processors like A7 and A15 embed an L2 unified\ncache\ncontroller that becomes part of the cache level hierarchy. Some\noperations in\nthe kernel like cpu_suspend and __cpu_disable do not require a flush of\nthe\nentire cache hierarchy to DRAM but just the cache levels belonging to\nthe\nLevel of Unification Inner Shareable (LoUIS), which in most of ARM v7\nsystems\ncorrespond to L1.\n\nThe current cache flushing API used in cpu_suspend and __cpu_disable,\nflush_cache_all(), ends up flushing the whole cache hierarchy since for\nv7 it cleans and invalidates all cache levels up to Level of Coherency\n(LoC) which cripples system performance when used in hot paths like\nhotplug\nand cpuidle.\n\nTherefore a new kernel cache maintenance API must be added to cope with\nlatest ARM system requirements.\n\nThis patch adds flush_cache_louis() to the ARM kernel cache maintenance\nAPI.\n\nThis function cleans and invalidates all data cache levels up to the\nLevel of Unification Inner Shareable (LoUIS) and invalidates the\ninstruction\ncache for processors that support it (> v7).\n\nThis patch also creates an alias of the cache LoUIS function to\nflush_kern_all\nfor all processor versions prior to v7, so that the current cache\nflushing\nbehaviour is unchanged for those processors.\n\nv7 cache maintenance code implements a cache LoUIS function that cleans\nand\ninvalidates the D-cache up to LoUIS and invalidates the I-cache,\naccording\nto the new API.\n\nReviewed-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>\n\nSigned-off-by: Paul Reioux <reioux@gmail.com>\n\nConflicts:\n\tarch/arm/mm/cache-v7.S","distinct":true,"url":"https://api.github.com/repos/Tkkg1994/Hulk-Kernel-V2/commits/9014bb0b1da1950599fe8f2a31be88f10832914e"}]}