{"push_id":826807457,"size":2,"distinct_size":2,"ref":"refs/heads/smm3_v3","head":"3263df07d8c9768f7dca07742a20893e2a15add2","before":"01396f28dcf4d606476c9f839216754b3626d8a5","commits":[{"sha":"4e41ea50465ffb33c547312009085c2c935a6449","author":{"email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com","name":"Paolo Bonzini"},"message":"UefiCpuPkg: PiSmmCpuDxeSmm: do not execute RSM from 64-bit mode\n\nAccording to Intel this is invalid.  Go back to 32-bit protected mode and\nclear EFER.LME before executing RSM.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":true,"url":"https://api.github.com/repos/bonzini/edk2/commits/4e41ea50465ffb33c547312009085c2c935a6449"},{"sha":"3263df07d8c9768f7dca07742a20893e2a15add2","author":{"email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com","name":"Paolo Bonzini"},"message":"OvmfPkg: use relaxed AP SMM synchronization mode\n\nPort 0xb2 on QEMU only sends an SMI to the currently executing processor.\nThe SMI handler, however, and in particular SmmWaitForApArrival, currently\nexpects that SmmControl2DxeTrigger triggers an SMI IPI on all processors\nrather than just the BSP.  Thus all SMM invocations loop for a second (the\ndefault value of PcdCpuSmmApSyncTimeout) before SmmWaitForApArrival sends\nanother SMI IPI to the APs.\n\nWith the default SmmCpuFeaturesLib, 32-bit machines must broadcast SMIs\nbecause 32-bit machines must reset the MTRRs on each entry to system\nmanagement modes (they have no SMRRs).  However, our virtual platform\ndoes not have problems with cacheability of SMRAM, so we can use \"directed\"\nSMIs instead.  To do this, just set gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode\nto 1 (aka SmmCpuSyncModeRelaxedAp).  This fixes SMM on multiprocessor virtual\nmachines.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":true,"url":"https://api.github.com/repos/bonzini/edk2/commits/3263df07d8c9768f7dca07742a20893e2a15add2"}]}