{"action":"opened","issue":{"url":"https://api.github.com/repos/voidlinux/void-packages/issues/1017","labels_url":"https://api.github.com/repos/voidlinux/void-packages/issues/1017/labels{/name}","comments_url":"https://api.github.com/repos/voidlinux/void-packages/issues/1017/comments","events_url":"https://api.github.com/repos/voidlinux/void-packages/issues/1017/events","html_url":"https://github.com/voidlinux/void-packages/issues/1017","id":58770012,"number":1017,"title":"glibc-devel on x86_64 uses TSX instructions","user":{"login":"strake","id":976729,"avatar_url":"https://avatars.githubusercontent.com/u/976729?v=3","gravatar_id":"","url":"https://api.github.com/users/strake","html_url":"https://github.com/strake","followers_url":"https://api.github.com/users/strake/followers","following_url":"https://api.github.com/users/strake/following{/other_user}","gists_url":"https://api.github.com/users/strake/gists{/gist_id}","starred_url":"https://api.github.com/users/strake/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/strake/subscriptions","organizations_url":"https://api.github.com/users/strake/orgs","repos_url":"https://api.github.com/users/strake/repos","events_url":"https://api.github.com/users/strake/events{/privacy}","received_events_url":"https://api.github.com/users/strake/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":0,"created_at":"2015-02-24T17:13:08Z","updated_at":"2015-02-24T17:13:08Z","closed_at":null,"body":"XEND in particular, which is illegal on many machines, including mine.\r\n\r\nI tried configuring with --disable-lock-elision and building with -march=x86-64, in vain.\r\n\r\n$ objdump -d /lib/libpthread.a\r\n\r\n    pthread_rwlock_unlock.o:     file format elf64-x86-64\r\n    \r\n    \r\n    Disassembly of section .text:\r\n    \r\n    0000000000000000 <__pthread_rwlock_unlock>:\r\n       0:\t49 89 f8             \tmov    %rdi,%r8\r\n       3:\t8b 7f 18             \tmov    0x18(%rdi),%edi\r\n       6:\t85 ff                \ttest   %edi,%edi\r\n       8:\t75 16                \tjne    20 <__pthread_rwlock_unlock+0x20>\r\n       a:\t41 8b 70 04          \tmov    0x4(%r8),%esi\r\n       e:\t85 f6                \ttest   %esi,%esi\r\n      10:\t75 0e                \tjne    20 <__pthread_rwlock_unlock+0x20>\r\n      12:\t0f 01 d5             \txend   \r\n      15:\t31 c0                \txor    %eax,%eax\r\n      17:\tc3                   \tretq   \r\n      18:\t0f 1f 84 00 00 00 00 \tnopl   0x0(%rax,%rax,1)\r\n      1f:\t00 \r\n      20:\tbf 01 00 00 00       \tmov    $0x1,%edi\r\n      25:\t31 c0                \txor    %eax,%eax\r\n      27:\t41 8b 70 1c          \tmov    0x1c(%r8),%esi\r\n      2b:\tf0 41 0f b1 38       \tlock cmpxchg %edi,(%r8)\r\n      30:\t74 16                \tje     48 <__pthread_rwlock_unlock+0x48>\r\n      32:\t49 8d 38             \tlea    (%r8),%rdi\r\n      35:\t48 81 ec 80 00 00 00 \tsub    $0x80,%rsp\r\n      3c:\te8 00 00 00 00       \tcallq  41 <__pthread_rwlock_unlock+0x41>\r\n      41:\t48 81 c4 80 00 00 00 \tadd    $0x80,%rsp\r\n      48:\t41 8b 40 18          \tmov    0x18(%r8),%eax\r\n      4c:\t85 c0                \ttest   %eax,%eax\r\n      4e:\t75 70                \tjne    c0 <__pthread_rwlock_unlock+0xc0>\r\n      50:\t41 8b 40 04          \tmov    0x4(%r8),%eax\r\n      54:\t83 e8 01             \tsub    $0x1,%eax\r\n      57:\t85 c0                \ttest   %eax,%eax\r\n      59:\t41 89 40 04          \tmov    %eax,0x4(%r8)\r\n      5d:\t75 71                \tjne    d0 <__pthread_rwlock_unlock+0xd0>\r\n      5f:\t41 8b 48 14          \tmov    0x14(%r8),%ecx\r\n      63:\t85 c9                \ttest   %ecx,%ecx\r\n      65:\t0f 85 8d 00 00 00    \tjne    f8 <__pthread_rwlock_unlock+0xf8>\r\n      6b:\t41 8b 50 10          \tmov    0x10(%r8),%edx\r\n      6f:\t85 d2                \ttest   %edx,%edx\r\n      71:\t74 5d                \tje     d0 <__pthread_rwlock_unlock+0xd0>\r\n      73:\t41 83 40 08 01       \taddl   $0x1,0x8(%r8)\r\n      78:\t41 8b 70 1c          \tmov    0x1c(%r8),%esi\r\n      7c:\tf0 41 ff 08          \tlock decl (%r8)\r\n      80:\t74 16                \tje     98 <__pthread_rwlock_unlock+0x98>\r\n      82:\t49 8d 38             \tlea    (%r8),%rdi\r\n      85:\t48 81 ec 80 00 00 00 \tsub    $0x80,%rsp\r\n      8c:\te8 00 00 00 00       \tcallq  91 <__pthread_rwlock_unlock+0x91>\r\n      91:\t48 81 c4 80 00 00 00 \tadd    $0x80,%rsp\r\n      98:\t41 8b 70 1c          \tmov    0x1c(%r8),%esi\r\n      9c:\t45 31 d2             \txor    %r10d,%r10d\r\n      9f:\tba ff ff ff 7f       \tmov    $0x7fffffff,%edx\r\n      a4:\t49 8d 78 08          \tlea    0x8(%r8),%rdi\r\n      a8:\tb8 ca 00 00 00       \tmov    $0xca,%eax\r\n      ad:\t40 80 f6 81          \txor    $0x81,%sil\r\n      b1:\t48 63 f6             \tmovslq %esi,%rsi\r\n      b4:\t0f 05                \tsyscall \r\n      b6:\te9 5a ff ff ff       \tjmpq   15 <__pthread_rwlock_unlock+0x15>\r\n      bb:\t0f 1f 44 00 00       \tnopl   0x0(%rax,%rax,1)\r\n      c0:\t41 8b 40 04          \tmov    0x4(%r8),%eax\r\n      c4:\t41 c7 40 18 00 00 00 \tmovl   $0x0,0x18(%r8)\r\n      cb:\t00 \r\n      cc:\t85 c0                \ttest   %eax,%eax\r\n      ce:\t74 8f                \tje     5f <__pthread_rwlock_unlock+0x5f>\r\n      d0:\t41 8b 70 1c          \tmov    0x1c(%r8),%esi\r\n      d4:\tf0 41 ff 08          \tlock decl (%r8)\r\n      d8:\t74 16                \tje     f0 <__pthread_rwlock_unlock+0xf0>\r\n      da:\t49 8d 38             \tlea    (%r8),%rdi\r\n      dd:\t48 81 ec 80 00 00 00 \tsub    $0x80,%rsp\r\n      e4:\te8 00 00 00 00       \tcallq  e9 <__pthread_rwlock_unlock+0xe9>\r\n      e9:\t48 81 c4 80 00 00 00 \tadd    $0x80,%rsp\r\n      f0:\t31 c0                \txor    %eax,%eax\r\n      f2:\tc3                   \tretq   \r\n      f3:\t0f 1f 44 00 00       \tnopl   0x0(%rax,%rax,1)\r\n      f8:\t41 83 40 0c 01       \taddl   $0x1,0xc(%r8)\r\n      fd:\t41 8b 70 1c          \tmov    0x1c(%r8),%esi\r\n     101:\tf0 41 ff 08          \tlock decl (%r8)\r\n     105:\t74 16                \tje     11d <__pthread_rwlock_unlock+0x11d>\r\n     107:\t49 8d 38             \tlea    (%r8),%rdi\r\n     10a:\t48 81 ec 80 00 00 00 \tsub    $0x80,%rsp\r\n     111:\te8 00 00 00 00       \tcallq  116 <__pthread_rwlock_unlock+0x116>\r\n     116:\t48 81 c4 80 00 00 00 \tadd    $0x80,%rsp\r\n     11d:\t41 8b 70 1c          \tmov    0x1c(%r8),%esi\r\n     121:\t45 31 d2             \txor    %r10d,%r10d\r\n     124:\tba 01 00 00 00       \tmov    $0x1,%edx\r\n     129:\t49 8d 78 0c          \tlea    0xc(%r8),%rdi\r\n     12d:\tb8 ca 00 00 00       \tmov    $0xca,%eax\r\n     132:\t40 80 f6 81          \txor    $0x81,%sil\r\n     136:\t48 63 f6             \tmovslq %esi,%rsi\r\n     139:\t0f 05                \tsyscall \r\n     13b:\t31 c0                \txor    %eax,%eax\r\n     13d:\tc3                   \tretq   \r\n\r\n\r\n\r\n    elision-unlock.o:     file format elf64-x86-64\r\n    \r\n    \r\n    Disassembly of section .text:\r\n    \r\n    0000000000000000 <__lll_unlock_elision>:\r\n       0:   8b 07                   mov    (%rdi),%eax\r\n       2:   48 89 fa                mov    %rdi,%rdx\r\n       5:   85 c0                   test   %eax,%eax\r\n       7:   74 27                   je     30 <__lll_unlock_elision+0x30>\r\n       9:   f0 ff 0a                lock decl (%rdx)\r\n       c:   74 16                   je     24 <__lll_unlock_elision+0x24>\r\n       e:   48 8d 3a                lea    (%rdx),%rdi\r\n      11:   48 81 ec 80 00 00 00    sub    $0x80,%rsp\r\n      18:   e8 00 00 00 00          callq  1d <__lll_unlock_elision+0x1d>\r\n      1d:   48 81 c4 80 00 00 00    add    $0x80,%rsp\r\n      24:   31 c0                   xor    %eax,%eax\r\n      26:   c3                      retq\r\n      27:   66 0f 1f 84 00 00 00    nopw   0x0(%rax,%rax,1)\r\n      2e:   00 00\r\n      30:   0f 01 d5                xend\r\n      33:   31 c0                   xor    %eax,%eax\r\n      35:   c3                      retq\r\n"}}