{"push_id":607345295,"size":10,"distinct_size":10,"ref":"refs/heads/master","head":"4fe888702d9474320d6af203b70feb71fba80bcd","before":"f30aafe4e039aa913efa773fbf4d90b18cb25306","commits":[{"sha":"bdc47b205ac3c9624f3e82d21ff88e9a5b383030","author":{"email":"b70482a9c35b236639019cd8b2ecb03a9ee7db09@m-labs.hk","name":"Sebastien Bourdeauducq"},"message":"Revert \"fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)\"\n\nThis breaks simulations, and we will try to use the \"reg name = value\" syntax instead.\n\nThis reverts commit e946f6e4538277308e374cd1f0b1b9a31f66dc5a.","distinct":true,"url":"https://api.github.com/repos/jordens/migen/commits/bdc47b205ac3c9624f3e82d21ff88e9a5b383030"},{"sha":"2fc2f8a6c076658c024bfa785c5bbe30597b582b","author":{"email":"0f54f30f4ab9c86383b9179288475fb6cf4699a8@enjoy-digital.fr","name":"Florent Kermarrec"},"message":"migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)","distinct":true,"url":"https://api.github.com/repos/jordens/migen/commits/2fc2f8a6c076658c024bfa785c5bbe30597b582b"},{"sha":"ea9c1b8e69a672b2bcdc8243a49ca7854f6c95b0","author":{"email":"0f54f30f4ab9c86383b9179288475fb6cf4699a8@enjoy-digital.fr","name":"Florent Kermarrec"},"message":"fhdl/verilog: revert \"fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code\"\n\nThis probably breaks simulation with Icarus Verilog (and others simulators?)","distinct":true,"url":"https://api.github.com/repos/jordens/migen/commits/ea9c1b8e69a672b2bcdc8243a49ca7854f6c95b0"},{"sha":"c0fb0ef6002849f08c664b955cea8c557c7497e4","author":{"email":"0f54f30f4ab9c86383b9179288475fb6cf4699a8@enjoy-digital.fr","name":"Florent Kermarrec"},"message":"fhdl/verilog: change the way we initialize reg: reg name = init_value;\nThis allows simplifications (init in _printsync and _printinit no longer needed)","distinct":true,"url":"https://api.github.com/repos/jordens/migen/commits/c0fb0ef6002849f08c664b955cea8c557c7497e4"},{"sha":"5a9afee234210d501a9a3960ceb1ef9b26aa270f","author":{"email":"0f54f30f4ab9c86383b9179288475fb6cf4699a8@enjoy-digital.fr","name":"Florent Kermarrec"},"message":"fhdl/specials/memory: use $readmemh to initialize memories","distinct":true,"url":"https://api.github.com/repos/jordens/migen/commits/5a9afee234210d501a9a3960ceb1ef9b26aa270f"},{"sha":"3aee58f484a7b659b0d002f0e554a8d8bb87afbe","author":{"email":"0f54f30f4ab9c86383b9179288475fb6cf4699a8@enjoy-digital.fr","name":"Florent Kermarrec"},"message":"mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented)","distinct":true,"url":"https://api.github.com/repos/jordens/migen/commits/3aee58f484a7b659b0d002f0e554a8d8bb87afbe"},{"sha":"7fa1cd72a8d354409087dc8b001a5eeb7a4385d2","author":{"email":"b70482a9c35b236639019cd8b2ecb03a9ee7db09@m-labs.hk","name":"Sebastien Bourdeauducq"},"message":"fhdl/verilog: fix dummy signal initial event","distinct":true,"url":"https://api.github.com/repos/jordens/migen/commits/7fa1cd72a8d354409087dc8b001a5eeb7a4385d2"},{"sha":"860b72c8b6a47e8bb03d059a5a6cf28f172f928e","author":{"email":"97ea597f6300135b40201b7e9245123fae601762@gmail.com","name":"Robert Jordens"},"message":"pipistrello: rename sdram->ddram","distinct":true,"url":"https://api.github.com/repos/jordens/migen/commits/860b72c8b6a47e8bb03d059a5a6cf28f172f928e"},{"sha":"47ea4513158159acf350d8cec9dc7eb949139d44","author":{"email":"97ea597f6300135b40201b7e9245123fae601762@gmail.com","name":"Robert Jordens"},"message":"pipistrello: compress and load bitstream at 6MHz","distinct":true,"url":"https://api.github.com/repos/jordens/migen/commits/47ea4513158159acf350d8cec9dc7eb949139d44"},{"sha":"4fe888702d9474320d6af203b70feb71fba80bcd","author":{"email":"97ea597f6300135b40201b7e9245123fae601762@gmail.com","name":"Robert Jordens"},"message":"pipistrello: switch is a button","distinct":true,"url":"https://api.github.com/repos/jordens/migen/commits/4fe888702d9474320d6af203b70feb71fba80bcd"}]}