{"push_id":829413237,"size":29,"distinct_size":29,"ref":"refs/heads/wip/rib/oa-next","head":"d2103c43e883fc1b68cec662a91967765974949d","before":"ec6d22e0b0a11b77b4619e9178ed403fe8956abd","commits":[{"sha":"90a210e20dd4a359564c57ca2cd10548adaf3e2c","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: Add i915 perf infrastructure\n\nThis adds a DRM_IOCTL_I915_PERF_OPEN ioctl comparable to perf_event_open\nthat opens a file descriptor for an event source.\n\nBased on our initial experience aiming to use the core perf\ninfrastructure, this interface is inspired by perf, but focused on\nexposing metrics about work running on Gen graphics instead a CPU.\n\nOne notable difference is that it doesn't support mmaping a circular\nbuffer of samples into userspace. The currently planned use cases\nrequire an internal buffering that forces at least one copy of data\nwhich can be neatly hidden in a read() based interface.\n\nNo specific event types are supported yet so perf_event_open can currently\nonly get as far as returning EINVAL for an unknown event type.\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/90a210e20dd4a359564c57ca2cd10548adaf3e2c"},{"sha":"677d1f5be51b4075de6dad9c3c6b6c9757d7ff8a","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: rename OACONTROL GEN7_OACONTROL\n\nOACONTROL changes quite a bit for gen8, with some bits split out into a\nper-context OACTXCONTROL register\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/677d1f5be51b4075de6dad9c3c6b6c9757d7ff8a"},{"sha":"3c5b3646608b97572a29f89b320e9cd7db042dcd","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: Add static '3D' Haswell OA unit config\n\nAdds a static OA unit, MUX + B Counter configuration for basic '3D'\nmetrics on Haswell. This is autogenerated from an internal XML\ndescription of metric sets.\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/3c5b3646608b97572a29f89b320e9cd7db042dcd"},{"sha":"6090cb74a78aee7f1f4f56552fe02066d4432cf4","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: Add i915 perf event for Haswell OA unit\n\nGen graphics hardware can be set up to periodically write snapshots of\nperformance counters into a circular buffer via its Observation\nArchitecture and this patch exposes that capability to userspace via the\ni915 perf interface.\n\nCc: Chris Wilson <chris@chris-wilson.co.uk>\nSigned-off-by: Robert Bragg <robert@sixbynine.org>\nSigned-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/6090cb74a78aee7f1f4f56552fe02066d4432cf4"},{"sha":"2702ef35254e9ba009776403ceeb66bdd5703941","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: Add dev.i915.perf_event_paranoid sysctl option\n\nConsistent with the kernel.perf_event_paranoid sysctl option that can\nallow non-root users to access system wide cpu metrics, this can\noptionally allow non-root users to access system wide OA counter metrics\nfrom Gen graphics hardware.\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/2702ef35254e9ba009776403ceeb66bdd5703941"},{"sha":"50a2e5e7a2726f51ec5aa30eedcd0b2ee477fd91","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: add oa_event_min_timer_exponent sysctl\n\nThe minimal sampling period is now configurable via a\ndev.i915.oa_event_min_timer_exponent sysctl parameter.\n\nFollowing the precedent set by perf, the default is the minimum that\nwon't (on its own) exceed the default kernel.perf_event_max_sample_rate\ndefault of 100000 samples/s.\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/50a2e5e7a2726f51ec5aa30eedcd0b2ee477fd91"},{"sha":"ce5738b2ed82f846d08d329dc16c17bca444b28f","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: Add more Haswell OA metric sets\n\nThis adds 'compute', 'compute extended', 'memory reads', 'memory writes'\nand 'sampler balance' metric sets for Haswell.\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/ce5738b2ed82f846d08d329dc16c17bca444b28f"},{"sha":"6aba6a07390b7fd162d85f7eb12cd238becf897e","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: Add runtime eu/slice fuse checks for Broadwell\n\nUserspace will need information about the EU, slice and sub slice\nconfiguration to be able to normalize some OA metrics. Some of this can\nbe determined based on the device id, but we will also need to expose\nfurther information such as the slice and subslice mask which can't be\nderived from the device id. Its convenient for userspace if we can\nreport this information consistently for Gen 8+\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/6aba6a07390b7fd162d85f7eb12cd238becf897e"},{"sha":"ba62f1eed26b7ca43f87f54134e45210d0f1e382","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: start tracking device_info slice_mask\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/ba62f1eed26b7ca43f87f54134e45210d0f1e382"},{"sha":"a691e8a527ea92b159bbe340c9f6c48b4a3c8ce5","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: broadwell_sseu_info_init: init info->slice_mask\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/a691e8a527ea92b159bbe340c9f6c48b4a3c8ce5"},{"sha":"e6f9676832e755d0bef99bb3564dd7a065c1bab1","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: cherryview_sseu_info_init: init info->slice_mask\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/e6f9676832e755d0bef99bb3564dd7a065c1bab1"},{"sha":"7bdc41b9ad45b6bf2c05823cb54273d98959f3bd","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: gen9_sseu_info_init: init info->slice_mask\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/7bdc41b9ad45b6bf2c05823cb54273d98959f3bd"},{"sha":"64949d2edeeca91d485e438db2e7a8a41130f379","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: expose _SLICE_MASK GETPARM\n\nEnables userspace to determine the number of slices enabled and also\nknow what specific slices are enabled. This information is required, for\nexample, to be able to analyse some OA counter reports where the counter\nconfiguration depends on the HW slice configuration.\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/64949d2edeeca91d485e438db2e7a8a41130f379"},{"sha":"155a5d19b835adccaf2f5edc3f06e7719de9edf7","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: start tracking device_info subslice_mask\n\nCc: Zhenyu Wang <zhenyuw@linux.intel.com>\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/155a5d19b835adccaf2f5edc3f06e7719de9edf7"},{"sha":"0a030982eadc19235c42ef186150bdde520f0b7b","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: broadwell_sseu_info_init: init info->subslice_mask\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/0a030982eadc19235c42ef186150bdde520f0b7b"},{"sha":"3ccb8979f8b5035b6bc27a85e52b46e23f0418a5","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: cherryview_sseu_info_init: init info->subslice_mask\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/3ccb8979f8b5035b6bc27a85e52b46e23f0418a5"},{"sha":"e19e31bba59d8c424e8052e3004a802206f3a716","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: gen9_sseu_info_init: init info->subslice_mask\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/e19e31bba59d8c424e8052e3004a802206f3a716"},{"sha":"ebdc4792340e2cc18094981f05561225875fc339","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: expose _SUBSLICE_MASK GETPARM\n\nAssuming a uniform mask across all slices, this enables userspace to\ndetermine the specific sub slices enabled. This information is required,\nfor example, to be able to analyse some OA counter reports where the\ncounter configuration depends on the HW sub slice configuration.\n\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/ebdc4792340e2cc18094981f05561225875fc339"},{"sha":"6b80a565a19dd95dc2f7a3b58f4f9f658b9bdcbb","author":{"email":"f8c1e02e2aced2a829e1c894f7418daa2b0d2f0e@intel.com","name":"Sourab Gupta"},"message":"drm/i915: Introduce global id for contexts\n\nThe current context user handles are specific to drm file instance.\nThere are some usecases, which may require a global id for the contexts.\nFor e.g. a system level GPU profiler tool may lean upon the global context\nids to associate the performance snapshots with individual contexts.\n\nThis global id may also be used further in order to provide a unique\ncontext id to hw.\n\nIn this patch, the global ids are allocated from a separate cyclic idr and\ncan be further utilized for any usecase described above.\n\nv2: According to Chris' suggestion, implemented a separate idr for holding\nglobal ids for contexts, as opposed to overloading the file specific\nctx->user_handle for this purpose. This global id can also further be used\nwherever hw has to be programmed with ctx unique id, though this patch just\nintroduces the hw global id as such.\n\nSigned-off-by: Sourab Gupta <sourab.gupta@intel.com>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/6b80a565a19dd95dc2f7a3b58f4f9f658b9bdcbb"},{"sha":"025dd739920d535a88f1ab2a8faeb6c2c5032517","author":{"email":"12e9293ec6b30c7fa8a0926af42807e929c1684f@sixbynine.org","name":"Robert Bragg"},"message":"drm/i915: Constrain intel_context::global_id to 20 bits\n\nThis will allow the ID to be given to the HW as the unique context\nidentifier that's written, for example, to the context status buffer\non preemption and included in reports written by the OA unit.\n\nCc: Sourab Gupta <sourab.gupta@intel.com>\nSigned-off-by: Robert Bragg <robert@sixbynine.org>","distinct":true,"url":"https://api.github.com/repos/zhenyw/linux/commits/025dd739920d535a88f1ab2a8faeb6c2c5032517"}]}