{"push_id":575776741,"size":577,"distinct_size":13,"ref":"refs/heads/spapr-hotplug-core","head":"b83b64b65aad5a5f943ce80ee47dc4ab2afa2e18","before":"dd01148241181a085fb018272ec0fcef14d34445","commits":[{"sha":"800675f11742b6080e40d17b8d5f35d3a5fc5724","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Correct the handling of register #72 on writes\n\nFix an off-by-one error in `mips_cpu_gdb_write_register' for register\nmatching how `mips_cpu_gdb_read_register' handles it.  This register\nslot is a fake anyway, there's nothing in hardware that corresponds to\nit.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/800675f11742b6080e40d17b8d5f35d3a5fc5724"},{"sha":"c7d4d98ae7057467f48c02a11ad9120021976089","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Make CP1.FIR read-only here too\n\nCP1.FIR is read-only in hardware so gdbstub must respect it.  We already\nrespect it for CTC1 instructions, so do it here too.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/c7d4d98ae7057467f48c02a11ad9120021976089"},{"sha":"36b86e0dc2be93fc538fe7e11e0fda1a198f0135","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Add 5KEc and 5KEf MIPS64r2 processors\n\nAdd the 5KEc and 5KEf processors from MIPS Technologies that are the\noriginal implementation of the MIPS64r2 ISA.\n\nSilicon for these processors has never been taped out and no soft cores\nwere released even.  They do exist though, a CP0.PRId value has been\nassigned and experimental RTLs produced at the time the MIPS64r2 ISA has\nbeen finalized.  The settings introduced here faithfully reproduce that\nhardware.\n\nAs far the implementation goes these processors are the same as the 5Kc\nand the 5Kf CPUs respectively, except implementing the MIPS64r2 rather\nthan the original MIPS64 instruction set.  There must have been some\nupdates to the CP0 architecture as mandated by the ISA, such as the\naddition of the EBase register, although I am not sure about the exact\ndetails, no documentation has ever been produced for these processors.\nThe remaining parts of the microarchitecture, in particular the\npipeline, stayed unchanged.  Or to put it another way, the difference\nbetween a 5K and a 5KE CPU corresponds to one between a 4K and a 4KE\nCPU, except for the 64-bit rather than 32-bit ISA.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/36b86e0dc2be93fc538fe7e11e0fda1a198f0135"},{"sha":"8280b12c0e4b515d707509dde4ddde05d9bda4ef","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Make CP0.Config4 and CP0.Config5 registers signed\n\nMake the data type used for the CP0.Config4 and CP0.Config5 registers\nand their mask signed, for consistency with the remaining 32-bit CP0\nregisters, like CP0.Config0, etc.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/8280b12c0e4b515d707509dde4ddde05d9bda4ef"},{"sha":"11f5ea105c06bec72e9bc9a700fa65d60afb5ec3","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processors\n\nAdd the M14K and M14Kc processors from MIPS Technologies that are the\noriginal implementation of the microMIPS ISA.  They are dual instruction\nset processors, implementing both the microMIPS and the standard MIPSr32\nISA.\n\nThese processors correspond to the M4K and 4KEc CPUs respectively,\nexcept with support for the microMIPS instruction set added, support for\nthe MCU ASE added and two extra interrupt lines, making a total of 8\nhardware interrupts plus 2 software interrupts.  The remaining parts of\nthe microarchitecture, in particular the pipeline, stayed unchanged.\n\nThe presence of the microMIPS ASE is is reflected in the configuration\nadded.  We currently have no support for the MCU ASE, including in\nparticular the ACLR, ASET and IRET instructions in either encoding, and\nwe have no support for the extra interrupt lines, including bits in\nCP0.Status and CP0.Cause registers, so these features are not marked,\nmaking our support diverge from real hardware.\n\nSigned-off-by: Sandra Loosemore <sandra@codesourcery.com>\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/11f5ea105c06bec72e9bc9a700fa65d60afb5ec3"},{"sha":"4386f08767240080334539ac0b07a8bfe30bffe9","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Enable vectored interrupt support for the 74Kf CPU\n\nEnable vectored interrupt support for the 74Kf CPU, reflecting hardware.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/4386f08767240080334539ac0b07a8bfe30bffe9"},{"sha":"d75de74967f631a7d0b538d4b88f96f9c426bfe2","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Fix formatting in `decode_extended_mips16_opc'\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/d75de74967f631a7d0b538d4b88f96f9c426bfe2"},{"sha":"6225a4a0e39cb24e7b9e1d4d2c1a3e6eaee18e85","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Fix formatting in `mips_defs'\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/6225a4a0e39cb24e7b9e1d4d2c1a3e6eaee18e85"},{"sha":"d2bfa6e6222baa0218bd0658499d38bac56ac34c","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Fix formatting in `decode_opc'\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/d2bfa6e6222baa0218bd0658499d38bac56ac34c"},{"sha":"2b09f94cdbf5c54e2278d7f3aed2eceff3494790","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpers\n\nMove the call to `update_fcr31' in `helper_float_cvtw_s' after the\nexception flag check, for consistency with the remaining helpers that do\nit last too.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/2b09f94cdbf5c54e2278d7f3aed2eceff3494790"},{"sha":"51fdea945ae7adae8d7e4a1624e35bb7f714b58f","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Remove unused `FLOAT_OP' macro\n\nRemove the `FLOAT_OP' macro, unused since commit\nb6d96beda3a6cbf20a2d04a609eff78adebd8859 [Use temporary registers for\nthe MIPS FPU emulation.].\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/51fdea945ae7adae8d7e4a1624e35bb7f714b58f"},{"sha":"8fc605b8aa257feb3e69d44794a765bd492b573b","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Restore the order of helpers\n\nRestore the order of helpers that used to be: unary operations (generic,\nthen MIPS-specific), binary operations (generic, then MIPS-specific),\ncompare operations.  At one point FMA operations were inserted at a\nrandom place in the file, disregarding the preexisting order, and later\non even more operations sprinkled across the file.  Revert the mess by\nmoving FMA operations to a new ternary class inserted after the binary\nclass and move the misplaced unary and binary operations to where they\nbelong.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/8fc605b8aa257feb3e69d44794a765bd492b573b"},{"sha":"c3577479815f5bcf9d38993967bca2115af245d8","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Correct MIPS16/microMIPS branch size calculation\n\nCorrect MIPS16/microMIPS branch size calculation in PC adjustment\nneeded:\n\n- to set the value of CP0.ErrorEPC at the entry to the reset exception,\n\n- for the purpose of branch reexecution in the context of device I/O.\n\nFollow the approach taken in `exception_resume_pc' for ordinary, Debug\nand NMI exceptions.\n\nMIPS16 and microMIPS branches can be 2 or 4 bytes in size and that has\nto be reflected in calculation.  Original MIPS ISA branches, which is\nwhere this code originates from, are always 4 bytes long, just as all\noriginal MIPS ISA instructions.\n\nSigned-off-by: Nathan Froyd <froydnj@codesourcery.com>\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/c3577479815f5bcf9d38993967bca2115af245d8"},{"sha":"f88f79ec9df06d26d84e1d2e0c02d2634b4d8583","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Correct the handling of writes to CP0.Status for MIPSr6\n\nCorrect these issues with the handling of CP0.Status for MIPSr6:\n\n* only ignore the bit pattern of 0b11 on writes to CP0.Status.KSU, that\n  is for processors that do implement Supervisor Mode, let the bit\n  pattern be written to CP0.Status.UM:R0 freely (of course the value\n  written to read-only CP0.Status.R0 will be discarded anyway); this is\n  in accordance to the relevant architecture specification[1],\n\n* check the newly written pattern rather than the current contents of\n  CP0.Status for the KSU bits being 0b11,\n\n* use meaningful macro names to refer to CP0.Status bits rather than\n  magic numbers.\n\nReferences:\n\n[1] \"MIPS Architecture For Programmers, Volume III: MIPS64 / microMIPS64\n    Privileged Resource Architecture\", MIPS Technologies, Inc., Document\n    Number: MD00091, Revision 6.00, March 31, 2014, Table 9.45 \"Status\n    Register Field Descriptions\", pp. 210-211.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/f88f79ec9df06d26d84e1d2e0c02d2634b4d8583"},{"sha":"81a423e6c6d3ccaa79de4e58024369c660c1eeb4","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Correct the writes to Status and Cause registers via gdbstub\n\nMake writes to CP0.Status and CP0.Cause have the same effect as\nexecuting corresponding MTC0 instructions would in Kernel Mode.  Also\nignore writes in the user emulation mode.\n\nCurrently for requests from the GDB stub we write all the bits across\nboth registers, ignoring any read-only locations, and do not synchronise\nthe environment to evaluate side effects.  We also write these registers\nin the user emulation mode even though a real kernel presents them as\nread only.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/81a423e6c6d3ccaa79de4e58024369c660c1eeb4"},{"sha":"7215d7e7aea85699bf516c3e8d84f6a22584da35","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP\n\nFix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by\nusing register addition operations.\n\nThis copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R\nand I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands\nto tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying\n`rs' to `rd' verbatim.  This is not the case with OPC_ADDIU where a\nsign-extension from bit #31 is made, unless in the uninteresting case of\n`rs' being 0, losing the upper 32 bits of the value copied for any\nproper 64-bit values.\n\nThis also serves as an optimization as one op is produced in generated\ncode rather than two (again, unless `rs' is 0, where it doesn't change\nanything).\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/7215d7e7aea85699bf516c3e8d84f6a22584da35"},{"sha":"27e1fb13f21e132011673f0a39e17bcc97583633","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Output CP0.Config2-5 in the register dump\n\nInclude CP0.Config2 through CP0.Config5 registers in the register dump\nproduced with the `info registers' monitor command.  Align vertically\nwith the registers already output.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/27e1fb13f21e132011673f0a39e17bcc97583633"},{"sha":"90f12d735d66ac1196d9a2bced039a432eefc03d","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Fix CP0.Config3.ISAOnExc write accesses\n\nFix CP0.Config3.ISAOnExc write accesses on microMIPS processors.  This\nbit is mandatory for any processor that implements the microMIPS\ninstruction set.  This bit is r/w for processors that implement both the\nstandard MIPS and the microMIPS instruction set.  This bit is r/o and\nhardwired to 1 if only the microMIPS instruction set is implemented.\n\nThere is no other bit ever writable in CP0.Config3 so defining a\ncorresponding `CP0_Config3_rw_bitmask' member in `CPUMIPSState' is I\nthink an overkill.  Therefore make the ability to write the bit rely on\nthe presence of ASE_MICROMIPS set in the instruction flags.\n\nThe read-only case of the microMIPS instruction set being implemented\nonly can be added when we add support for such a configuration.  We do\nnot currently have such support, we have no instruction flag that would\ncontrol the presence of the standard MIPS instruction set nor any\nassociated code in instruction decoding.\n\nThis change is needed to boot a microMIPS Linux kernel successfully,\notherwise it hangs early on as interrupts are enabled and then the\nexception handler invoked loops as its first instruction is interpreted\nin the wrong execution mode and triggers another exception right away.\nAnd then over and over again.\n\nWe already check the current setting of the CP0.Config3.ISAOnExc in\n`set_hflags_for_handler' to set the ISA bit correctly on the exception\nhandler entry so it is the ability to set it that is missing only.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/90f12d735d66ac1196d9a2bced039a432eefc03d"},{"sha":"d9224450208e0de62323b64ace91f98bc31d6e2c","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Tighten ISA level checks\n\nTighten ISA level checks down to MIPS II that many of our instructions\nare missing.  Also make sure any 64-bit instruction enables are only\napplied to 64-bit processors, that is ones that implement at least the\nMIPS III ISA.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/d9224450208e0de62323b64ace91f98bc31d6e2c"},{"sha":"c48245f0c62405f27266fcf08722d8c290520418","author":{"email":"78f3a3d9d6e4d907a7d12e475d0a751d6b7e256b@codesourcery.com","name":"Maciej W. Rozycki"},"message":"target-mips: Correct 32-bit address space wrapping\n\nMake sure the address space is unconditionally wrapped on 32-bit\nprocessors, that is ones that do not implement at least the MIPS III\nISA.\n\nAlso make MIPS16 SAVE and RESTORE instructions use address calculation\nrather than plain arithmetic operations for stack pointer manipulation\nso that their semantics for stack accesses follows the architecture\nspecification.  That in particular applies to user software run on\n64-bit processors with the CP0.Status.UX bit clear where the address\nspace is wrapped to 32 bits.\n\nSigned-off-by: Maciej W. Rozycki <macro@codesourcery.com>\nReviewed-by: Leon Alrae <leon.alrae@imgtec.com>\nSigned-off-by: Leon Alrae <leon.alrae@imgtec.com>","distinct":false,"url":"https://api.github.com/repos/mdroth/qemu/commits/c48245f0c62405f27266fcf08722d8c290520418"}]}