{"push_id":747519349,"size":25,"distinct_size":25,"ref":"refs/heads/master","head":"e22b1a54942d9003b10564325a34e3cf767556ce","before":"c109dd0079711cb86ece088e2da4f4d792fc4730","commits":[{"sha":"5b7252424684e424647ae67f92bd6ebdd2458923","author":{"email":"f2b849f8f37c7d84535e3214faa00200f886e301@freescale.com","name":"Zhuoyu Zhang"},"message":"armv7/ls1021a: Reserve secure code into RAM instead of OCRAM\n\nFor ls1021a, Reserve secure code in to memory in case OCRAM\nis needed by other usage.\n\nSigned-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>\nAcked-by: Alison Wang <alison.wang@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/5b7252424684e424647ae67f92bd6ebdd2458923"},{"sha":"e94a8fd36300b1df347f034e0cfa6704dad83b6d","author":{"email":"d625eca35bf73a7ead1e7970443030cd40d2da25@freescale.com","name":"Zhao Qiang"},"message":"drivers/qe: transform parameter to compatible type\n\nwhen using printf, the parameter type need to be compatible\ntype, so transform them to compatible type\n\nSigned-off-by: Zhao Qiang <B45475@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/e94a8fd36300b1df347f034e0cfa6704dad83b6d"},{"sha":"0e0224ee627a71191a4e704c367c09723b995993","author":{"email":"d625eca35bf73a7ead1e7970443030cd40d2da25@freescale.com","name":"Zhao Qiang"},"message":"driver/qe: use strncpy instead of strcpy\n\nstrncpy is safer than strcpy, use it to instead of strcpy.\n\nSigned-off-by: Zhao Qiang <B45475@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/0e0224ee627a71191a4e704c367c09723b995993"},{"sha":"562583deb3ff6cac0833c91c7cc0c24f0d7e0413","author":{"email":"99c1ae5fc899310a74d6eda7ef8769fcb7791452@freescale.com","name":"gaurav rana"},"message":"armv7/lS1021atwr: Enable bootscript for secure boot\n\nEnable bootscript support in secure boot for establishing\nchain of trust on LS1021atwr.\n\nSigned-off-by: Gaurav Rana <gaurav.rana@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/562583deb3ff6cac0833c91c7cc0c24f0d7e0413"},{"sha":"99e1bd4241262440dce8950ccadb9d8588b0479b","author":{"email":"f66c2687de8c45b04592c834d7fc1c4c93da77ea@freescale.com","name":"Tang Yuantian"},"message":"armv7/ls1021atwr: added deep sleep support in uboot\n\nSigned-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>\nAcked-by: Alison Wang <alison.wang@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/99e1bd4241262440dce8950ccadb9d8588b0479b"},{"sha":"933db81c0494f692bbd384db11f7bab43706c87c","author":{"email":"07d9f5a554d4415975845fb521b9fecbb531a839@freescale.com","name":"chenhui zhao"},"message":"armv7/ls1021atwr: program the regulator for deep sleep\n\nProgram the external regulator to switch off voltage in deep sleep.\n\nSigned-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>\nAcked-by: Alison Wang <alison.wang@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/933db81c0494f692bbd384db11f7bab43706c87c"},{"sha":"6f0586e692c91ac9dc33fd479f68c3d957bf61b3","author":{"email":"5960aaaba185a50e91c7ab03e3fa96b745a59480@freescale.com","name":"Wang Dongsheng"},"message":"armv7/ls102xa: Fix non-boot cpus cannot correctly fall in spin table\n\nBootrom will put cpus into WFE state when boot cpu release cpus, so\ntarget cpu cannot correctly go to spin state.\n\nAdd 'sev' to wakeup non-boot cpu that hold on bootrom space, let target\ncpu can fall into u-boot spin table.\n\nSigned-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/6f0586e692c91ac9dc33fd479f68c3d957bf61b3"},{"sha":"8f0c7cbb0dd45614f31982ce6d095e203d7e5cda","author":{"email":"d44da55a283b3f67fec472e76af7093c7c6afeb9@freescale.com","name":"Alison Wang"},"message":"armv7/ls1021a: allow OCRAM access permission as R/W in SPL\n\nOn LS1021A Rev2.0, OCRAM's security level needs to be changed to\nnon-secure access for SD boot. This patch will allow OCRAM\naccess permission as R/W in SPL.\n\nSigned-off-by: Alison Wang <alison.wang@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/8f0c7cbb0dd45614f31982ce6d095e203d7e5cda"},{"sha":"6a17365b658b1e5b1d33da0e77722d8a3d7da8d6","author":{"email":"d44da55a283b3f67fec472e76af7093c7c6afeb9@freescale.com","name":"Alison Wang"},"message":"armv7/ls1021a/etsec: Enable Tx Data and TxBD snooping\n\nTo improve eTSEC performance on LS1021A Rev2.0,\nsnooping of all transmit frames from memory and\nall transmit BD memory accesses in enabled.\n\nSigned-off-by: Alison Wang <alison.wang@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/6a17365b658b1e5b1d33da0e77722d8a3d7da8d6"},{"sha":"026a3f1b7ca487bbce632060b8ca9193bb9edf87","author":{"email":"9cd4fe7678e1630676677a8799e6ca36cabb4300@freescale.com","name":"Alex Porosanu"},"message":"drivers/crypto/fsl: disable RNG oscillator maximum frequency check\n\nThe rtfrqmax & rtfrqmin set the bounds of the expected frequency of the\noscillator, when SEC runs at its maximum frequency. For certain platforms\n(f.i. T2080), the oscillator is very fast and thus if the SEC runs at\na lower than normal frequency, the ring oscillator is incorrectly detected\nas being out of bounds.\n\nThis patch effectively disables the maximum frequency check, by setting a\nhigh enough maximum allowable frequency for the oscillator. The reasoning\nbehind this is that usually a broken oscillator will run too slow\n(i.e. not run at all) rather than run too fast.\n\nSigned-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>\nAcked-by: Ruchika Gupta<ruchika.gupta@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/026a3f1b7ca487bbce632060b8ca9193bb9edf87"},{"sha":"17649e1b94b450f1ab0de7fa14553f390285f291","author":{"email":"9cd4fe7678e1630676677a8799e6ca36cabb4300@freescale.com","name":"Alex Porosanu"},"message":"drivers/crypto/fsl: change starting entropy delay value\n\nThe entropy delay (the length in system clocks of each\nentropy sample) for the RNG4 block of CAAM is dependent\non the frequency of the SoC. By elaborate methods, it\nhas been determined that a good starting value for all\nplatforms integrating the CAAM IP is 3200. Using a\nhigher value has additional benefit of  speeding up\nthe process of instantiating the RNG, since the entropy\ndelay will be increased and instantiation of the RNG\nstate handles will be reattempted by the driver. If the\nstarting value is low, for certain platforms, this can\nlead to a quite lengthy process.\nThis patch changes the starting value of the length of\nthe entropy sample to 3200 system clocks.\nIn addition to this change, the attempted entropy delay\nvalues are now printed on the console upon initialization\nof the RNG block.\n\nSigned-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>\nAcked-by: Ruchika Gupta<ruchika.gupta@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/17649e1b94b450f1ab0de7fa14553f390285f291"},{"sha":"c4065517362ae9132ceaaec4103ed5ad6c9cfe92","author":{"email":"9cd4fe7678e1630676677a8799e6ca36cabb4300@freescale.com","name":"Alex Porosanu"},"message":"drivers/crypto/fsl: enable raw data instead of von Neumann data\n\nThe sampling of the oscillator can be done in multiple modes for\ngenerating the entropy value. By default, this is set to von\nNeumann. This patch changes the sampling to raw data, since it\nhas been discovered that the generated entropy has a better\n'quality'.\n\nSigned-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>\nAcked-by: Ruchika Gupta<ruchika.gupta@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/c4065517362ae9132ceaaec4103ed5ad6c9cfe92"},{"sha":"87457d118f77b6d4de4de83118360fb0eade491c","author":{"email":"2fbe35bf2a56078116f98b30b2b493844cc201e1@freescale.com","name":"Prabhakar Kushwaha"},"message":"drivers/fsl-mc: flib changes for mc 8.0.0\n\nMC firware version 8.0.0 contains new command flags. This patch\ncontains modifications in FLIB files to support the new command flags.\n\nSigned-off-by: Itai Katz <itai.katz@freescale.com>\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/87457d118f77b6d4de4de83118360fb0eade491c"},{"sha":"ed5b580b381307c522cb977dccd207a170ad9b13","author":{"email":"edc9fd01d7be6da9c99ad8f260a21609cbf862d0@freescale.com","name":"Minghuan Lian"},"message":"drivers/pci: Add function to find an extended capability\n\nPCIe extends device's configuration space to 4k and provides\nextended capability. The patch adds function to find them.\nThe code is ported from Linux PCIe driver.\n\nSigned-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>\nReviewed-by: Bin Meng <bmeng.cn@gmail.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/ed5b580b381307c522cb977dccd207a170ad9b13"},{"sha":"01cafcedbfbefef6c975d7bbe704994bf3357ebd","author":{"email":"edc9fd01d7be6da9c99ad8f260a21609cbf862d0@freescale.com","name":"Minghuan Lian"},"message":"drivers/pci/layerscape: Add EP mode support\n\nThe patch will initialize PCIe controller on EP mode\n1. Setup bar:\n   bar0 32bit 4K for specific configuration\n   bar1 32bit 8K for MSIX\n   bar2 64bit 4K for descriptor of memory\n   bar4 64bit 1M for DMA memory test\n2. Setup iATU:\n   iATU inbound 0-3 to map bar transaction to memory address\n   started at CONFIG_SYS_PCI_EP_MEMORY_BASE\n   iATU outbound 0 to map 4G memory space\n\nSigned-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/01cafcedbfbefef6c975d7bbe704994bf3357ebd"},{"sha":"e5d08b4d601d4060609b162f437327c823b00947","author":{"email":"6135224f23789828bd8d3b771a2745286516a2b5@freescale.com","name":"horia.geanta@freescale.com"},"message":"drivers/crypto/fsl: fix \"era\" property value on LE platforms\n\nUse fdt_setprop_u32() instead of fdt_setprop().\n\nFixes: 0181937fa371a (\"crypto/fsl: Add fixup for crypto node\")\nSigned-off-by: Horia Geantă <horia.geanta@freescale.com>\nReviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>\nAcked-by: Ruchika Gupta<ruchika.gupta@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/e5d08b4d601d4060609b162f437327c823b00947"},{"sha":"3ef2412de6680c751abd39047cadff7e052a0f51","author":{"email":"6135224f23789828bd8d3b771a2745286516a2b5@freescale.com","name":"horia.geanta@freescale.com"},"message":"drivers/crypto/fsl: fix snooping for write transactions\n\nHW coherency won't work properly for CAAM write transactions\nif AWCACHE is left to default (POR) value - 4'b0001.\nIt has to be programmed to 4'b0010.\n\nFor platforms that have HW coherency support:\n-PPC-based: the update has no effect; CAAM coherency already works\ndue to the IOMMU (PAMU) driver setting the correct memory coherency\nattributes\n-ARM-based: the update fixes cache coherency issues,\nsince IOMMU (SMMU) driver is not programmed to behave similar to PAMU\n\nFixes: b9eebfade974c (\"fsl_sec: Add hardware accelerated SHA256 and SHA1\")\nSigned-off-by: Horia Geantă <horia.geanta@freescale.com>\nReviewed-by: Aneesh Bansal <aneesh.bansal@freescale.com>\nReviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>\nAcked-by: Ruchika Gupta<ruchika.gupta@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/3ef2412de6680c751abd39047cadff7e052a0f51"},{"sha":"14d5547cf158c18bc340f01424e011b0802a6bb0","author":{"email":"6135224f23789828bd8d3b771a2745286516a2b5@freescale.com","name":"horia.geanta@freescale.com"},"message":"drivers/crypto/fsl: clean-up - use fdt_setprop_u32 helper\n\nSigned-off-by: Horia Geantă <horia.geanta@freescale.com>\nAcked-by: Ruchika Gupta<ruchika.gupta@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/14d5547cf158c18bc340f01424e011b0802a6bb0"},{"sha":"56848428a88f89420ae7acc04bb5805e70c430a3","author":{"email":"44c377796b04a476428a0fa0782ddb7fe1581969@freescale.com","name":"York Sun"},"message":"drivers/ddr/fsl: Adjust bstopre value\n\nBy default the bstopre value has been set to 0x100, used to be 1/4\nvalue of refint. Modern DDR has increased the refresh time. Adjust\nto 1/4 of refresh interval dynamically. Individual board can still\noverride this value in board ddr file, or to use auto-precharge.\n\nSigned-off-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/56848428a88f89420ae7acc04bb5805e70c430a3"},{"sha":"ca7fb12cc18e80d14cca9570aec1d544f5d8c169","author":{"email":"392e1861dfe3128e490601f594a36f1bc559fe6f@freescale.com","name":"Nikhil Badola"},"message":"armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A\n\nDefine CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by\nUSB XHCI stack for alignment\n\nSigned-off-by: Nikhil Badola <nikhil.badola@freescale.com>\nReviewed-by: York Sun <yorksun@freescale.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/ca7fb12cc18e80d14cca9570aec1d544f5d8c169"}]}