{"push_id":846948338,"size":3,"distinct_size":3,"ref":"refs/heads/lolivoli","head":"888b93a3f729949cbe052ae138f6031799dc1822","before":"093519b9111e11d73ba1afd9b1b00449b4da2217","commits":[{"sha":"1d8931d5d722b4968af0bc61fc146e377b1b14bb","author":{"email":"89f130be114f443a91682cc7170f0242871273d3@codeaurora.org","name":"Pushkar Joshi"},"message":"clk: qcom: clock-mmss-8992: Support multiple parents for byte/pixel clocks\n\nAdd additional parents for the pixel and byte clocks as these can now\nswitch between those. Also export the sources for the byte and pixel\nclocks so that clients can switch between the parents for the relevant\nRCGs.\n\nChange-Id: I4e1430778dae4a0b77ecc81836b23b6f8c841197\nSigned-off-by: Pushkar Joshi <pushkarj@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/cile381/H815_kernel/commits/1d8931d5d722b4968af0bc61fc146e377b1b14bb"},{"sha":"4ce2b5f02a769bd2a0ce2da8eb50edac6d8705b1","author":{"email":"89f130be114f443a91682cc7170f0242871273d3@codeaurora.org","name":"Pushkar Joshi"},"message":"clk: qcom: clock-mmss-8994: Support multiple parents for byte/pixel clocks\n\nAdd additional parents for the pixel and byte clocks as these can now\nswitch between those. Also export the sources for the byte and pixel\nclocks so that clients can switch between the parents for the relevant\nRCGs.\n\nChange-Id: If2c7fe4f12c6ad5a15f13acf71d6dc296b57b665\nSigned-off-by: Pushkar Joshi <pushkarj@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/cile381/H815_kernel/commits/4ce2b5f02a769bd2a0ce2da8eb50edac6d8705b1"},{"sha":"888b93a3f729949cbe052ae138f6031799dc1822","author":{"email":"577f74ec3f2c8a155237d5ad42a70103d17f8313@codeaurora.org","name":"Vikram Mulukutla"},"message":"clk: qcom: clock-pll: Panic if a variable rate PLL fails to lock\n\nOccasionally, variable rate PLLs may fail to achieve a lock, and the\noutput frequency may not match what software expects after configuring\nan L value for a certain frequency. If the PLL fails to lock, that is,\nthe lock detection bit does not go high even after waiting for the\nmandated amount of time, record additional PLL debug information in the\nkernel log and then panic.\n\nChange-Id: Ib913d7620ef9d1fc94a1c353e528f558c3117d81\nSigned-off-by: Vikram Mulukutla <markivx@codeaurora.org>\nSigned-off-by: Pushkar Joshi <pushkarj@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/cile381/H815_kernel/commits/888b93a3f729949cbe052ae138f6031799dc1822"}]}