{"action":"opened","issue":{"url":"https://api.github.com/repos/ujamjar/hardcaml-llvmsim/issues/2","labels_url":"https://api.github.com/repos/ujamjar/hardcaml-llvmsim/issues/2/labels{/name}","comments_url":"https://api.github.com/repos/ujamjar/hardcaml-llvmsim/issues/2/comments","events_url":"https://api.github.com/repos/ujamjar/hardcaml-llvmsim/issues/2/events","html_url":"https://github.com/ujamjar/hardcaml-llvmsim/issues/2","id":65054623,"number":2,"title":"Memory write scheduling","user":{"login":"andrewray","id":5944099,"avatar_url":"https://avatars.githubusercontent.com/u/5944099?v=3","gravatar_id":"","url":"https://api.github.com/users/andrewray","html_url":"https://github.com/andrewray","followers_url":"https://api.github.com/users/andrewray/followers","following_url":"https://api.github.com/users/andrewray/following{/other_user}","gists_url":"https://api.github.com/users/andrewray/gists{/gist_id}","starred_url":"https://api.github.com/users/andrewray/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/andrewray/subscriptions","organizations_url":"https://api.github.com/users/andrewray/orgs","repos_url":"https://api.github.com/users/andrewray/repos","events_url":"https://api.github.com/users/andrewray/events{/privacy}","received_events_url":"https://api.github.com/users/andrewray/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":0,"created_at":"2015-03-29T12:05:43Z","updated_at":"2015-03-29T12:05:43Z","closed_at":null,"body":"(unusual, but possible) structures with memory outputs driving a memory write/write enable/write address (at a specific address, with some bad luck regarding the chosen memory scheduling order) might be incorrect.  \r\n\r\nMore investigation needed."}}