{"push_id":616320120,"size":4,"distinct_size":4,"ref":"refs/heads/master","head":"c8100c1d938f3ac2a655c696be478a49533a2230","before":"150be32b730312692b4262cd5d26f682a7c26cad","commits":[{"sha":"76ee1953b3fe7ea6d6eeaead9fa1bda37281ba0c","author":{"email":"9a71e7c977055f3216e6ac993c790af4dbadc86f@gmail.com","name":"andrewray"},"message":"control exactly where load instructions are emitted.\n\nFor memories we need to load the address and data element at the address.\nBefore loads were pushed onto the front of the 1st basic block which\nreversed the address/data load and caused an assert.  We now split\neach funtion into 2 basic blocks (which should be collapsed) - one\nfor the loads, one for the operations.  As loads are generated they\nare pushed onto the end on the loading basic block (just before the\njump) so everything is in order.\n\n/rant on/ the irbuilder interface is *seriously* horrible.","distinct":true,"url":"https://api.github.com/repos/ujamjar/hardcaml-llvmsim/commits/76ee1953b3fe7ea6d6eeaead9fa1bda37281ba0c"},{"sha":"43c7421c7d6358a3ddab0acc9ca451a252b5a9bd","author":{"email":"9a71e7c977055f3216e6ac993c790af4dbadc86f@gmail.com","name":"andrewray"},"message":"rework globals module a bit\n\npreparing for some changes needed for memory implementation","distinct":true,"url":"https://api.github.com/repos/ujamjar/hardcaml-llvmsim/commits/43c7421c7d6358a3ddab0acc9ca451a252b5a9bd"},{"sha":"6c8f6449e846dad04a3e7bfd8357d055228d7ede","author":{"email":"9a71e7c977055f3216e6ac993c790af4dbadc86f@gmail.com","name":"andrewray"},"message":"memories almost working...\n\nmem->mem test is off by 1 cycle; need to add mem r/w address to map for cycle deps","distinct":true,"url":"https://api.github.com/repos/ujamjar/hardcaml-llvmsim/commits/6c8f6449e846dad04a3e7bfd8357d055228d7ede"},{"sha":"c8100c1d938f3ac2a655c696be478a49533a2230","author":{"email":"9a71e7c977055f3216e6ac993c790af4dbadc86f@gmail.com","name":"andrewray"},"message":"redo logic again.  memories seem to be working.\n\nwe're now much closer to the cyclesim implementation, and, thankfully\na *good* bit simpler.","distinct":true,"url":"https://api.github.com/repos/ujamjar/hardcaml-llvmsim/commits/c8100c1d938f3ac2a655c696be478a49533a2230"}]}