{"push_id":782238348,"size":65,"distinct_size":65,"ref":"refs/heads/master","head":"472d83c8aa4e43333faef1474ad10267bd617d43","before":"c9c94dbcc7cf17b794cc3d59e6d304c1c1c51866","commits":[{"sha":"ce181aea6cb5353181add7b5aca3c0b196a9b513","author":{"email":"822ec91a7ef82248fd36162ca8ac3283eba70848@linux.intel.com","name":"Neil Roberts"},"message":"mesa/pbo: Handle zero width, height or depth when validating access\n\nIt's legal to call glTexSubImage with zero values for the width,\nheight or depth. Previously this was breaking the PBO access\nvalidation because it tries to work out the last pixel accessed by\ngetting the pixel at height-1 and depth-1 which would end up with\nbogus values.\n\nThis was causing GL errors to be generated during the Piglit\ntexsubimage test, although the test was passing anyway.\n\nv2: Also check for width == 0. Don't validate the start pointer if any\n    of the dimensions are zero.\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/ce181aea6cb5353181add7b5aca3c0b196a9b513"},{"sha":"7d475bad66b99e171542bc9ea62abac56abfa6f2","author":{"email":"eac34e836c3bc120048c86fead6dd0257a872a9e@gmail.com","name":"Grazvydas Ignotas"},"message":"r600g: make all scissor states use single atom\n\nAs suggested by Marek Olšák, we can use single atom to track all scissor\nstates. This will allow to simplify dirty atom handling later.\n\nSigned-off-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/7d475bad66b99e171542bc9ea62abac56abfa6f2"},{"sha":"fbb423b43380d0e43d14056e96846da412693148","author":{"email":"eac34e836c3bc120048c86fead6dd0257a872a9e@gmail.com","name":"Grazvydas Ignotas"},"message":"r600g: apply disable workaround on all scissors\n\nDuring review of the \"r600g: make all scissor states use single atom\" patch\nMarek Olšák noticed that scissor disable workaround should be applied on\nall scissor states and not just first one, so let's do so.\n\nSigned-off-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/fbb423b43380d0e43d14056e96846da412693148"},{"sha":"4d9af438bc41ed20da1963a438249fee43213121","author":{"email":"eac34e836c3bc120048c86fead6dd0257a872a9e@gmail.com","name":"Grazvydas Ignotas"},"message":"r600g: make all viewport states use single atom\n\nSimilarly to scissor states, we can use single atom to track all viewport\nstates. This will allow to simplify dirty atom handling later.\n\nSigned-off-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/4d9af438bc41ed20da1963a438249fee43213121"},{"sha":"6ef4572937015c1e076afc12f19e8453d08babec","author":{"email":"eac34e836c3bc120048c86fead6dd0257a872a9e@gmail.com","name":"Grazvydas Ignotas"},"message":"r600g: start numbering atoms from 1\n\nThere doesn't seem any reason to start from 4.\nStart from 1 instead (0 is left reserved to catch uninitialized atoms).\n\nSigned-off-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/6ef4572937015c1e076afc12f19e8453d08babec"},{"sha":"ccbc7952a4c125741f412ebc0278e17b65cf6fd7","author":{"email":"eac34e836c3bc120048c86fead6dd0257a872a9e@gmail.com","name":"Grazvydas Ignotas"},"message":"r600g: simplify dirty atom tracking\n\nNow that R600_NUM_ATOMS is below 64, dirty atom tracking can be\nsimplified.\n\nSigned-off-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/ccbc7952a4c125741f412ebc0278e17b65cf6fd7"},{"sha":"722ce747436f5b9c79d1fa4a8c59eed2f9cb611b","author":{"email":"eac34e836c3bc120048c86fead6dd0257a872a9e@gmail.com","name":"Grazvydas Ignotas"},"message":"gallium/radeon: remove 'dirty' member from r600_atom\n\nIt's no longer used by both r600 and radeonsi now.\n\nSigned-off-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/722ce747436f5b9c79d1fa4a8c59eed2f9cb611b"},{"sha":"6c1e368cf38e02174a8c88218ae711ab0b27954f","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"u_upload_mgr: optimize u_upload_alloc\n\nThis is probably the most called util function. It does almost nothing,\nyet it can consume 10% of the CPU on the profile. This drops it down to 5%.\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/6c1e368cf38e02174a8c88218ae711ab0b27954f"},{"sha":"8c6ff05517137ab9d96015783fcf1bf9d8d1fa12","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"u_upload_mgr: remove the return value from u_upload_alloc\n\nThe return buffer or the returned pointer can be used instead.\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/8c6ff05517137ab9d96015783fcf1bf9d8d1fa12"},{"sha":"b4f7639955b6c74436db6dea9174a8c7ce37ec62","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"u_upload_mgr: remove the return value from u_upload_alloc_buffer\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/b4f7639955b6c74436db6dea9174a8c7ce37ec62"},{"sha":"0c5df863ba27d31993f3fdc85b26407f398514fa","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"u_upload_mgr: remove the return value from u_upload_buffer\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/0c5df863ba27d31993f3fdc85b26407f398514fa"},{"sha":"44dbaa1746833f2874786fc2067f8837f149261f","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"u_upload_mgr: remove the return value from u_upload_data\n\nReviewed-by: Brian Paul <brianp@vmware.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/44dbaa1746833f2874786fc2067f8837f149261f"},{"sha":"35d0f12797237cdd38e7fd2c39d3c19e875875ca","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"gallium/pb_bufmgr_cache: add a way to remove buffers from the cache explicitly\n\nThis must be done before exporting a buffer as dmabuf fds, because\nwe lose track of who is using it and can't trust the reference counter.\n\nCc: 11.0 <mesa-stable@lists.freedesktop.org>\nReviewed-by: Alex Deucher <alexander.deucher@amd.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/35d0f12797237cdd38e7fd2c39d3c19e875875ca"},{"sha":"54964c77510b060806615c842692c0f393e807e6","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"winsys/amdgpu: remove exported buffers from the cache\n\nCc: 11.0 <mesa-stable@lists.freedesktop.org>\nReviewed-by: Alex Deucher <alexander.deucher@amd.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/54964c77510b060806615c842692c0f393e807e6"},{"sha":"efea7c3a3f91219db6e2fa3588388b6be4ecfa40","author":{"email":"8c7344a1abdb103e79ecfd488098373070c3c70e@amd.com","name":"Marek Olšák"},"message":"winsys/radeon: remove exported buffers from the cache\n\nCc: 11.0 <mesa-stable@lists.freedesktop.org>\nReviewed-by: Alex Deucher <alexander.deucher@amd.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/efea7c3a3f91219db6e2fa3588388b6be4ecfa40"},{"sha":"70dbdca15fa173302481111cdfb86881dd13dc38","author":{"email":"3cb4e1df5ec4da2c7c4af7c52cec8cf340a55a10@vmware.com","name":"Brian Paul"},"message":"svga: update call to u_upload_alloc()\n\nu_upload_alloc() no longer returns a return value.\n\nTrivial.","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/70dbdca15fa173302481111cdfb86881dd13dc38"},{"sha":"b05619c627122a0e35a18f92e457d3aefa55f2f7","author":{"email":"cf148a1c890adeeb4308e9e093ed95f3d05c8318@intel.com","name":"Ben Widawsky"},"message":"i965/gen9: Annotate input coverage mask change\n\nAs far as I can tell, the behavior is preserved from the previous generations.\nBefore we set a single bit to tell the FS whether or not we'll be using an input\ncoverage mask. Now we have some options which are implementing various\nextensions. These bits are used for the various conservative rasterization\nmechanisms (for collision detection, binning, and whatever else).\n\nI believe that the behavior is preserved because the problem which conservative\nrasterization is attempting to fix would go away with the \"NORMAL\" mode (at the\ncost of performance, I believe).\n\nThis patch serves as documentation of the change by creating the enums, as well\nas giving some of the history with the links here so that the next person who\ncomes along and looks at it doesn't spend as long as I had to in order to\ndetermine if there is an issue or not.\n\nPreviously, this algorithm had been done in software, and this can still be used\nas long as we don't export an extension stating otherwise.\n\nReferences: https://www.opengl.org/registry/specs/NV/conservative_raster.txt\nReferences: https://http.developer.nvidia.com/GPUGems2/gpugems2_chapter42.html\nSigned-off-by: Ben Widawsky <ben@bwidawsk.net>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/b05619c627122a0e35a18f92e457d3aefa55f2f7"},{"sha":"5fa5a012b163bad80d01a65e2947510f15e1be6b","author":{"email":"f2295d84e358395675bc8031be58672073ae065e@redhat.com","name":"Dave Airlie"},"message":"r600: fix loop overrun in cayman_mul_double_instr\n\nCoverity warned about this. Ilia pointed it out.\n\nSigned-off-by: Dave Airlie <airlied@redhat.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/5fa5a012b163bad80d01a65e2947510f15e1be6b"},{"sha":"2ace64fd598816fd1be9877962734242fc27b87b","author":{"email":"bd2562f754ec92342f93f61c25d731e290a2ffa8@whitecape.org","name":"Kenneth Graunke"},"message":"i965: Fix copy propagation type changes.\n\ncommit 472ef9a02f2e5c5d0caa2809cb736a0f4f0d4693 introduced code to\nchange the types of SEL and MOV instructions for moves that simply\n\"copy bits around\".  It didn't account for type conversion moves,\nhowever.  So it would happily turn this:\n\n   mov(8) vgrf6:D, -vgrf5:D\n   mov(8) vgrf7:F, vgrf6:UD\n\ninto this:\n\n   mov(8) vgrf6:D, -vgrf5:D\n   mov(8) vgrf7:D, -vgrf5:D\n\nwhich erroneously drops the conversion to float.\n\nCc: \"11.0 10.6\" <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>\nReviewed-by: Matt Turner <mattst88@gmail.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/2ace64fd598816fd1be9877962734242fc27b87b"},{"sha":"0db323a62481a57269a46287a64fa743756e80f3","author":{"email":"cdcb67a5e49297de94340ca09f25994bd5e7f762@intel.com","name":"Tapani Pälli"},"message":"build: add HAVE_SHA1 define when using --with-sha1 option\n\nSigned-off-by: Tapani Pälli <tapani.palli@intel.com>\nAcked-by: Brian Paul <brianp@vmware.com>","distinct":true,"url":"https://api.github.com/repos/jvesely/mesa/commits/0db323a62481a57269a46287a64fa743756e80f3"}]}