{"push_id":840211650,"size":6,"distinct_size":6,"ref":"refs/heads/EZ-arc-upstream-reviewd-DO-NOT-COMMENT","head":"c63e2181c16139e7e8a68e7ffd7e667092b7110a","before":"0c1e5a8bdda5ae4dd8d65433e20b48bf038a37fa","commits":[{"sha":"c078c2c34a7635b839741738f1b2a2a9accbb276","author":{"email":"9eb5903f3e94f804514a44d30418315f7a8c2f7d@ezchip.com","name":"Tal Zilcer"},"message":"ARC: [plat-eznps] replace sync with proper cpu barrier\n\nIn SMT system like we have the generic \"sync\" is not working with\nHW threads. The replacement is \"schd.rw\" instruction that is served\nas cpu barrier for HW threads.\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/c078c2c34a7635b839741738f1b2a2a9accbb276"},{"sha":"dea69128a7b8bbc050b9f72c1aadbf7d1e198de9","author":{"email":"9eb5903f3e94f804514a44d30418315f7a8c2f7d@ezchip.com","name":"Tal Zilcer"},"message":"ARC: [plat-eznps] handle shared caches\n\nNPS share its caches among all its HW threads.\nWhen we use one chach contorl registers we need\nto dissallow HW scheduling until access to those\nregisters is done, this way we keep caches in\nconsist state.\nWe use couple instruction for enable/disable of\nHW scheduling that occures periodically.\nWe wrap those instruction both for assembly code\nas well as C code.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/dea69128a7b8bbc050b9f72c1aadbf7d1e198de9"},{"sha":"8ffc8b9aa5d91f7d6cd0b6a44dabdbf2bd366678","author":{"email":"9eb5903f3e94f804514a44d30418315f7a8c2f7d@ezchip.com","name":"Tal Zilcer"},"message":"ARC: [plat-eznps] adapt ASID assigning\n\nIn NPS all 16 HW threads of same core share TLB cache.\n\nTo avoid more than one HW thread to use same ASID we\nsplit ASID range between all HW threads.\nFor HW thread 0 ASIDs 0-15 are used, for HW thread 1 ASIDs\n16-31 are used and so on spliting all 256 possible ASIDs.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/8ffc8b9aa5d91f7d6cd0b6a44dabdbf2bd366678"},{"sha":"28a60f0460353f1e67da6d651ea4ae412f690310","author":{"email":"9eb5903f3e94f804514a44d30418315f7a8c2f7d@ezchip.com","name":"Tal Zilcer"},"message":"ARC: add __weak attribute to arc_local_timer_setup()\n\nMaking arc_local_timer_setup() weak will enable us later\ndefine platform specific implementation.\nAlso we move registers definitions from C file to header file\nSo platform implementation can reuse them.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/28a60f0460353f1e67da6d651ea4ae412f690310"},{"sha":"402b799e76055775fdd433fe1270acbea3b5e5c8","author":{"email":"9eb5903f3e94f804514a44d30418315f7a8c2f7d@ezchip.com","name":"Tal Zilcer"},"message":"ARC: [plat-eznps] dedicated driver for shared timer0\n\nNPS have one timer0 for all HW threads in single core.\nclock events can be registered to more than one thread by using\ndedicated register called TSI1 which is a bitmask.\nSo each set bit means that when timer0 expires the HW thread\ncorresponds to same bit will get timer interrupt.\n\nNew CONFIG_EZNPS_SHARED_TIMER option will enable this.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/402b799e76055775fdd433fe1270acbea3b5e5c8"},{"sha":"c63e2181c16139e7e8a68e7ffd7e667092b7110a","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: Add eznps platform to Kconfig and Makefile\n\nThis commit should be left last since only now eznps platform\nis in state which one can actually use.\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/c63e2181c16139e7e8a68e7ffd7e667092b7110a"}]}