{"push_id":750834199,"size":3,"distinct_size":0,"ref":"refs/heads/master","head":"c57de507e54768e285729799a24d026fc4b3f756","before":"c0698ae8f883cdd3af631bdc53ff0e7e3f27d884","commits":[{"sha":"cd20b8d90798ad0d2a632d135e86eb42ebe09909","author":{"email":"c376221f99e2c9ceacfa41dec806b26074cb7f05@atmel.com","name":"Wenyou Yang"},"message":"driver: at91_wdt: change the implementation to disable watchdog timer\n\nFrom SAMA5D4, the watchdog timer is upgrated with a new feature,\nwhich is describled as in the datasheet, \"WDT_MR can be written\nuntil a LOCKMR command is issued in WDT_CR\".\nThat is to say, as long as the bootstrap and u-boot don't issue\na LOCKMR command, WDT_MR can be written more than once,\nand the watchdog timer can be enable/disable without any constraints.\n\nIn current implementation, to disable the watchdog timer by only\nsetting the WDDIS bit(i.e. other bits are all set 0), this will\ncause the watchdog timer can't be enabled in the future.\nSo it should be, read the WDT_MR register first, then modify the WDDIS\nbit to disable the watchdog timer.\n\nSigned-off-by: Wenyou Yang <wenyou.yang@atmel.com>","distinct":false,"url":"https://api.github.com/repos/linux4sam/at91bootstrap/commits/cd20b8d90798ad0d2a632d135e86eb42ebe09909"},{"sha":"0de92b59f8ffcf32741b0da963db2dc4ddac40b6","author":{"email":"c376221f99e2c9ceacfa41dec806b26074cb7f05@atmel.com","name":"Wenyou Yang"},"message":"Makefile: update version v3.8 alpha4 release\n\nSigned-off-by: Wenyou Yang <wenyou.yang@atmel.com>","distinct":false,"url":"https://api.github.com/repos/linux4sam/at91bootstrap/commits/0de92b59f8ffcf32741b0da963db2dc4ddac40b6"},{"sha":"c57de507e54768e285729799a24d026fc4b3f756","author":{"email":"c376221f99e2c9ceacfa41dec806b26074cb7f05@atmel.com","name":"Wenyou Yang"},"message":"sama5d2: tmp fix DDR3 timing\n\nSigned-off-by: Wenyou Yang <wenyou.yang@atmel.com>","distinct":false,"url":"https://api.github.com/repos/linux4sam/at91bootstrap/commits/c57de507e54768e285729799a24d026fc4b3f756"}]}