{"push_id":841610173,"size":63,"distinct_size":63,"ref":"refs/heads/master","head":"5c905903e8f3a2836cbc09f8045b40ccb284503b","before":"c2857bda279678dd52accab92934b7b9a72c7a54","commits":[{"sha":"434302d503c8eeb7e47c9155488367145e2ed907","author":{"email":"fbe9e45cbb51ebd86366cc402735e3c7e9b1e064@gmail.com","name":"David Majnemer"},"message":"[MC] Add support for GNU as-compatible binary operator precedence\n\nGNU as and Darwin give the various binary operators different\nprecedence.  LLVM's MC supported the Darwin semantics but not the GNU\nsemantics.\n\nThis fixes PR25311.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251271 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/434302d503c8eeb7e47c9155488367145e2ed907"},{"sha":"c08caf74139885b70eaf698b98dcc4f7a7389c45","author":{"email":"fbe9e45cbb51ebd86366cc402735e3c7e9b1e064@gmail.com","name":"David Majnemer"},"message":"Update test to take into account for r251271.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251272 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/c08caf74139885b70eaf698b98dcc4f7a7389c45"},{"sha":"88b1f94ab52399f98b631abfe6f69fcf3fe157c8","author":{"email":"74486463aa8344ad78208a26153a7177f8db5983@gmail.com","name":"Lang Hames"},"message":"[Orc] In the CompileOnDemand layer, wrap module ownership in order to preserve\nthe module pointer type passed in by the user.\n\nThe previous ownership scheme, where the user pointer was always moved into a\nstd::shared_ptr, breaks if the user passes in a raw pointer.\n\nDiscovered while working on the Orc C API, which should be landing shortly.\nI expect to include a test-case with that.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251273 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/88b1f94ab52399f98b631abfe6f69fcf3fe157c8"},{"sha":"540bea1f528a37c69d3a281ab43dd482f7907f9d","author":{"email":"74486463aa8344ad78208a26153a7177f8db5983@gmail.com","name":"Lang Hames"},"message":"[Orc] Add license header to OrcTargetSupport.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251274 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/540bea1f528a37c69d3a281ab43dd482f7907f9d"},{"sha":"31a3f5f4a1783dafc8addc5677e55f05d457597a","author":{"email":"bce72489011e5753569f2110bd524579066fa193@intel.com","name":"Igor Breger"},"message":"AVX512: Add AVX-512 not materializable instructions. \nOtherwise value can be reused , despite its value could be changed - produces incorrect assembler.\n\nhttps://llvm.org/bugs/show_bug.cgi?id=25270\n\nDifferential Revision: http://reviews.llvm.org/D14057\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251275 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/31a3f5f4a1783dafc8addc5677e55f05d457597a"},{"sha":"6f975c928c74fa24dbfa28eca475c0b11e4dda23","author":{"email":"ea91796269c7842d401af30276638d4aaa593379@googlemail.com","name":"Benjamin Kramer"},"message":"Drop code after unreachable. No functionality change.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251278 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/6f975c928c74fa24dbfa28eca475c0b11e4dda23"},{"sha":"82ace96a30933c2ded81521de51774d406aba3b1","author":{"email":"f4a524c472c347a18d71daaa7c4ae51db69c69da@arm.com","name":"James Molloy"},"message":"[ARM] Handle the inline asm constraint type 'o'\n\nThis means \"memory with offset\" and requires very little plumbing to get working. This fixes PR25317.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251280 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/82ace96a30933c2ded81521de51774d406aba3b1"},{"sha":"ebacf44320b5aa59efa03cd0ae90935fc4b953fd","author":{"email":"35e141d918c3ab40e625222c41fcc8b2333c1294@arm.com","name":"Silviu Baranga"},"message":"[InstCombine] Teach instcombine not to create extra PHI nodes when folding GEPs\n\nSummary:\nInstCombine tries to transform GEP(PHI(GEP1, GEP2, ..)) into GEP(GEP(PHI(...))\nwhen possible. However, this may leave the old PHI node around. Even if we\ndo end up folding the GEPs, having an extra PHI node might not be beneficial.\n\nThis change makes the transformation more conservative. We now only do this if\nthe PHI has only one use, and can therefore be removed after the transformation.\n\nReviewers: jmolloy, majnemer\n\nSubscribers: mcrosier, mssimpso, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D13887\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251281 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/ebacf44320b5aa59efa03cd0ae90935fc4b953fd"},{"sha":"e1ed72f4594726ef7ed4afcfe14c82a7097b6c29","author":{"email":"35e141d918c3ab40e625222c41fcc8b2333c1294@arm.com","name":"Silviu Baranga"},"message":"[SCEV] Factor out common visiting patterns for SCEV rewriters. NFC.\n\nSummary:\nAdd a SCEVRewriteVisitor class which contains the common\nvisiting patterns used when rewriting SCEVs.\n\nSCEVParameterRewriter and SCEVApplyRewriter now inherit\nfrom SCEVRewriteVisitor (and are therefore much simpler).\n\nReviewers: anemet, mzolotukhin, sanjoy\n\nSubscribers: rengolin, llvm-commits, sanjoy\n\nDifferential Revision: http://reviews.llvm.org/D13242\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251283 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/e1ed72f4594726ef7ed4afcfe14c82a7097b6c29"},{"sha":"40b928c9fe1f9fc7f7ffff720b029293aaac7fc1","author":{"email":"bce72489011e5753569f2110bd524579066fa193@intel.com","name":"Igor Breger"},"message":"AVX-512: Use correct extract vector length.\n\nBug https://llvm.org/bugs/show_bug.cgi?id=25318\n\nDifferential Revision: http://reviews.llvm.org/D14062\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251285 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/40b928c9fe1f9fc7f7ffff720b029293aaac7fc1"},{"sha":"9f2026ed3f9b66a84fd537c66fc3d09ce74aedb0","author":{"email":"d1d6fcc54c3fa761ad24d0db0db020ec8aa5f5ca@imgtec.com","name":"Vasileios Kalintiris"},"message":"[mips] Interrupt attribute support for mips32r2+.\n\nSummary:\nThis patch adds support for using the \"interrupt\" attribute on Mips\nfor interrupt handling functions. At this time only mips32r2+ with the\no32 ABI with the static relocation model is supported. Unsupported\nconfigurations will be rejected\n\nPatch by Simon Dardis (+ clang-format & some trivial changes to follow the\nLLVM coding standards by me).\n\nReviewers: mpf, dsanders\n\nSubscribers: dsanders, vkalintiris, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D10768\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251286 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/9f2026ed3f9b66a84fd537c66fc3d09ce74aedb0"},{"sha":"e9ad33d22d23f0316a5faccb9b005774df22effb","author":{"email":"bce72489011e5753569f2110bd524579066fa193@intel.com","name":"Igor Breger"},"message":"AVX512: Enabled VPBROADCASTB lowering for v64i8 vectors.\n\nDifferential Revision: http://reviews.llvm.org/D13896\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251287 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/e9ad33d22d23f0316a5faccb9b005774df22effb"},{"sha":"5f131f7a3701ff38c34fdbd9b449961a2a3b61ee","author":{"email":"bce72489011e5753569f2110bd524579066fa193@intel.com","name":"Igor Breger"},"message":"fix test errors (on windows) for commit r251287\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251288 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/5f131f7a3701ff38c34fdbd9b449961a2a3b61ee"},{"sha":"3d79a7932c2bba25244cc6a1582fc7cf504932bd","author":{"email":"26294bcb01cdc361afe06a2787bab8d16e97ede5@apple.com","name":"Tim Northover"},"message":"Tests: be slightly more specific to avoid conflict with path.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251290 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/3d79a7932c2bba25244cc6a1582fc7cf504932bd"},{"sha":"df91a787c0fd828dff5dcf7dc2965c4a11f94b99","author":{"email":"92f0075cc843baaa8e5be141782d35ca2fb90d2d@intel.com","name":"Elena Demikhovsky"},"message":"Loop Vectorizer - skipping \"bitcast\" before GEP\n\nVectorization of memory instruction (Load/Store) is possible when the pointer is coming from GEP. The GEP analysis allows to estimate the profit.\nIn some cases we have a \"bitcast\" between GEP and memory instruction.\nI added code that skips the \"bitcast\".\n\nhttp://reviews.llvm.org/D13886\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251291 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/df91a787c0fd828dff5dcf7dc2965c4a11f94b99"},{"sha":"bd8522817da585714a793d850da7e3eafc79b139","author":{"email":"35e141d918c3ab40e625222c41fcc8b2333c1294@arm.com","name":"Silviu Baranga"},"message":"[SCEV] Fix issues found during the review of r251283. NFC.\n\nSummary:\nReplace (const SCEVAddRecExpr *) with cast<SCEVAddRecExpr>.\n\nRename SCEVApplyRewriter to SCEVLoopAddRecRewriter (which is a more\nappropriate name) since the description is \"takes a scalar evolution\nexpression and applies the Map (Loop -> SCEV) to all AddRecExprs.\"\n\nSubscribers: llvm-commits, sanjoy\n\nDifferential Revision: http://reviews.llvm.org/D14065\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251292 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/bd8522817da585714a793d850da7e3eafc79b139"},{"sha":"bf7b3fed5c75e7256ac395c01a7770edb20735e8","author":{"email":"f4a524c472c347a18d71daaa7c4ae51db69c69da@arm.com","name":"James Molloy"},"message":"[ValueTracking] Extend r251146 to catch a fairly common case\n\nEven though we may not know the value of the shifter operand, it's possible we know the shifter operand is non-zero. This can allow us to infer more known bits - for example:\n\n  %1 = load %p !range {1, 5}\n  %2 = shl %q, %1\n\nWe don't know %1, but we do know that it is nonzero so %2[0] is known zero, and importantly %2 is known non-zero.\n\nCalling isKnownNonZero is nontrivially expensive so use an Optional to run it lazily and cache its result.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251294 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/bf7b3fed5c75e7256ac395c01a7770edb20735e8"},{"sha":"2df12188c55cf8e764407b32834d820fbb6acada","author":{"email":"d1d6fcc54c3fa761ad24d0db0db020ec8aa5f5ca@imgtec.com","name":"Vasileios Kalintiris"},"message":"[mips] Check for the correct error message in tests for interrupt attributes.\n\nInstead of XFAIL-ing the tests with the wrong usage of the \"interrupt\"\nattribute, we should check that we emit the correct error messages to\nthe user.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251295 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/2df12188c55cf8e764407b32834d820fbb6acada"},{"sha":"436e7ea464665201747c1cfe5135339d6638a62b","author":{"email":"dc5e0dddc73b83fc14defbf1cf7a0a7158c853d2@ericsson.com","name":"Jonas Paulsson"},"message":"[SystemZ] Tie operands in SystemZShorteInst if MI becomes 2-address.\n\nDiscovered by testing fp-add-02.ll with -verify-machineinstrs.\n\nTest case updated to always run with -verify-machineinstrs.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251296 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/436e7ea464665201747c1cfe5135339d6638a62b"},{"sha":"599024dc12d22fdc79279e356a8436729508183d","author":{"email":"dc5e0dddc73b83fc14defbf1cf7a0a7158c853d2@ericsson.com","name":"Jonas Paulsson"},"message":"[SystemZ] Don't forget the CC def op on LTEBRCompare pseudos\n\nDiscovered by running fp-cmp-02.ll with -verify-machineinstrs (now added\nto test run).\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251297 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/599024dc12d22fdc79279e356a8436729508183d"}]}