{"push_id":752241109,"size":229,"distinct_size":229,"ref":"refs/heads/master","head":"bd48c0617b5c7212e5bf22169e716da878842da4","before":"ae27120c31d58b8bb694d9155bcffdcfae8552a6","commits":[{"sha":"bfa89d2ba8f0a278df6de584dcfbd33814753e33","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: socfpga: Fix FPGA bitstream programming routine\n\nIn case the FPGA bitstream is aligned to 4 bytes, skip the\npart of the assembler which handles unaligned bitstream.\nOtherwise, that part will loop indefinitelly.\n\nSigned-off-by: Marek Vasut <marex@denx.de>\nCc: Dinh Nguyen <dinguyen@opensource.altera.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/bfa89d2ba8f0a278df6de584dcfbd33814753e33"},{"sha":"b09b72d83b17f353bed47df9ddaba8380a06e9f5","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: dts: socfpga: Fix SPI aliases\n\nThe SPI aliases are completely wrong. First, they point to non-existing\n/spi@.* nodes instead of the correct /soc/spi@.* nodes. Second, the use\nad-hoc string instead of a handle. Furthermore, they are copied multiple\ntimes in each board DTS.\n\nSo fix it such that we move these into socfpga.dtsi and make them use\nthe usual handles.\n\nSigned-off-by: Marek Vasut <marex@denx.de>\nCc: Dinh Nguyen <dinguyen@opensource.altera.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/b09b72d83b17f353bed47df9ddaba8380a06e9f5"},{"sha":"2e8fcc7e41cc5fea7fa399e5e35fc261fa67b13b","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: dts: socfpga: Add mmc alias\n\nAdd alias for the SD/MMC controller, so it can be located by U-Boot OF support.\n\nSigned-off-by: Marek Vasut <marex@denx.de>\nCc: Dinh Nguyen <dinguyen@opensource.altera.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/2e8fcc7e41cc5fea7fa399e5e35fc261fa67b13b"},{"sha":"9617ceb9cfc1eeb3ca0d962b53d2d87506cc23ca","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: socfpga: Move generated files into qts subdir\n\nMove all the files generated by Quartus into the qts/ subdir of the\nboard/altera/socfpga dir to make them explicitly separate from the\ngeneric U-Boot code.\n\nSigned-off-by: Marek Vasut <marex@denx.de>\nCc: Dinh Nguyen <dinguyen@opensource.altera.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/9617ceb9cfc1eeb3ca0d962b53d2d87506cc23ca"},{"sha":"b9628595b40ec30e1b60ef437127a7b332ee4835","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"net: designware: Add SoCFPGA GMAC DT compatible string\n\nAdd the OF compatible property to match the SoCFPGA GMAC.\n\nSigned-off-by: Marek Vasut <marex@denx.de>\nCc: Dinh Nguyen <dinguyen@opensource.altera.com>\nAcked-by: Joe Hershberger <joe.hershberger@ni.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/b9628595b40ec30e1b60ef437127a7b332ee4835"},{"sha":"9f76f105c765d3c681309137e9ca5364e1ae9f2a","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"net: designware: Rename the driver var name to eth_designware\n\nThe driver variable name is eth_sandbox, which is probably a copy-paste\nmistake. Fix it.\n\nSigned-off-by: Marek Vasut <marex@denx.de>\nCc: Dinh Nguyen <dinguyen@opensource.altera.com>\nAcked-by: Joe Hershberger <joe.hershberger@ni.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/9f76f105c765d3c681309137e9ca5364e1ae9f2a"},{"sha":"9bbd2132e3af95ac225f3641b69bd129da11457f","author":{"email":"a48724738fc762a7f206428dfcaf7ede2fd84d0f@opensource.altera.com","name":"Dinh Nguyen"},"message":"driver/ddr/altera: Add DDR driver for Altera's SDRAM controller\n\nThis patch enables the SDRAM controller that is used on Altera's SoCFPGA\nfamily. This patch configures the SDRAM controller based on a configuration\nfile that is generated from the Quartus tool, sdram_config.h.\n\nSigned-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/9bbd2132e3af95ac225f3641b69bd129da11457f"},{"sha":"3da428595e861f90ff0d6687cedff3056f7c7890","author":{"email":"a48724738fc762a7f206428dfcaf7ede2fd84d0f@opensource.altera.com","name":"Dinh Nguyen"},"message":"driver/ddr/altera: Add the sdram calibration portion\n\nThis patch adds the DDR calibration portion of the Altera SDRAM driver.\n\nSigned-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/3da428595e861f90ff0d6687cedff3056f7c7890"},{"sha":"cdd4e6cc372b643e0aa09b5c31ff7e32d7a076de","author":{"email":"a48724738fc762a7f206428dfcaf7ede2fd84d0f@opensource.altera.com","name":"Dinh Nguyen"},"message":"arm: socfpga: enable the Altera SDRAM controller driver\n\nEnable the Altera SDRAM driver for the SoCFPGA platform.\n\nSigned-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>\nAcked-by: Marek Vasut <marex@denx.de>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/cdd4e6cc372b643e0aa09b5c31ff7e32d7a076de"},{"sha":"d04941cf3314c4b1f75f5c5d543b0c6257eff1ee","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: socfpga: Move sdram_config.h to board dir\n\nThis file is absolutelly positively board specific, so move it\ninto the correct place.\n\nSigned-off-by: Marek Vasut <marex@denx.de>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/d04941cf3314c4b1f75f5c5d543b0c6257eff1ee"},{"sha":"42f7ebb82bce6f145ded1a469b1377fee34d32fa","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"ddr: altera: Move struct sdram_prot_rule prototype\n\nMove the structure prototype from sdram.h header file into sdram.c\nsource file, since it is used only there and for local purpose only.\nThere is no point in having it global.\n\nWhile at this move, fix the data types in the structure from uintNN_t\nto uNN and fix the coding style a bit.\n\nSigned-off-by: Marek Vasut <marex@denx.de>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/42f7ebb82bce6f145ded1a469b1377fee34d32fa"},{"sha":"452a81e0786825d0a86c26d320b22055a387c749","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"ddr: altera: Fix typo in mp_threshold1 programming\n\nIt is the configuration data that should go into the register,\nnot the register mask, just like the surrounding code does it.\nFix this typo.\n\nSigned-off-by: Marek Vasut <marex@denx.de>\nCc: Chin Liang See <clsee@altera.com>\nCc: Dinh Nguyen <dinguyen@altera.com>\nCc: Tom Rini <trini@konsulko.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/452a81e0786825d0a86c26d320b22055a387c749"},{"sha":"7ac40d25cfab5502ab38c323f5b862ced4ea1dad","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"ddr: altera: Fix debug message format in sequencer\n\nThe debug messages missed proper newlines and/or spaces in them.\nFix the formatting.\n\nSigned-off-by: Marek Vasut <marex@denx.de>\nCc: Chin Liang See <clsee@altera.com>\nCc: Dinh Nguyen <dinguyen@altera.com>\nCc: Tom Rini <trini@konsulko.com>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/7ac40d25cfab5502ab38c323f5b862ced4ea1dad"},{"sha":"8d009e4542e88b511bab1ce194ba3b04c5c0f6ae","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: socfpga: reset: Add missing reset manager regs\n\nDefine two missing reset manager registers, which are in the\nSoCFPGA CV datasheet.\n\nSigned-off-by: Marek Vasut <marex@denx.de>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/8d009e4542e88b511bab1ce194ba3b04c5c0f6ae"},{"sha":"1115cd2de76bf698b0e621c0c71e4a2cd5ab3b2a","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: socfpga: reset: Start reworking the SoCFPGA reset manager\n\nImplement macro SOCFPGA_RESET(name), which produces an abstract\nreset number. Implement macros which allow extracting the reset\noffset in permodrstN register and which permodrstN register the\nreset is located in from this abstract reset number. Use these\nmacros throughout the reset manager.\n\nSigned-off-by: Marek Vasut <marex@denx.de>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/1115cd2de76bf698b0e621c0c71e4a2cd5ab3b2a"},{"sha":"bdfc2ef64a4df550a4090c31dae9a133c92ac5ca","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: socfpga: reset: Implement unified function to toggle reset\n\nImplement function socfpga_per_reset(), which allows asserting or\nde-asserting reset of each reset manager peripheral in a unified\nmanner. Use this function throughout reset manager.\n\nSigned-off-by: Marek Vasut <marex@denx.de>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/bdfc2ef64a4df550a4090c31dae9a133c92ac5ca"},{"sha":"a71df7aa4fa775199280bba19072bd232cc35cb1","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: socfpga: reset: Replace ad-hoc reset functions\n\nReplace all those ad-hoc reset functions, which were all copies\nof the same invocation of clrbits_le32() anyway, with one single\nunified function, socfpga_per_reset(), with necessary parameters.\n\nSigned-off-by: Marek Vasut <marex@denx.de>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/a71df7aa4fa775199280bba19072bd232cc35cb1"},{"sha":"292260ca21723ab78d23fa2cf6b574cf17778991","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: socfpga: reset: Repair bridge reset handling\n\nThe current bridge reset code, which de-asserted the bridge reset,\nwas activelly polling whether the FPGA is programmed and ready and\nin case it was (!), the code called hang(). This makes no sense at\nall. Repair it such that the code instead checks whether the FPGA\nis programmed, but without any polling involved, and only if it is\nprogrammed, it de-asserts the reset.\n\nSigned-off-by: Marek Vasut <marex@denx.de>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/292260ca21723ab78d23fa2cf6b574cf17778991"},{"sha":"3191611a05df993826a0d2d0d5607e5e38365cce","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: socfpga: reset: Add function to reset add peripherals\n\nAdd socfpga_per_reset_all() function to reset all peripherals\nbut the L4 watchdog. This is needed in the SPL.\n\nSigned-off-by: Marek Vasut <marex@denx.de>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/3191611a05df993826a0d2d0d5607e5e38365cce"},{"sha":"34122eb2621ff49e5e85ef89f98a823db4ff2c68","author":{"email":"f40600653b33f5282fa4c5daf377dfc444fb4625@denx.de","name":"Marek Vasut"},"message":"arm: socfpga: reset: Add SDMMC, QSPI and DMA defines\n\nAdd SDMMC, QSPI and DMA reset defines. These are needed by SPL\nso that we can boot from SD card and QSPI.\n\nSigned-off-by: Marek Vasut <marex@denx.de>","distinct":true,"url":"https://api.github.com/repos/RobertCNelson/u-boot/commits/34122eb2621ff49e5e85ef89f98a823db4ff2c68"}]}