{"push_id":784005605,"size":214,"distinct_size":0,"ref":"refs/heads/<74ffe4f3-c653-4e67-a8d0-2bf9cae1c53c@HUB1.rwth-ad.de>","head":"4fdd83ccbe322bd699c2c37bb37e30e0340d2210","before":"26ae1e8a64f8cfb1f68d95f7e6de6fb455bedf57","commits":[{"sha":"5f2a80adc6fd2b2e4e0579a6613a9913e3cc9a05","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Rewrite helper_cmpbge using bit tests\n\nNot quite as good as using a proper host vector compare,\nbut certainly better than a loop.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/5f2a80adc6fd2b2e4e0579a6613a9913e3cc9a05"},{"sha":"112e4518f0d38fc3c52e55c7d7e77b66a295ec2b","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"target-alpha: Special case cmpbge with zero\n\nKnowing the comparator is zero leads to a simpler operation.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/112e4518f0d38fc3c52e55c7d7e77b66a295ec2b"},{"sha":"29f3ff8d6cbc28f79933aeaa25805408d0984a8f","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg/optimize: fix constant signedness\n\nBy convention, on a 64-bit host TCG internally stores 32-bit constants\nas sign-extended. This is not the case in the optimizer when a 32-bit\nconstant is folded.\n\nThis doesn't seem to have more consequences than suboptimal code\ngeneration. For instance the x86 backend assumes sign-extended constants,\nand in some rare cases uses a 32-bit unsigned immediate 0xffffffff\ninstead of a 8-bit signed immediate 0xff for the constant -1. This is\nwith a ppc guest:\n\nbefore\n------\n\n ---- 0x9f29cc\n movi_i32 tmp1,$0xffffffff\n movi_i32 tmp2,$0x0\n add2_i32 tmp0,CA,CA,tmp2,r6,tmp2\n add2_i32 tmp0,CA,tmp0,CA,tmp1,tmp2\n mov_i32 r10,tmp0\n\n0x7fd8c7dfe90c:  xor    %ebp,%ebp\n0x7fd8c7dfe90e:  mov    %ebp,%r11d\n0x7fd8c7dfe911:  mov    0x18(%r14),%r9d\n0x7fd8c7dfe915:  add    %r9d,%r10d\n0x7fd8c7dfe918:  adc    %ebp,%r11d\n0x7fd8c7dfe91b:  add    $0xffffffff,%r10d\n0x7fd8c7dfe922:  adc    %ebp,%r11d\n0x7fd8c7dfe925:  mov    %r11d,0x134(%r14)\n0x7fd8c7dfe92c:  mov    %r10d,0x28(%r14)\n\nafter\n-----\n\n ---- 0x9f29cc\n movi_i32 tmp1,$0xffffffffffffffff\n movi_i32 tmp2,$0x0\n add2_i32 tmp0,CA,CA,tmp2,r6,tmp2\n add2_i32 tmp0,CA,tmp0,CA,tmp1,tmp2\n mov_i32 r10,tmp0\n\n0x7f37010d490c:  xor    %ebp,%ebp\n0x7f37010d490e:  mov    %ebp,%r11d\n0x7f37010d4911:  mov    0x18(%r14),%r9d\n0x7f37010d4915:  add    %r9d,%r10d\n0x7f37010d4918:  adc    %ebp,%r11d\n0x7f37010d491b:  add    $0xffffffffffffffff,%r10d\n0x7f37010d491f:  adc    %ebp,%r11d\n0x7f37010d4922:  mov    %r11d,0x134(%r14)\n0x7f37010d4929:  mov    %r10d,0x28(%r14)\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nMessage-Id: <1436544211-2769-2-git-send-email-aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/29f3ff8d6cbc28f79933aeaa25805408d0984a8f"},{"sha":"1208d7dd5fddc1fbd98de800d17429b4e5578848","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg/optimize: optimize temps tracking\n\nThe tcg_temp_info structure uses 24 bytes per temp. Now that we emulate\nvector registers on most guests, it's not uncommon to have more than 100\nused temps. This means we have initialize more than 2kB at least twice\nper TB, often more when there is a few goto_tb.\n\nInstead used a TCGTempSet bit array to track which temps are in used in\nthe current basic block. This means there are only around 16 bytes to\ninitialize.\n\nThis improves the boot time of a MIPS guest on an x86-64 host by around\n7% and moves out tcg_optimize from the the top of the profiler list.\n\n[rth: Handle TCG_CALL_DUMMY_ARG]\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/1208d7dd5fddc1fbd98de800d17429b4e5578848"},{"sha":"d9c769c60948815ee03b2684b1c1c68ee4375149","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg/optimize: add temp_is_const and temp_is_copy functions\n\nAdd two accessor functions temp_is_const and temp_is_copy, to make the\ncode more readable and make code change easier.\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/d9c769c60948815ee03b2684b1c1c68ee4375149"},{"sha":"b41059dd9deec367a4ccd296659f0bc5de2dc705","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg/optimize: track const/copy status separately\n\nInstead of using an enum which could be either a copy or a const, track\nthem separately. This will be used in the next patch.\n\nConstants are tracked through a bool. Copies are tracked by initializing\ntemp's next_copy and prev_copy to itself, allowing to simplify the code\na bit.\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/b41059dd9deec367a4ccd296659f0bc5de2dc705"},{"sha":"299f80130401153af1a6ddb3cc011781bcd47600","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg/optimize: allow constant to have copies\n\nNow that copies and constants are tracked separately, we can allow\nconstant to have copies, deferring the choice to use a register or a\nconstant to the register allocation pass. This prevent this kind of\nregular constant reloading:\n\n-OUT: [size=338]\n+OUT: [size=298]\n   mov    -0x4(%r14),%ebp\n   test   %ebp,%ebp\n   jne    0x7ffbe9cb0ed6\n   mov    $0x40002219f8,%rbp\n   mov    %rbp,(%r14)\n-  mov    $0x40002219f8,%rbp\n   mov    $0x4000221a20,%rbx\n   mov    %rbp,(%rbx)\n   mov    $0x4000000000,%rbp\n   mov    %rbp,(%r14)\n-  mov    $0x4000000000,%rbp\n   mov    $0x4000221d38,%rbx\n   mov    %rbp,(%rbx)\n   mov    $0x40002221a8,%rbp\n   mov    %rbp,(%r14)\n-  mov    $0x40002221a8,%rbp\n   mov    $0x4000221d40,%rbx\n   mov    %rbp,(%rbx)\n   mov    $0x4000019170,%rbp\n   mov    %rbp,(%r14)\n-  mov    $0x4000019170,%rbp\n   mov    $0x4000221d48,%rbx\n   mov    %rbp,(%rbx)\n   mov    $0x40000049ee,%rbp\n   mov    %rbp,0x80(%r14)\n   mov    %r14,%rdi\n   callq  0x7ffbe99924d0\n   mov    $0x4000001680,%rbp\n   mov    %rbp,0x30(%r14)\n   mov    0x10(%r14),%rbp\n   mov    $0x4000001680,%rbp\n   mov    %rbp,0x30(%r14)\n   mov    0x10(%r14),%rbp\n   shl    $0x20,%rbp\n   mov    (%r14),%rbx\n   mov    %ebx,%ebx\n   mov    %rbx,(%r14)\n   or     %rbx,%rbp\n   mov    %rbp,0x10(%r14)\n   mov    %rbp,0x90(%r14)\n   mov    0x60(%r14),%rbx\n   mov    %rbx,0x38(%r14)\n   mov    0x28(%r14),%rbx\n   mov    $0x4000220e60,%r12\n   mov    %rbx,(%r12)\n   mov    $0x40002219c8,%rbx\n   mov    %rbp,(%rbx)\n   mov    0x20(%r14),%rbp\n   sub    $0x8,%rbp\n   mov    $0x4000004a16,%rbx\n   mov    %rbx,0x0(%rbp)\n   mov    %rbp,0x20(%r14)\n   mov    $0x19,%ebp\n   mov    %ebp,0xa8(%r14)\n   mov    $0x4000015110,%rbp\n   mov    %rbp,0x80(%r14)\n   xor    %eax,%eax\n   jmpq   0x7ffbebcae426\n   lea    -0x5f6d72a(%rip),%rax        # 0x7ffbe3d437b3\n   jmpq   0x7ffbebcae426\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/299f80130401153af1a6ddb3cc011781bcd47600"},{"sha":"0632e555fc4d281d69cb08d98d500d96185b041f","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg: rename trunc_shr_i32 into trunc_shr_i64_i32\n\nThe op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32,\nand the name in the README doesn't match the name offered to the\nfrontends.\n\nAlways use the long name to make it clear it is a size changing op.\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/0632e555fc4d281d69cb08d98d500d96185b041f"},{"sha":"6acd2558fdb7dd9de6b10697914bdc1d75d624e5","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg: don't abuse TCG type in tcg_gen_trunc_shr_i64_i32\n\nThe tcg_gen_trunc_shr_i64_i32 function takes a 64-bit argument and\nreturns a 32-bit value. Directly call tcg_gen_op3 with the correct\ntypes instead of calling tcg_gen_op3i_i32 and abusing the TCG types.\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/6acd2558fdb7dd9de6b10697914bdc1d75d624e5"},{"sha":"4f2331e5b67af8172419eb1c8db510b497b30a7b","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg: implement real ext_i32_i64 and extu_i32_i64 ops\n\nImplement real ext_i32_i64 and extu_i32_i64 ops. They ensure that a\n32-bit value is always converted to a 64-bit value and not propagated\nthrough the register allocator or the optimizer.\n\nCc: Andrzej Zaborowski <balrogg@gmail.com>\nCc: Alexander Graf <agraf@suse.de>\nCc: Blue Swirl <blauwirbel@gmail.com>\nCc: Stefan Weil <sw@weilnetz.de>\nAcked-by: Claudio Fontana <claudio.fontana@huawei.com>\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/4f2331e5b67af8172419eb1c8db510b497b30a7b"},{"sha":"8bcb5c8f34f9215d4f88f388c7ff14c9bd5cecd3","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg/optimize: add optimizations for ext_i32_i64 and extu_i32_i64 ops\n\nThey behave the same as ext32s_i64 and ext32u_i64 from the constant\nfolding and zero propagation point of view, except that they can't\nbe replaced by a mov, so we don't compute the affected value.\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/8bcb5c8f34f9215d4f88f388c7ff14c9bd5cecd3"},{"sha":"870ad1547ac53bc79c21d86cf453b3b20cc660a2","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg: update README about size changing ops\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/870ad1547ac53bc79c21d86cf453b3b20cc660a2"},{"sha":"609ad70562793937257c89d07bf7c1370b9fc9aa","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32\n\nRather than allow arbitrary shift+trunc, only concern ourselves\nwith low and high parts.  This is all that was being used anyway.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/609ad70562793937257c89d07bf7c1370b9fc9aa"},{"sha":"ecc7b3aa71f5fdcf9ee87e74ca811d988282641d","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg: Remove tcg_gen_trunc_i64_i32\n\nReplacing it with tcg_gen_extrl_i64_i32.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/ecc7b3aa71f5fdcf9ee87e74ca811d988282641d"},{"sha":"8cc580f6a0d8c0e2f590c1472cf5cd8e51761760","author":{"email":"bceb368e7f2cb351af47298f32034f0587bbe4a6@aurel32.net","name":"Aurelien Jarno"},"message":"tcg/i386: use softmmu fast path for unaligned accesses\n\nSoftmmu unaligned load/stores currently goes through through the slow\npath for two reasons:\n  - to support unaligned access on host with strict alignement\n  - to correctly handle accesses crossing pages\n\nx86 is only concerned by the second reason. Unaligned accesses are\navoided by compilers, but are not uncommon. We therefore would like\nto see them going through the fast path, if they don't cross pages.\n\nFor that we can use the fact that two adjacent TLB entries can't contain\nthe same page. Therefore accessing the TLB entry corresponding to the\nfirst byte, but comparing its content to page address of the last byte\nensures that we don't cross pages. We can do this check without adding\nmore instructions in the TLB code (but increasing its length by one\nbyte) by using the LEA instruction to combine the existing move with the\nsize addition.\n\nOn an x86-64 host, this gives a 3% boot time improvement for a powerpc\nguest and 4% for an x86-64 guest.\n\n[rth: Tidied calculation of the offset mask]\n\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>\nMessage-Id: <1436467197-2183-1-git-send-email-aurelien@aurel32.net>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/8cc580f6a0d8c0e2f590c1472cf5cd8e51761760"},{"sha":"68d45bb61c5bbfb3999486f78cf026c1e79eb301","author":{"email":"a7089bb6e7e92505d88aaff006cbdd60cc9120b6@kernel.crashing.org","name":"Benjamin Herrenschmidt"},"message":"tcg/ppc: Improve unaligned load/store handling on 64-bit backend\n\nCurrently, we get to the slow path for any unaligned access in the\nbackend, because we effectively preserve the bottom address bits\nbelow the alignment requirement when comparing with the TLB entry,\nso any non-0 bit there will cause the compare to fail.\n\nFor the same number of instructions, we can instead add the access\nsize - 1 to the address and stick to clearing all the bottom bits.\n\nThat means that normal unaligned accesses will not fallback (the HW\nwill handle them fine). Only when crossing a page boundary well we\nend up having a mismatch because we'll end up pointing to the next\npage which cannot possibly be in that same TLB entry.\n\nReviewed-by: Aurelien Jarno <aurelien@aurel32.net>\nSigned-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>\nMessage-Id: <1437455978.5809.2.camel@kernel.crashing.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/68d45bb61c5bbfb3999486f78cf026c1e79eb301"},{"sha":"a5e39810b9088b5d20fac8e0293f281e1c8b608f","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg/s390: Use softmmu fast path for unaligned accesses\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/a5e39810b9088b5d20fac8e0293f281e1c8b608f"},{"sha":"9ee14902bf107e37fb2c8119fa7bca424396237c","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg/aarch64: Use softmmu fast path for unaligned accesses\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/9ee14902bf107e37fb2c8119fa7bca424396237c"},{"sha":"4cbea5986981998cda07b13794c7e3ff7bc42e80","author":{"email":"f1b010126f61b5c59e7d5eb42c5c68f6105c5914@vivier.eu","name":"Laurent Vivier"},"message":"linux-user: remove --enable-guest-base/--disable-guest-base\n\nAll tcg host architectures now support the guest base and as\nthere is no real performance lost, it can be always enabled.\n\nAnyway, guest base use can be disabled lively by setting guest\nbase to 0.\n\nCONFIG_USE_GUEST_BASE is defined as (USE_GUEST_BASE && USER_ONLY),\nit should have to be replaced by CONFIG_USER_ONLY in non CONFIG_USER_ONLY\nparts, but as some other parts are using !CONFIG_SOFTMMU I have chosen to\nuse !CONFIG_SOFTMMU instead.\n\nReviewed-by: Alexander Graf <agraf@suse.de>\nSigned-off-by: Laurent Vivier <laurent@vivier.eu>\nMessage-Id: <1440373328-9788-2-git-send-email-laurent@vivier.eu>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/4cbea5986981998cda07b13794c7e3ff7bc42e80"},{"sha":"b76f21a70748b735d6ac84fec4bb9bdaafa339b1","author":{"email":"f1b010126f61b5c59e7d5eb42c5c68f6105c5914@vivier.eu","name":"Laurent Vivier"},"message":"linux-user: remove useless macros GUEST_BASE and RESERVED_VA\n\nAs we have removed CONFIG_USE_GUEST_BASE, we always use a guest base\nand the macros GUEST_BASE and RESERVED_VA become useless: replace\nthem by their values.\n\nReviewed-by: Alexander Graf <agraf@suse.de>\nSigned-off-by: Laurent Vivier <laurent@vivier.eu>\nMessage-Id: <1440420834-8388-1-git-send-email-laurent@vivier.eu>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":false,"url":"https://api.github.com/repos/famz/qemu-patchew/commits/b76f21a70748b735d6ac84fec4bb9bdaafa339b1"}]}