{"push_id":742295832,"size":3,"distinct_size":3,"ref":"refs/heads/clockFix","head":"a780336c874f43cc17428ee9ef4e7f0e7e077163","before":"51006c2f657ffce03c26b07c81d6eab8b7136c91","commits":[{"sha":"e7b778b5fbc6eb71f776fccdd239724ce8ff069f","author":{"email":"06fa905d7f2aaced6dc72e9511c71a2a51e8aead@tridgell.net","name":"Stephen Tridgell"},"message":"Added a test case for same reset with two clocks, emulator is failing","distinct":true,"url":"https://api.github.com/repos/da-steve101/chisel/commits/e7b778b5fbc6eb71f776fccdd239724ce8ff069f"},{"sha":"685e6862f59ac525b7f69acddc345c8b809ffa42","author":{"email":"06fa905d7f2aaced6dc72e9511c71a2a51e8aead@tridgell.net","name":"Stephen Tridgell"},"message":"Moved emitRef logic to Backend, have Verilog call super,\nfix multiple reset issue by ensuring unique def and correct clock names for unnamed clock","distinct":true,"url":"https://api.github.com/repos/da-steve101/chisel/commits/685e6862f59ac525b7f69acddc345c8b809ffa42"},{"sha":"a780336c874f43cc17428ee9ef4e7f0e7e077163","author":{"email":"06fa905d7f2aaced6dc72e9511c71a2a51e8aead@tridgell.net","name":"Stephen Tridgell"},"message":"Update tests as ref indexs have now changed","distinct":true,"url":"https://api.github.com/repos/da-steve101/chisel/commits/a780336c874f43cc17428ee9ef4e7f0e7e077163"}]}