{"action":"created","issue":{"url":"https://api.github.com/repos/avr-llvm/llvm/issues/126","labels_url":"https://api.github.com/repos/avr-llvm/llvm/issues/126/labels{/name}","comments_url":"https://api.github.com/repos/avr-llvm/llvm/issues/126/comments","events_url":"https://api.github.com/repos/avr-llvm/llvm/issues/126/events","html_url":"https://github.com/avr-llvm/llvm/pull/126","id":89127995,"number":126,"title":"Experimental: Better inline asm","user":{"login":"agnat","id":137545,"avatar_url":"https://avatars.githubusercontent.com/u/137545?v=3","gravatar_id":"","url":"https://api.github.com/users/agnat","html_url":"https://github.com/agnat","followers_url":"https://api.github.com/users/agnat/followers","following_url":"https://api.github.com/users/agnat/following{/other_user}","gists_url":"https://api.github.com/users/agnat/gists{/gist_id}","starred_url":"https://api.github.com/users/agnat/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/agnat/subscriptions","organizations_url":"https://api.github.com/users/agnat/orgs","repos_url":"https://api.github.com/users/agnat/repos","events_url":"https://api.github.com/users/agnat/events{/privacy}","received_events_url":"https://api.github.com/users/agnat/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":6,"created_at":"2015-06-17T21:17:19Z","updated_at":"2015-06-18T11:53:58Z","closed_at":null,"pull_request":{"url":"https://api.github.com/repos/avr-llvm/llvm/pulls/126","html_url":"https://github.com/avr-llvm/llvm/pull/126","diff_url":"https://github.com/avr-llvm/llvm/pull/126.diff","patch_url":"https://github.com/avr-llvm/llvm/pull/126.patch"},"body":"This is work in progress.\r\n\r\nI started looking into inline assembly. I'm currently stuck at this test case from CodeGen/AVR/inline-asm.ll:\r\n\r\n``` asm\r\n; RUN: llc < %s -march=avr | FileCheck %s\r\n\r\n; CHECK-LABEL: multibyte_i32\r\ndefine void @multibyte_i32(i32 %a) {\r\nentry:\r\n; CHECK: instr r22 r23 r24 r25\r\n  call void asm sideeffect \"instr ${0:A} ${0:B} ${0:C} ${0:D}\", \"r\"(i32 %a)\r\n; CHECK: instr r25 r24 r23 r22\r\n  call void asm sideeffect \"instr ${0:D} ${0:C} ${0:B} ${0:A}\", \"r\"(i32 %a)\r\n  ret void\r\n}\r\n````\r\n\r\nSeems like handling of i32 values is missing. I've seen a few comments along the line \"We only support i8 and i16\". Why is that? Could you elaborate?"},"comment":{"url":"https://api.github.com/repos/avr-llvm/llvm/issues/comments/113129120","html_url":"https://github.com/avr-llvm/llvm/pull/126#issuecomment-113129120","issue_url":"https://api.github.com/repos/avr-llvm/llvm/issues/126","id":113129120,"user":{"login":"agnat","id":137545,"avatar_url":"https://avatars.githubusercontent.com/u/137545?v=3","gravatar_id":"","url":"https://api.github.com/users/agnat","html_url":"https://github.com/agnat","followers_url":"https://api.github.com/users/agnat/followers","following_url":"https://api.github.com/users/agnat/following{/other_user}","gists_url":"https://api.github.com/users/agnat/gists{/gist_id}","starred_url":"https://api.github.com/users/agnat/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/agnat/subscriptions","organizations_url":"https://api.github.com/users/agnat/orgs","repos_url":"https://api.github.com/users/agnat/repos","events_url":"https://api.github.com/users/agnat/events{/privacy}","received_events_url":"https://api.github.com/users/agnat/received_events","type":"User","site_admin":false},"created_at":"2015-06-18T11:53:58Z","updated_at":"2015-06-18T11:53:58Z","body":"I don't think we have to define additional patterns. Maybe load and store... at least not for the inline assembler.\r\n\r\nI think we're on the same page. I don't want to add more pseudos let alone a whole set of them. I'm always looking for opportunities to offload work to ... existing infrastructure. ;)\r\n\r\nRegarding `AVRExpandPseudoInsts.cpp`, I noticed the pattern. Pretty sure we can DRY that up. However, I think we should do #107 first... and yes that is a lot of work as it is.\r\n"}}