{"action":"created","comment":{"url":"https://api.github.com/repos/openrisc/mor1kx/pulls/comments/25629184","id":25629184,"diff_hunk":"@@ -669,6 +726,25 @@ endgenerate\n      endcase // case (opc_alu_secondary_i)\n \n    //\n+   // Comparison logic\n+   // To update SR[F] either from integer or float point comparision\n+   generate\n+     /* verilator lint_off WIDTH */\n+     if (FEATURE_FPU!=\"NONE\") begin\n+     /* verilator lint_on WIDTH */\n+       assign flag_set_o   = fpu_op_is_cmp ?","path":"rtl/verilog/mor1kx_execute_alu.v","position":119,"original_position":119,"commit_id":"ec58c223b1fae1009095dd030b498987581733ef","original_commit_id":"ec58c223b1fae1009095dd030b498987581733ef","user":{"login":"skristiansson","id":1028784,"avatar_url":"https://avatars.githubusercontent.com/u/1028784?v=3","gravatar_id":"","url":"https://api.github.com/users/skristiansson","html_url":"https://github.com/skristiansson","followers_url":"https://api.github.com/users/skristiansson/followers","following_url":"https://api.github.com/users/skristiansson/following{/other_user}","gists_url":"https://api.github.com/users/skristiansson/gists{/gist_id}","starred_url":"https://api.github.com/users/skristiansson/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/skristiansson/subscriptions","organizations_url":"https://api.github.com/users/skristiansson/orgs","repos_url":"https://api.github.com/users/skristiansson/repos","events_url":"https://api.github.com/users/skristiansson/events{/privacy}","received_events_url":"https://api.github.com/users/skristiansson/received_events","type":"User","site_admin":false},"body":"I think it'd be nicer to just let fpu_op_is_cmp evaluate to zero when FEATURE_FPU==\"NONE\" and get rid\r\nof the generate here.\r\nThat way if the flag_set_o logic would happen to change, there is only one code path to change.\r\nThe tools should be able to optimize the logic away from that.","created_at":"2015-03-02T19:27:43Z","updated_at":"2015-03-02T19:27:43Z","html_url":"https://github.com/openrisc/mor1kx/pull/26#discussion_r25629184","pull_request_url":"https://api.github.com/repos/openrisc/mor1kx/pulls/26","_links":{"self":{"href":"https://api.github.com/repos/openrisc/mor1kx/pulls/comments/25629184"},"html":{"href":"https://github.com/openrisc/mor1kx/pull/26#discussion_r25629184"},"pull_request":{"href":"https://api.github.com/repos/openrisc/mor1kx/pulls/26"}}},"pull_request":{"url":"https://api.github.com/repos/openrisc/mor1kx/pulls/26","id":30310875,"html_url":"https://github.com/openrisc/mor1kx/pull/26","diff_url":"https://github.com/openrisc/mor1kx/pull/26.diff","patch_url":"https://github.com/openrisc/mor1kx/pull/26.patch","issue_url":"https://api.github.com/repos/openrisc/mor1kx/issues/26","number":26,"state":"open","locked":false,"title":"Withfpu","user":{"login":"bandvig","id":6967860,"avatar_url":"https://avatars.githubusercontent.com/u/6967860?v=3","gravatar_id":"","url":"https://api.github.com/users/bandvig","html_url":"https://github.com/bandvig","followers_url":"https://api.github.com/users/bandvig/followers","following_url":"https://api.github.com/users/bandvig/following{/other_user}","gists_url":"https://api.github.com/users/bandvig/gists{/gist_id}","starred_url":"https://api.github.com/users/bandvig/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/bandvig/subscriptions","organizations_url":"https://api.github.com/users/bandvig/orgs","repos_url":"https://api.github.com/users/bandvig/repos","events_url":"https://api.github.com/users/bandvig/events{/privacy}","received_events_url":"https://api.github.com/users/bandvig/received_events","type":"User","site_admin":false},"body":"Well. As the good state of FPU is achieved, it is time for pull request.\r\nTo use FPU:\r\n(1) add all files from verilog/pfpu32 folder into your project\r\n(2) add .FEATURE_FPU(\"ENABLED\") in parameter list of mor1kx instance\r\n\r\nComparison with OR1200's FPU.\r\n\r\nOperation clock cost for:  ADD/SUB - MUL - DIV - I2F/F2I\r\nPort of OR1200 FPU     8  -   36 -  35 -    6\r\nPipelined FPU          5  -    6 -  18 -    3\r\n\r\nSize of standalone FPU (LUTs as logic, Spartan6, ISE14.6):\r\n\r\nPort of OR1200 FPU      : 2966 /  96 MHz\r\nPipelined FPU\r\n  DSP blocks arn't used : 2822 / 112 MHz\r\n  DSP blocks are used   : 1554 /  76 MHz  (+5 DSP modules)\r\n\r\nPerformance gain by Whetstone benchmark is up to 2 ... 3.5 times against OR1200's FPU and up to 20 times against soft-float depending on test. Detailed comparison will be published in mailing list after OpenRISC.NET operation restoring.\r\n\r\nAdditionally there is an extension to FPCSR. Thanks to the extension the each of FPU's exceptions  could be masked separately. The extension is blocked by default till approve from community. To activate the extension, uncomment the OR1K_FPCSR_MASK_FLAGS macro in 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