{"action":"created","comment":{"url":"https://api.github.com/repos/RIOT-OS/RIOT/pulls/comments/23310503","id":23310503,"diff_hunk":"@@ -0,0 +1,334 @@\n+/*\n+ * Copyright (C) 2014 Phytec Messtechnik GmbH\n+ *\n+ * This file is subject to the terms and conditions of the GNU Lesser\n+ * General Public License v2.1. See the file LICENSE in the top level\n+ * directory for more details.\n+ */\n+\n+/**\n+ * @ingroup     drivers_kw2xrf\n+ * @{\n+ *\n+ * @file\n+ * @brief       Register and command definitions for the MKW2XD Modem\n+ *\n+ * @author      Johann Fischer <j.fischer@phytec.de>\n+ */\n+\n+#ifndef MKW2XD_MODEM_REG_H\n+#define MKW2XD_MODEM_REG_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define MKW2XDRF_REG_READ               (uint8_t)(1 << 7)\n+#define MKW2XDRF_REG_WRITE              (uint8_t)(0)\n+#define MKW2XDRF_BUF_READ               (uint8_t)(1 << 7 | 1 << 6)\n+#define MKW2XDRF_BUF_WRITE              (uint8_t)(1 << 6)\n+#define MKW2XDRF_BUF_BYTE_READ          (uint8_t)(1 << 7 | 1 << 6 | 1 << 5)\n+#define MKW2XDRF_BUF_BYTE_WRITE         (uint8_t)(1 << 6 | 1 << 5)\n+\n+enum mkw2xdrf_dregister {\n+    MKW2XDM_IRQSTS1 = 0x0,              /* Interrupt Request Status 1 */\n+    MKW2XDM_IRQSTS2 = 0x1,              /* Interrupt Request Status 2 */\n+    MKW2XDM_IRQSTS3 = 0x2,              /* Interrupt Request Status 3 */\n+    MKW2XDM_PHY_CTRL1 = 0x3,            /* PHY Control 1 */\n+    MKW2XDM_PHY_CTRL2 = 0x4,            /* PHY Control 2 */\n+    MKW2XDM_PHY_CTRL3 = 0x5,            /* PHY Control 3 */\n+    MKW2XDM_RX_FRM_LEN = 0x6,           /* Receive Frame Length */\n+    MKW2XDM_PHY_CTRL4 = 0x7,            /* PHY Control 4 */\n+    MKW2XDM_SRC_CTRL = 0x8,             /* SRC Control */\n+    MKW2XDM_SRC_ADDRS_SUM_LSB = 0x9,    /* SRC Address SUM LSB */\n+    MKW2XDM_SRC_ADDRS_SUM_MSB = 0xa,    /* SRC Address SUM MSB */\n+    MKW2XDM_CCA1_ED_FNL = 0xb,          /* CCA1 ED FNL */\n+    MKW2XDM_EVENT_TIMER_LSB = 0xc,      /* Event Timer LSB */\n+    MKW2XDM_EVENT_TIMER_MSB = 0xd,      /* Event Timer MSB */\n+    MKW2XDM_EVENT_TIMER_USB = 0xe,      /* Event Timer USB */\n+    MKW2XDM_TIMESTAMP_LSB = 0xf,        /* Timestamp LSB */\n+    MKW2XDM_TIMESTAMP_MSB = 0x10,       /* Timestamp MSB */\n+    MKW2XDM_TIMESTAMP_USB = 0x11,       /* Timestamp USB */\n+    MKW2XDM_T3CMP_LSB = 0x12,           /* Timer 3 Compare Value LSB */\n+    MKW2XDM_T3CMP_MSB = 0x13,           /* Timer 3 Compare Value MSB */\n+    MKW2XDM_T3CMP_USB = 0x14,           /* Timer 3 Compare Value USB */\n+    MKW2XDM_T2PRIMECMP_LSB = 0x15,      /* Timer 2-Prime Compare Value LSB */\n+    MKW2XDM_T2PRIMECMP_MSB = 0x16,      /* Timer 2-Prime Compare Value MSB */\n+    MKW2XDM_T1CMP_LSB = 0x17,           /* Timer 1 Compare Value LSB */\n+    MKW2XDM_T1CMP_MSB = 0x18,           /* Timer 1 Compare Value MSB */\n+    MKW2XDM_T1CMP_USB = 0x19,           /* Timer 1 Compare Value USB */\n+    MKW2XDM_T2CMP_LSB = 0x1a,           /* Timer 2 Compare Value LSB */\n+    MKW2XDM_T2CMP_MSB = 0x1b,           /* Timer 2 Compare Value MSB */\n+    MKW2XDM_T2CMP_USB = 0x1c,           /* Timer 2 Compare Value USB */\n+    MKW2XDM_T4CMP_LSB = 0x1d,           /* Timer 4 Compare Value LSB */\n+    MKW2XDM_T4CMP_MSB = 0x1e,           /* Timer 4 Compare Value MSB */\n+    MKW2XDM_T4CMP_USB = 0x1f,           /* Timer 4 Compare Value USB */\n+    MKW2XDM_PLL_INT0 = 0x20,            /* PLL Integer Value for PAN0 */\n+    MKW2XDM_PLL_FRAC0_LSB = 0x21,       /* PLL Frequency Fractional Value for PAN0 */\n+    MKW2XDM_PLL_FRAC0_MSB = 0x22,       /* PLL Frequency Fractional Value for PAN0 */\n+    MKW2XDM_PA_PWR = 0x23,              /* PA Power Control (PA_PWR) */\n+    MKW2XDM_SEQ_STATE = 0x24,           /* Sequence Manager State */\n+    MKW2XDM_LQI_VALUE = 0x25,           /* Link Quality Indicator */\n+    MKW2XDM_RSSI_CCA_CNT = 0x26,        /* RSSI CCA CNT */\n+    MKW2XDM_OVERWRITE_VER = 0x3b,       /* Overwrite Version Number */\n+    MKW2XDM_CLK_OUT_CTRL = 0x3c,        /* CLK_OUT Control */\n+    MKW2XDM_PWR_MODES = 0x3d,           /* Power Modes */\n+    MKW2XDM_IAR_INDEX = 0x3e,           /* IAR Index */\n+    MKW2XDM_IAR_DATA = 0x3f,            /* IAR Data */\n+};\n+\n+#define MKW2XDM_IRQSTS1_RX_FRM_PEND                 (1 << 7)\n+#define MKW2XDM_IRQSTS1_PLL_UNLOCK_IRQ              (1 << 6)\n+#define MKW2XDM_IRQSTS1_FILTERFAIL_IRQ              (1 << 5)\n+#define MKW2XDM_IRQSTS1_RXWTRMRKIRQ                 (1 << 4)\n+#define MKW2XDM_IRQSTS1_CCAIRQ                      (1 << 3)\n+#define MKW2XDM_IRQSTS1_RXIRQ                       (1 << 2)\n+#define MKW2XDM_IRQSTS1_TXIRQ                       (1 << 1)\n+#define MKW2XDM_IRQSTS1_SEQIRQ                      (1 << 0)\n+\n+#define MKW2XDM_IRQSTS2_CRCVALID                    (1 << 7)\n+#define MKW2XDM_IRQSTS2_CCA                         (1 << 6)\n+#define MKW2XDM_IRQSTS2_SRCADDR                     (1 << 5)\n+#define MKW2XDM_IRQSTS2_PI                          (1 << 4)\n+#define MKW2XDM_IRQSTS2_TMRSTATUS                   (1 << 3)\n+#define MKW2XDM_IRQSTS2_PB_ERR_IRQ                  (1 << 1)\n+#define MKW2XDM_IRQSTS2_WAKE_IRQ                    (1 << 0)\n+\n+#define MKW2XDM_IRQSTS3_TMR4MSK                     (1 << 7)\n+#define MKW2XDM_IRQSTS3_TMR3MSK                     (1 << 6)\n+#define MKW2XDM_IRQSTS3_TMR2MSK                     (1 << 5)\n+#define MKW2XDM_IRQSTS3_TMR1MSK                     (1 << 4)\n+#define MKW2XDM_IRQSTS3_TMR4IRQ                     (1 << 3)\n+#define MKW2XDM_IRQSTS3_TMR3IRQ                     (1 << 2)\n+#define MKW2XDM_IRQSTS3_TMR2IRQ                     (1 << 1)\n+#define MKW2XDM_IRQSTS3_TMR1IRQ                     (1 << 0)\n+\n+#define MKW2XDM_PHY_CTRL1_TMRTRIGEN                 (1 << 7)\n+#define MKW2XDM_PHY_CTRL1_SLOTTED                   (1 << 6)\n+#define MKW2XDM_PHY_CTRL1_CCABFRTX                  (1 << 5)\n+#define MKW2XDM_PHY_CTRL1_RXACKRQD                  (1 << 4)\n+#define MKW2XDM_PHY_CTRL1_AUTOACK                   (1 << 3)\n+#define MKW2XDM_PHY_CTRL1_XCVSEQ_MASK               0x03u\n+#define MKW2XDM_PHY_CTRL1_XCVSEQ(x)                 (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PHY_CTRL1_XCVSEQ_MASK)\n+\n+#define MKW2XDM_PHY_CTRL2_CRC_MSK                   (1 << 7)\n+#define MKW2XDM_PHY_CTRL2_PLL_UNLOCK_MSK            (1 << 6)\n+#define MKW2XDM_PHY_CTRL2_FILTERFAIL_MSK            (1 << 5)\n+#define MKW2XDM_PHY_CTRL2_RX_WMRK_MSK               (1 << 4)\n+#define MKW2XDM_PHY_CTRL2_CCAMSK                    (1 << 3)\n+#define MKW2XDM_PHY_CTRL2_RXMSK                     (1 << 2)\n+#define MKW2XDM_PHY_CTRL2_TXMSK                     (1 << 1)\n+#define MKW2XDM_PHY_CTRL2_SEQMSK                    (1 << 0)\n+\n+#define MKW2XDM_PHY_CTRL3_TMR4CMP_EN                (1 << 7)\n+#define MKW2XDM_PHY_CTRL3_TMR3CMP_EN                (1 << 6)\n+#define MKW2XDM_PHY_CTRL3_TMR2CMP_EN                (1 << 5)\n+#define MKW2XDM_PHY_CTRL3_TMR1CMP_EN                (1 << 4)\n+#define MKW2XDM_PHY_CTRL3_PB_ERR_MSK                (1 << 1)\n+#define MKW2XDM_PHY_CTRL3_WAKE_MSK                  (1 << 0)\n+\n+#define MKW2XDM_RX_FRM_LENGTH_MASK                  0x7Fu\n+\n+#define MKW2XDM_PHY_CTRL4_TRCV_MSK                  (1 << 7)\n+#define MKW2XDM_PHY_CTRL4_TC3TMOUT                  (1 << 6)\n+#define MKW2XDM_PHY_CTRL4_PANCORDNTR0               (1 << 5)\n+#define MKW2XDM_PHY_CTRL4_CCATYPE_MASK              0x18u\n+#define MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT             3\n+#define MKW2XDM_PHY_CTRL4_CCATYPE(x)                (((uint8_t)(((uint8_t)(x))<<MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT))&MKW2XDM_PHY_CTRL4_CCATYPE_MASK)\n+#define MKW2XDM_PHY_CTRL4_TMRLOAD                   (1 << 2)\n+#define MKW2XDM_PHY_CTRL4_PROMISCUOUS               (1 << 1)\n+#define MKW2XDM_PHY_CTRL4_TC2PRIME_EN               (1 << 0)\n+\n+#define MKW2XDM_SRC_CTRL_INDEX_MASK                 0xF0u\n+#define MKW2XDM_SRC_CTRL_INDEX_SHIFT                4\n+#define MKW2XDM_SRC_CTRL_ACK_FRM_PND                (1 << 3)\n+#define MKW2XDM_SRC_CTRL_SRCADDR_EN                 (1 << 2)\n+#define MKW2XDM_SRC_CTRL_INDEX_EN                   (1 << 1)\n+#define MKW2XDM_SRC_CTRL_INDEX_DISABLE              (1 << 0)\n+\n+#define MKW2XDM_PLL_INT0_MASK                       0x1Fu\n+#define MKW2XDM_PLL_INT0_VAL(x)                     (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PLL_INT0_MASK)\n+\n+#define MKW2XDM_PA_PWR_MASK                         0x1Fu\n+#define MKW2XDM_PA_PWR(x)                           (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PA_PWR_MASK)\n+\n+#define MKW2XDM_CLK_OUT_EXTEND                      (1 << 7)\n+#define MKW2XDM_CLK_OUT_HIZ                         (1 << 6)\n+#define MKW2XDM_CLK_OUT_SR                          (1 << 5)\n+#define MKW2XDM_CLK_OUT_DS                          (1 << 4)\n+#define MKW2XDM_CLK_OUT_EN                          (1 << 3)\n+#define MKW2XDM_CLK_OUT_DIV_MASK                    0x03u\n+#define MKW2XDM_CLK_OUT_DIV(x)                      (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_CLK_OUT_DIV_MASK)\n+\n+#define MKW2XDM_PWR_MODES_XTAL_READY                (1 << 5)\n+#define MKW2XDM_PWR_MODES_XTALEN                    (1 << 4)\n+#define MKW2XDM_PWR_MODES_AUTODOZE                  (1 << 1)\n+#define MKW2XDM_PWR_MODES_PMC_MODE                  (1 << 0)\n+\n+enum mkw2xdrf_iregister {\n+    MKW2XDMI_PART_ID = 0x00,\t\t /* Part Identification */\n+    MKW2XDMI_XTAL_TRIM = 0x01,\t\t /* XTAL 32 MHz Trim */\n+    MKW2XDMI_MACPANID0_LSB = 0x03,\t /* MAC PAN ID for PAN0 */\n+    MKW2XDMI_MACPANID0_MSB = 0x04,\t /* MAC PAN ID for PAN0 */\n+    MKW2XDMI_MACSHORTADDRS0_LSB = 0x05,\t /* MAC Short Address for PAN0 */\n+    MKW2XDMI_MACSHORTADDRS0_MSB = 0x06,\t /* MAC Short Address for PAN0 */\n+    MKW2XDMI_MACLONGADDRS0_0 = 0x07,\t /* MAC Long Address for PAN0 */\n+    MKW2XDMI_MACLONGADDRS0_1 = 0x08,\t /* MAC Long Address for PAN0 */\n+    MKW2XDMI_MACLONGADDRS0_2 = 0x09,\t /* MAC Long Address for PAN0 */\n+    MKW2XDMI_MACLONGADDRS0_3 = 0x0a,\t /* MAC Long Address for PAN0 */\n+    MKW2XDMI_MACLONGADDRS0_4 = 0x0b,\t /* MAC Long Address for PAN0 */\n+    MKW2XDMI_MACLONGADDRS0_5 = 0x0c,\t /* MAC Long Address for PAN0 */\n+    MKW2XDMI_MACLONGADDRS0_6 = 0x0d,\t /* MAC Long Address for PAN0 */\n+    MKW2XDMI_MACLONGADDRS0_7 = 0x0e,\t /* MAC Long Address for PAN0 */\n+    MKW2XDMI_RX_FRAME_FILTER = 0x0f,\t /* Receive Frame Filter */\n+    MKW2XDMI_PLL_INT1 = 0x10,\t\t /* Frequency Integer for PAN1 */\n+    MKW2XDMI_PLL_FRAC1_LSB = 0x11,\t /* Frequency Fractional Value for PAN1 */\n+    MKW2XDMI_PLL_FRAC1_MSB = 0x12,\t /* Frequency Fractional Value for PAN1 */\n+    MKW2XDMI_MACPANID1_LSB = 0x13,\t /* Frequency Fractional Value for PAN1 */\n+    MKW2XDMI_MACPANID1_MSB = 0x14,\t /* Frequency Fractional Value for PAN1 */\n+    MKW2XDMI_MACSHORTADDRS1_LSB = 0x15,\t /* MAC Short Address for PAN1 */\n+    MKW2XDMI_MACSHORTADDRS1_MSB = 0x16,\t /* MAC Short Address for PAN1 */\n+    MKW2XDMI_MACLONGADDRS1_0 = 0x17,\t /* MAC Long Address for PAN1 */\n+    MKW2XDMI_MACLONGADDRS1_1 = 0x18,\t /* MAC Long Address for PAN1 */\n+    MKW2XDMI_MACLONGADDRS1_2 = 0x19,\t /* MAC Long Address for PAN1 */\n+    MKW2XDMI_MACLONGADDRS1_3 = 0x1a,\t /* MAC Long Address for PAN1 */\n+    MKW2XDMI_MACLONGADDRS1_4 = 0x1b,\t /* MAC Long Address for PAN1 */\n+    MKW2XDMI_MACLONGADDRS1_5 = 0x1c,\t /* MAC Long Address for PAN1 */\n+    MKW2XDMI_MACLONGADDRS1_6 = 0x1d,\t /* MAC Long Address for PAN1 */\n+    MKW2XDMI_MACLONGADDRS1_7 = 0x1e,\t /* MAC Long Address for PAN1 */\n+    MKW2XDMI_DUAL_PAN_CTRL = 0x1f,\t /* Dual PAN Control */\n+    MKW2XDMI_DUAL_PAN_DWELL = 0x20,\t /* Channel Frequency Dwell Time */\n+    MKW2XDMI_DUAL_PAN_STS = 0x21,\t /* Dual PAN Status */\n+    MKW2XDMI_CCA1_THRESH = 0x22,\t /* Clear Channel Assessment 1 Threshold */\n+    MKW2XDMI_CCA1_ED_OFFSET_COMP = 0x23, /* Clear Channel Assessment / ED Offset Computation */\n+    MKW2XDMI_LQI_OFFSET_COMP = 0x24,\t /* LQI Offset Computation */\n+    MKW2XDMI_CCA_CTRL = 0x25,\t\t /* CCA Control */\n+    MKW2XDMI_CCA2_CORR_PEAKS = 0x26,\t /* Clear Channel Assessment 2 Threshold Peak Compare */\n+    MKW2XDMI_CCA2_THRESH = 0x27,\t /* Clear Channel Assessment 2 Threshold */\n+    MKW2XDMI_GPIO_DATA = 0x2a,\t\t /* GPIO Data */\n+    MKW2XDMI_GPIO_DIR = 0x2b,\t\t /* GPIO Direction Control */\n+    MKW2XDMI_GPIO_PUL_EN = 0x2c,\t /* GPIO Pullup Enable */\n+    MKW2XDMI_GPIO_SEL = 0x2d,\t\t /* GPIO Pullup Select */\n+    MKW2XDMI_GPIO_DS = 0x2e,\t\t /* GPIO Drive Strength */\n+    MKW2XDMI_ANT_PAD_CTRL = 0x30,\t /* Antenna Control */\n+    MKW2XDMI_MISC_PAD_CTRL = 0x31,\t /* Miscellaneous Pad Control */\n+    MKW2XDMI_ANT_AGC_CTRL = 0x51,\t /* Antenna AGC and FAD Control */\n+    MKW2XDMI_LPPS_CTRL = 0x56,\t\t /* LPPS_CTRL */\n+};\n+\n+#define MKW2XDMI_PART_ID_MANUF_ID_MASK\t\t\t0x60u\n+#define MKW2XDMI_PART_ID_VERSION_MASK\t\t\t0x1Cu\n+#define MKW2XDMI_PART_ID_MASK_SET_MASK\t\t\t0x07u\n+\n+#define MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK\t\t0xC0u\n+#define MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT\t\t6\n+#define MKW2XDMI_RX_FRAME_FILTER_FRM_VER(x)             (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT))&MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK)\n+#define MKW2XDMI_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS\t(1 << 5)\n+#define MKW2XDMI_RX_FRAME_FILTER_NS_FT\t\t\t(1 << 4)\n+#define MKW2XDMI_RX_FRAME_FILTER_CMD_FT\t\t\t(1 << 3)\n+#define MKW2XDMI_RX_FRAME_FILTER_ACK_FT\t\t\t(1 << 2)\n+#define MKW2XDMI_RX_FRAME_FILTER_DATA_FT\t\t(1 << 1)\n+#define MKW2XDMI_RX_FRAME_FILTER_BEACON_FT\t\t(1 << 0)\n+\n+#define MKW2XDMI_PLL_INT1_MASK\t\t\t\t0x1Fu\n+\n+#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK\t0xF0\n+#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT\t4\n+#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL(x)      (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT))&MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK)\n+#define MKW2XDMI_DUAL_PAN_CTRL_CURRENT_NETWORK\t\t(1 << 3)\n+#define MKW2XDMI_DUAL_PAN_CTRL_PANCORDNTR1\t\t(1 << 2)\n+#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_AUTO\t\t(1 << 1)\n+#define MKW2XDMI_DUAL_PAN_CTRL_ACTIVE_NETWORK\t\t(1 << 0)\n+\n+#define MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN1\t\t(1 << 7)\n+#define MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN0\t\t(1 << 6)\n+#define MKW2XDMI_DUAL_PAN_STS_DUAL_PAN_REMAIN_MASK      0x3Fu\n+\n+#define MKW2XDMI_CCA_CTRL_AGC_FRZ_EN\t\t\t(1 << 6)\n+#define MKW2XDMI_CCA_CTRL_CONT_RSSI_EN\t\t\t(1 << 5)\n+#define MKW2XDMI_CCA_CTRL_QI_RSSI_NOT_CORR\t\t(1 << 4)\n+#define MKW2XDMI_CCA_CTRL_CCA3_AND_NOT_OR\t\t(1 << 3)\n+#define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_LQI\t\t(1 << 2)\n+#define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_ED\t\t(1 << 1)\n+#define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_CCA1\t\t(1 << 0)\n+\n+#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK\t0x70u\n+#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT\t4\n+#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH(x)\t(((uint8_t)(((uint8_t)(x))<<MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT))&MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK)\n+#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_NUM_CORR_PEAKS_MASK\t0x0Fu\n+\n+#define MKW2XDMI_GPIO_DATA8\t\t\t\t(1 << 7)\n+#define MKW2XDMI_GPIO_DATA7\t\t\t\t(1 << 6)\n+#define MKW2XDMI_GPIO_DATA6\t\t\t\t(1 << 5)\n+#define MKW2XDMI_GPIO_DATA5\t\t\t\t(1 << 4)\n+#define MKW2XDMI_GPIO_DATA4\t\t\t\t(1 << 3)\n+#define MKW2XDMI_GPIO_DATA3\t\t\t\t(1 << 2)\n+#define MKW2XDMI_GPIO_DATA2\t\t\t\t(1 << 1)\n+#define MKW2XDMI_GPIO_DATA1\t\t\t\t(1 << 0)\n+\n+#define MKW2XDMI_GPIO_DIR8\t\t\t\t(1 << 7)\n+#define MKW2XDMI_GPIO_DIR7\t\t\t\t(1 << 6)\n+#define MKW2XDMI_GPIO_DIR6\t\t\t\t(1 << 5)\n+#define MKW2XDMI_GPIO_DIR5\t\t\t\t(1 << 4)\n+#define MKW2XDMI_GPIO_DIR4\t\t\t\t(1 << 3)\n+#define MKW2XDMI_GPIO_DIR3\t\t\t\t(1 << 2)\n+#define MKW2XDMI_GPIO_DIR2\t\t\t\t(1 << 1)\n+#define MKW2XDMI_GPIO_DIR1\t\t\t\t(1 << 0)\n+\n+#define MKW2XDMI_GPIO_PUL_EN8\t\t\t\t(1 << 7)\n+#define MKW2XDMI_GPIO_PUL_EN7\t\t\t\t(1 << 6)\n+#define MKW2XDMI_GPIO_PUL_EN6\t\t\t\t(1 << 5)\n+#define MKW2XDMI_GPIO_PUL_EN5\t\t\t\t(1 << 4)\n+#define MKW2XDMI_GPIO_PUL_EN4\t\t\t\t(1 << 3)\n+#define MKW2XDMI_GPIO_PUL_EN3\t\t\t\t(1 << 2)\n+#define MKW2XDMI_GPIO_PUL_EN2\t\t\t\t(1 << 1)\n+#define MKW2XDMI_GPIO_PUL_EN1\t\t\t\t(1 << 0)\n+\n+#define MKW2XDMI_GPIO_PUL_SEL8\t\t\t\t(1 << 7)\n+#define MKW2XDMI_GPIO_PUL_SEL7\t\t\t\t(1 << 6)\n+#define MKW2XDMI_GPIO_PUL_SEL6\t\t\t\t(1 << 5)\n+#define MKW2XDMI_GPIO_PUL_SEL5\t\t\t\t(1 << 4)\n+#define MKW2XDMI_GPIO_PUL_SEL4\t\t\t\t(1 << 3)\n+#define MKW2XDMI_GPIO_PUL_SEL3\t\t\t\t(1 << 2)\n+#define MKW2XDMI_GPIO_PUL_SEL2\t\t\t\t(1 << 1)\n+#define MKW2XDMI_GPIO_PUL_SEL1\t\t\t\t(1 << 0)\n+\n+#define MKW2XDMI_GPIO_DS8\t\t\t\t(1 << 7)\n+#define MKW2XDMI_GPIO_DS7\t\t\t\t(1 << 6)\n+#define MKW2XDMI_GPIO_DS6\t\t\t\t(1 << 5)\n+#define MKW2XDMI_GPIO_DS5\t\t\t\t(1 << 4)\n+#define MKW2XDMI_GPIO_DS4\t\t\t\t(1 << 3)\n+#define MKW2XDMI_GPIO_DS3\t\t\t\t(1 << 2)\n+#define MKW2XDMI_GPIO_DS2\t\t\t\t(1 << 1)\n+#define MKW2XDMI_GPIO_DS1\t\t\t\t(1 << 0)\n+\n+#define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL3\t\t\t(1 << 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