{"action":"created","issue":{"url":"https://api.github.com/repos/open-ephys/GUI/issues/320","labels_url":"https://api.github.com/repos/open-ephys/GUI/issues/320/labels{/name}","comments_url":"https://api.github.com/repos/open-ephys/GUI/issues/320/comments","events_url":"https://api.github.com/repos/open-ephys/GUI/issues/320/events","html_url":"https://github.com/open-ephys/GUI/issues/320","id":117914949,"number":320,"title":"USB3 impedance/spike sorter error","user":{"login":"nikolaskaralis","id":4306518,"avatar_url":"https://avatars.githubusercontent.com/u/4306518?v=3","gravatar_id":"","url":"https://api.github.com/users/nikolaskaralis","html_url":"https://github.com/nikolaskaralis","followers_url":"https://api.github.com/users/nikolaskaralis/followers","following_url":"https://api.github.com/users/nikolaskaralis/following{/other_user}","gists_url":"https://api.github.com/users/nikolaskaralis/gists{/gist_id}","starred_url":"https://api.github.com/users/nikolaskaralis/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/nikolaskaralis/subscriptions","organizations_url":"https://api.github.com/users/nikolaskaralis/orgs","repos_url":"https://api.github.com/users/nikolaskaralis/repos","events_url":"https://api.github.com/users/nikolaskaralis/events{/privacy}","received_events_url":"https://api.github.com/users/nikolaskaralis/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":6,"created_at":"2015-11-19T21:47:35Z","updated_at":"2015-11-24T15:56:03Z","closed_at":null,"body":"Using the USB3 FPGA on Linux, I can record normally.\r\nHowever, trying to measure impedance, I get in the console: \r\n\"Error in RHD2000EvalBoard\"\r\nfor each channel, and then some crazy values as impedance (on the GUI).\r\nAlso trying to use Spike Sorter (with usb3) crashes the GUI.\r\n\r\nOn a perhaps related note: While recording with USB3 FPGA on Linux works fine (except of the above), on Windows (on the same computer, dual boot) the headstages are not even recognized.\r\nUSB2 board works for both systems.\r\n \r\nIs anybody working with the USB3 board?\r\n\r\nCheers,\r\nNikolas\r\n"},"comment":{"url":"https://api.github.com/repos/open-ephys/GUI/issues/comments/159312047","html_url":"https://github.com/open-ephys/GUI/issues/320#issuecomment-159312047","issue_url":"https://api.github.com/repos/open-ephys/GUI/issues/320","id":159312047,"user":{"login":"jvoigts","id":1414052,"avatar_url":"https://avatars.githubusercontent.com/u/1414052?v=3","gravatar_id":"","url":"https://api.github.com/users/jvoigts","html_url":"https://github.com/jvoigts","followers_url":"https://api.github.com/users/jvoigts/followers","following_url":"https://api.github.com/users/jvoigts/following{/other_user}","gists_url":"https://api.github.com/users/jvoigts/gists{/gist_id}","starred_url":"https://api.github.com/users/jvoigts/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jvoigts/subscriptions","organizations_url":"https://api.github.com/users/jvoigts/orgs","repos_url":"https://api.github.com/users/jvoigts/repos","events_url":"https://api.github.com/users/jvoigts/events{/privacy}","received_events_url":"https://api.github.com/users/jvoigts/received_events","type":"User","site_admin":false},"created_at":"2015-11-24T15:56:03Z","updated_at":"2015-11-24T15:56:03Z","body":"1) I saw a new .bit file. I assume there is new verilog code? Where is that stored in the repository?\r\n\r\nshould be https://github.com/open-ephys/rhythm/tree/usb3\r\n\r\nAaron had to make a lot of fairly deep changes, i dont know if there's a list/documentation of this somewhere already. If not it might be useful to do that at some point, similar to https://open-ephys.atlassian.net/wiki/display/OEW/Rhythm+firmware+fork\r\n\r\n2) You said that existing break out boards can still be used, and only the FPGA needs to be replaced, is that correct?\r\n\r\nyea, the I/O boards are the same you just swap out the usb3 fpga board\r\n\r\n3) How can one connect four 32ch amplifier to one port? Is there existing PCB/cabling solution for this?\r\n\r\nYou can only connect two RHD headstages per port, using a Y-adapter, because there's only 2 miso pairs per connector. This gives you 8 RHD chips total, for up to 512 channels (with 64 ch chips). \r\n\r\nWe have a few free pins left on the fpga that we pulled out to a .1\" header for future expansions so with a few cmos<>lvds bridges (because we dont have enough pins for straight lvds - and this is assuming that the bandwidth of these is not destroyed by the board layout etc) we can theoretically throw in a 2nd row of 4 ports, which would get us to 1024 chs per board.  Of course this would require some firmware, api, and GUI updates, and i'm not 100% sure how close this would come to saturating the usb3, though it should fit in theory ( http://www.wolframalpha.com/input/?i=2+byte+*+30kHz+*+1024+*+2+in+MB%2Fs ).\r\n\r\nI started putting together an extension board in the https://github.com/open-ephys/acquisition-board repository, if someone is up for some firmware coding this could be a fun project."}}