{"push_id":569881534,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"428e6b5600fb6ed3ea62654f5c096d5003821f25","before":"b62e80f556f96a011ab8d45b3ed385b40f8d1b30","commits":[{"sha":"428e6b5600fb6ed3ea62654f5c096d5003821f25","author":{"email":"8eec7bc461808e0b8a28783d0bec1a3a22eb0821@techno.ms","name":"HrRossi"},"message":"AMS: bugfix ADC reads all 0 after GPIO write\n\nAdded a clock bridge module to the sysbus connection to properly synchronize\nregister accesses to the adc_clk domain from the sys_clk domain. This avoids\na malfunction in the ADC sample registers which made them read constant 0.","distinct":true,"url":"https://api.github.com/repos/RedPitaya/RedPitaya/commits/428e6b5600fb6ed3ea62654f5c096d5003821f25"}]}