{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/chisel/issues/627","labels_url":"https://api.github.com/repos/ucb-bar/chisel/issues/627/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/chisel/issues/627/comments","events_url":"https://api.github.com/repos/ucb-bar/chisel/issues/627/events","html_url":"https://github.com/ucb-bar/chisel/issues/627","id":122888192,"number":627,"title":"wave form for registers is (still) off by one clock tick","user":{"login":"schoeberl","id":650648,"avatar_url":"https://avatars.githubusercontent.com/u/650648?v=3","gravatar_id":"","url":"https://api.github.com/users/schoeberl","html_url":"https://github.com/schoeberl","followers_url":"https://api.github.com/users/schoeberl/followers","following_url":"https://api.github.com/users/schoeberl/following{/other_user}","gists_url":"https://api.github.com/users/schoeberl/gists{/gist_id}","starred_url":"https://api.github.com/users/schoeberl/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/schoeberl/subscriptions","organizations_url":"https://api.github.com/users/schoeberl/orgs","repos_url":"https://api.github.com/users/schoeberl/repos","events_url":"https://api.github.com/users/schoeberl/events{/privacy}","received_events_url":"https://api.github.com/users/schoeberl/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":3,"created_at":"2015-12-18T06:26:22Z","updated_at":"2015-12-18T19:33:50Z","closed_at":null,"body":"Dear all,\r\n\r\nI am a little bit confused about the wave forms generated for registers. I thought this off by one issue has been solved some time ago. However, as I see it today the wave form still is off by one for registers - or in other words displays the input signal of a register instead of the output value. In standard VHDL/Verilog simulation the register signal is the output signal (i.e., one cycle later). Please, please: this needs to be fixed! Otherwise the acceptance of Chisel by EE engineers, who like to look at wave forms, will drop very, very fast.\r\n\r\nFor a small example you can look at:\r\n\r\nhttps://github.com/schoeberl/chisel-examples/blob/master/examples/src/BubbleFifo.scala\r\n\r\nYou can run this by checking out the repository and execute within the folder examples:\r\n\r\nmake fifo-test\r\ngtkwave generated/BubbleFifo.vcd\r\n\r\nYou will see that io_dout, which is connected to the output of dataReg, is one cycle later than dataReg.\r\n\r\nCheers,\r\nMartin"},"comment":{"url":"https://api.github.com/repos/ucb-bar/chisel/issues/comments/165878331","html_url":"https://github.com/ucb-bar/chisel/issues/627#issuecomment-165878331","issue_url":"https://api.github.com/repos/ucb-bar/chisel/issues/627","id":165878331,"user":{"login":"ucbjrl","id":6845888,"avatar_url":"https://avatars.githubusercontent.com/u/6845888?v=3","gravatar_id":"","url":"https://api.github.com/users/ucbjrl","html_url":"https://github.com/ucbjrl","followers_url":"https://api.github.com/users/ucbjrl/followers","following_url":"https://api.github.com/users/ucbjrl/following{/other_user}","gists_url":"https://api.github.com/users/ucbjrl/gists{/gist_id}","starred_url":"https://api.github.com/users/ucbjrl/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ucbjrl/subscriptions","organizations_url":"https://api.github.com/users/ucbjrl/orgs","repos_url":"https://api.github.com/users/ucbjrl/repos","events_url":"https://api.github.com/users/ucbjrl/events{/privacy}","received_events_url":"https://api.github.com/users/ucbjrl/received_events","type":"User","site_admin":false},"created_at":"2015-12-18T19:33:50Z","updated_at":"2015-12-18T19:33:50Z","body":"On Dec 18, 2015, at 11:22 AM, Martin Schoeberl <notifications@github.com> wrote:\n\n> \n> > On 18 Dec, 2015, at 5:03, rndfax <notifications@github.com> wrote:\n> > \n> > Can you verify that without #614 you are getting right results?\n> > \n> > �\n> > Reply to this email directly or view it on GitHub.\n> \n> I checked with the latest version of Chisel cloned from GitHub and there it is ok.\n> So this can be closed. Sorry for the noise generated.\n> \n> I did see the issue when I build my project against �latest.release�.\n> Will there be a release soon that includes the fix?\n> \n> Cheers,\n> Martin\n> \n\nI�m planning on generating a release next Wednesday (which will include the fix).\n\n"}}