{"action":"created","issue":{"url":"https://api.github.com/repos/jandecaluwe/myhdl/issues/98","labels_url":"https://api.github.com/repos/jandecaluwe/myhdl/issues/98/labels{/name}","comments_url":"https://api.github.com/repos/jandecaluwe/myhdl/issues/98/comments","events_url":"https://api.github.com/repos/jandecaluwe/myhdl/issues/98/events","html_url":"https://github.com/jandecaluwe/myhdl/issues/98","id":94160254,"number":98,"title":"TristateSignal Conversion Error and Verilog missing inout","user":{"login":"cfelton","id":766391,"avatar_url":"https://avatars.githubusercontent.com/u/766391?v=3","gravatar_id":"","url":"https://api.github.com/users/cfelton","html_url":"https://github.com/cfelton","followers_url":"https://api.github.com/users/cfelton/followers","following_url":"https://api.github.com/users/cfelton/following{/other_user}","gists_url":"https://api.github.com/users/cfelton/gists{/gist_id}","starred_url":"https://api.github.com/users/cfelton/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/cfelton/subscriptions","organizations_url":"https://api.github.com/users/cfelton/orgs","repos_url":"https://api.github.com/users/cfelton/repos","events_url":"https://api.github.com/users/cfelton/events{/privacy}","received_events_url":"https://api.github.com/users/cfelton/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":2,"created_at":"2015-07-09T21:53:45Z","updated_at":"2015-07-11T11:41:10Z","closed_at":null,"body":"When `TristateSignal`s are used as top-level ports the signal is not converted to an `inout` when the target is Verilog.  This appears to work in VHDL but not in Verilog. \r\n\r\nIn addition PR #74 appeared to break [code that use to convert](https://gist.github.com/cfelton/6119313).  I used `bisect` to verify the revision where the code stopped converting f965132.\r\n\r\nFailing code snip:\r\n```python\r\ndef top(sda, scl, sda_i, sda_o, scl_i, scl_o):\r\n     sda_d, scl_d = sda.driver(), scl.driver()\r\n     @always_comb\r\n     def hdl():\r\n         sda_i.next = sda\r\n         sda_d.next = False if not sda_o else None \r\n         scl_i.next = scl\r\n         scl_d.next = False if not scl_o else None\r\n     return hdl\r\n```\r\n\r\nIt is not clear (at this point) why the conversion is failing.  The conversion for the code snip only fails for VHDL conversion.\r\n"},"comment":{"url":"https://api.github.com/repos/jandecaluwe/myhdl/issues/comments/120606844","html_url":"https://github.com/jandecaluwe/myhdl/issues/98#issuecomment-120606844","issue_url":"https://api.github.com/repos/jandecaluwe/myhdl/issues/98","id":120606844,"user":{"login":"josyb","id":4457022,"avatar_url":"https://avatars.githubusercontent.com/u/4457022?v=3","gravatar_id":"","url":"https://api.github.com/users/josyb","html_url":"https://github.com/josyb","followers_url":"https://api.github.com/users/josyb/followers","following_url":"https://api.github.com/users/josyb/following{/other_user}","gists_url":"https://api.github.com/users/josyb/gists{/gist_id}","starred_url":"https://api.github.com/users/josyb/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/josyb/subscriptions","organizations_url":"https://api.github.com/users/josyb/orgs","repos_url":"https://api.github.com/users/josyb/repos","events_url":"https://api.github.com/users/josyb/events{/privacy}","received_events_url":"https://api.github.com/users/josyb/received_events","type":"User","site_admin":false},"created_at":"2015-07-11T11:41:10Z","updated_at":"2015-07-11T11:41:10Z","body":"It looks like the AST traversal errs:\r\nThis construct breaks at encountering the 'None' \r\n```python\r\nsda_d.next = False if not sda_o else None\r\n```\r\n```text\r\nline: sda_d <= '0' when (not bool(sda_o)) else stdl( \r\n```\r\nand if we swap places:\r\n```python\r\nsda_d.next = None if sda_o else 0\r\n```\r\n```text\r\nline: sda_d <= stdl(\r\n```\r\nNote that here the 'stdl(' is wrong too, as the expected first object in  the eventual ' a when b else c' statement is a 'Z'.\r\n#74 corrected (tried to) the invalid (others => 'Z') when the RHS had a width of 1 (bool or intbv[1:]). If we have an ternary construct, this width information is missing."}}