{"push_id":646974334,"size":3,"distinct_size":3,"ref":"refs/heads/master","head":"18d5a56d258af85dbaba5b6835dd8bdb562e6b69","before":"5d9d77a9e1e13e00771b1fc03d83cd88235a62f4","commits":[{"sha":"8dd91f3859359233d6dcf665bb5afcb131619cd5","author":{"email":"5fc48893deb452dfa8536f87a3ec37910dfa0cce@intel.com","name":"Weiliang Lin"},"message":"[SIMD.js] Optimize SIMD128 operations by TurboFan\n\nThe implementation is only for ia32 and x64 ports.\n\nOverall we have enabled 114 stable and core SIMD128 APIs (same as Crankshaft)\nfor three vector types (float32x4, int32x4 and float64x2) in TurboFan.\nPerformance speedup is expected(2x~9x) for several simd.js benchmarks.\n\nDesgin background:\n1. Introduce the types of float32x4, int32x4 and float64x2 to TurboFan's type\nsystem.\n2. Introduce opcode for both Node(TurboFan's HIR) and Instruction\n(TurboFan's LIR) for each SIMD128 API.\n3. For efficiency, all SIMD128 APIs are regarded as builtin functions and will be\ninlined in the phase of JS typed lowering of TurboFan's pipeline.\n4. For register allocation, we also need to introduce register types for\nfloat32x4, int32x4 and float64x2 and guarantee to use xmm register and move to a\n16-bytes stack slot if spilled.\n\nTODOs\n1. To support TurboFan OSR.\n2. To support TurboFan deoptimization.\n\nConflicts:\n\n\tsrc/compiler/ast-graph-builder.h\n\tsrc/compiler/code-generator-impl.h\n\tsrc/compiler/frame.h\n\tsrc/compiler/graph-visualizer.cc\n\tsrc/compiler/ia32/code-generator-ia32.cc\n\tsrc/compiler/ia32/instruction-selector-ia32.cc\n\tsrc/compiler/instruction-codes.h\n\tsrc/compiler/instruction-selector.cc\n\tsrc/compiler/instruction.h\n\tsrc/compiler/js-builtin-reducer.cc\n\tsrc/compiler/js-builtin-reducer.h\n\tsrc/compiler/js-typed-lowering.cc\n\tsrc/compiler/machine-operator.cc\n\tsrc/compiler/machine-operator.h\n\tsrc/compiler/opcodes.h\n\tsrc/compiler/register-allocator.cc\n\tsrc/compiler/register-allocator.h\n\tsrc/compiler/simplified-lowering.cc\n\tsrc/compiler/simplified-operator.cc\n\tsrc/compiler/x64/code-generator-x64.cc\n\tsrc/compiler/x64/instruction-selector-x64.cc\n\tsrc/isolate.cc\n\tsrc/objects.cc\n\nBUG=XWALK-3409","distinct":true,"url":"https://api.github.com/repos/crosswalk-project/v8-crosswalk/commits/8dd91f3859359233d6dcf665bb5afcb131619cd5"},{"sha":"d32b18a3945a6392ba04513e3b1f21155abbc827","author":{"email":"24faaec16a11fe2c0ded74a635139616d55770bc@intel.com","name":"Ningxin Hu"},"message":"[SIMD.js] Fix build failures of TurboFan SIMD on non-IA archs","distinct":true,"url":"https://api.github.com/repos/crosswalk-project/v8-crosswalk/commits/d32b18a3945a6392ba04513e3b1f21155abbc827"},{"sha":"18d5a56d258af85dbaba5b6835dd8bdb562e6b69","author":{"email":"24faaec16a11fe2c0ded74a635139616d55770bc@intel.com","name":"Ningxin Hu"},"message":"Merge pull request #102 from huningxin/simd-m43-turbofan\n\n[SIMD.js] Optimize SIMD128 operations by TurboFan","distinct":true,"url":"https://api.github.com/repos/crosswalk-project/v8-crosswalk/commits/18d5a56d258af85dbaba5b6835dd8bdb562e6b69"}]}