{"push_id":892245522,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"38208ce21efd59bbcb2d0ce57ef3a1b95775f911","before":"d8a0ef0be23594345421d3b12242bfc14020a3e0","commits":[{"sha":"73af5783cf2a4023f5b51e71ae37dc1ac1e655fa","author":{"email":"597976738c4e7247404f28c510dfed7fe9762040@6c8e4198-a580-4521-a02f-c9ae86df1db9","name":"vruppert"},"message":"Started implementing USB EHCI support. The PCI and MMIO register behaviour is\nalmost implemented, the port owner handling and the UHCI companion controllers\nare present. High speed devices are not yet supported, since the EHCI scheduler\ncode has not been written yet (e.g. porting from Qemu). Low and full speed\ndevices should be detected correctly and work after port ownership change to\nUHCI. 6 ports are available and the bochsrc syntax is similar to other HCs.\n\n\ngit-svn-id: http://svn.code.sf.net/p/bochs/code/trunk@12885 6c8e4198-a580-4521-a02f-c9ae86df1db9","distinct":true,"url":"https://api.github.com/repos/svn2github/bochs/commits/73af5783cf2a4023f5b51e71ae37dc1ac1e655fa"},{"sha":"38208ce21efd59bbcb2d0ce57ef3a1b95775f911","author":{"email":"597976738c4e7247404f28c510dfed7fe9762040@6c8e4198-a580-4521-a02f-c9ae86df1db9","name":"vruppert"},"message":"Started implementing USB EHCI support. The PCI and MMIO register behaviour is\nalmost implemented, the port owner handling and the UHCI companion controllers\nare present. High speed devices are not yet supported, since the EHCI scheduler\ncode has not been written yet (e.g. porting from Qemu). Low and full speed\ndevices should be detected correctly and work after port ownership change to\nUHCI. 6 ports are available and the bochsrc syntax is similar to other HCs.\n\n\ngit-svn-id: http://svn.code.sf.net/p/bochs/code/trunk@12886 6c8e4198-a580-4521-a02f-c9ae86df1db9","distinct":true,"url":"https://api.github.com/repos/svn2github/bochs/commits/38208ce21efd59bbcb2d0ce57ef3a1b95775f911"}]}