{"push_id":718099843,"size":8,"distinct_size":8,"ref":"refs/heads/staging","head":"9a566a83d6374e7425bcb330e03c8ca9b31a0d0b","before":"0c0cbf72cf9f28070cc5d49955b0a00df5c1d114","commits":[{"sha":"4824bdfdabebd4042277461cb3cbefa61c624804","author":{"email":"3a1de429413b8a337d3d0a9d72c52f6d44ea541c@linux.intel.com","name":"Chao Peng"},"message":"x86: add socket_cpumask\n\nMaintain socket_cpumask which contains all the HT and core siblings\nin the same socket.\n\nSigned-off-by: Chao Peng <chao.p.peng@linux.intel.com>\nAcked-by: Jan Beulich <jbeulich@suse.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/4824bdfdabebd4042277461cb3cbefa61c624804"},{"sha":"65a399acae1ae3065346f93717443676564bb2e5","author":{"email":"3a1de429413b8a337d3d0a9d72c52f6d44ea541c@linux.intel.com","name":"Chao Peng"},"message":"x86: detect and initialize Intel CAT feature\n\nDetect Intel Cache Allocation Technology(CAT) feature and store the\ncpuid information for later use. Currently only L3 cache allocation is\nsupported. The L3 CAT features may vary among sockets so per-socket\nfeature information is stored. The initialization can happen either at\nboot time or when CPU(s) is hot plugged after booting.\n\nSigned-off-by: Chao Peng <chao.p.peng@linux.intel.com>\n\nUse -1 as notifier priority. Fix typos.\n\nSigned-off-by: Jan Beulich <jbeulich@suse.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/65a399acae1ae3065346f93717443676564bb2e5"},{"sha":"39a24082b81c5eefbdcf98b4f78b96685664d56e","author":{"email":"3a1de429413b8a337d3d0a9d72c52f6d44ea541c@linux.intel.com","name":"Chao Peng"},"message":"x86: maintain COS to CBM mapping for each socket\n\nFor each socket, a COS to CBM mapping structure is maintained for each\nCOS. The mapping is indexed by COS and the value is the corresponding\nCBM. Different VMs may use the same CBM, a reference count is used to\nindicate if the CBM is available.\n\nSigned-off-by: Chao Peng <chao.p.peng@linux.intel.com>\nReviewed-by: Jan Beulich <jbeulich@suse.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/39a24082b81c5eefbdcf98b4f78b96685664d56e"},{"sha":"4bc9843a83c10baa8d908d214185d2ee6d422dab","author":{"email":"3a1de429413b8a337d3d0a9d72c52f6d44ea541c@linux.intel.com","name":"Chao Peng"},"message":"x86: add COS information for each domain\n\nIn Xen's implementation, the CAT enforcement granularity is per domain.\nDue to the length of CBM and the number of COS may be socket-different,\neach domain has COS ID for each socket. The domain get COS=0 by default\nand at runtime its COS is then allocated dynamically when user specifies\na CBM for the domain.\n\nSigned-off-by: Chao Peng <chao.p.peng@linux.intel.com>\nReviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/4bc9843a83c10baa8d908d214185d2ee6d422dab"},{"sha":"46af95231c9fa9db3363675dd15f7a42baf351c5","author":{"email":"3a1de429413b8a337d3d0a9d72c52f6d44ea541c@linux.intel.com","name":"Chao Peng"},"message":"x86: expose CBM length and COS number information\n\nGeneral CAT information such as maximum COS and CBM length are exposed to\nuser space by a SYSCTL hypercall, to help user space to construct the CBM.\n\nSigned-off-by: Chao Peng <chao.p.peng@linux.intel.com>\nReviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/46af95231c9fa9db3363675dd15f7a42baf351c5"},{"sha":"e3c56e1142c35e17f072d6f3c23678e45cb7a746","author":{"email":"3a1de429413b8a337d3d0a9d72c52f6d44ea541c@linux.intel.com","name":"Chao Peng"},"message":"x86: dynamically get/set CBM for a domain\n\nFor CAT, COS is maintained in hypervisor only while CBM is exposed to\nuser space directly to allow getting/setting domain's cache capacity.\nFor each specified CBM, hypervisor will either use a existed COS which\nhas the same CBM or allocate a new one if the same CBM is not found. If\nthe allocation fails because of no enough COS available then error is\nreturned. The getting/setting are always operated on a specified socket.\nFor multiple sockets system, the interface may be called several times.\n\nSigned-off-by: Chao Peng <chao.p.peng@linux.intel.com>\nReviewed-by: Dario Faggioli <dario.faggioli@citrix.com>\nAcked-by: Jan Beulich <jbeulich@suse.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/e3c56e1142c35e17f072d6f3c23678e45cb7a746"},{"sha":"4cbbe62a92434242c973cc56108d695ea6f053e7","author":{"email":"3a1de429413b8a337d3d0a9d72c52f6d44ea541c@linux.intel.com","name":"Chao Peng"},"message":"x86: add scheduling support for Intel CAT\n\nOn context switch, write the the domain's Class of Service(COS) to MSR\nIA32_PQR_ASSOC, to notify hardware to use the new COS.\n\nFor performance reason, the COS mask for current cpu is also cached in\nthe local per-CPU variable.\n\nSigned-off-by: Chao Peng <chao.p.peng@linux.intel.com>\nAcked-by: Jan Beulich <jbeulich@suse.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/4cbbe62a92434242c973cc56108d695ea6f053e7"},{"sha":"9a566a83d6374e7425bcb330e03c8ca9b31a0d0b","author":{"email":"3a1de429413b8a337d3d0a9d72c52f6d44ea541c@linux.intel.com","name":"Chao Peng"},"message":"xsm: add CAT related policies\n\nAdd xsm policies for Cache Allocation Technology(CAT) related hypercalls\nto restrict the functions visibility to control domain only.\n\nSigned-off-by: Chao Peng <chao.p.peng@linux.intel.com>\nAcked-by: Daniel De Graaf <dgdegra@tycho.nsa.gov>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/9a566a83d6374e7425bcb330e03c8ca9b31a0d0b"}]}