{"action":"created","comment":{"url":"https://api.github.com/repos/slava77/emu/pulls/comments/23505634","id":23505634,"diff_hunk":"@@ -462,54 +464,2132 @@ ChamberUtilities::ChamberUtilities(){\n     for (int j=0; j<32; j++) {\n       CFEBStripScan_[i][j] = -1;\n     }\n-  for (int i=0;i<112;i++) ALCTWireScan_[i] = -1;\n-  //\n-  // ranges over which to analyze DMB histograms\n-  ScopeMin_        = 0;\n-  ScopeMax_        = 4;\n-  AffToL1aValueMin_= 110;\n-  AffToL1aValueMax_= 160;\n-  CfebDavValueMin_ = 0;\n-  CfebDavValueMax_ = 10;\n-  TmbDavValueMin_  = 0;\n-  TmbDavValueMax_  = 10;\n-  AlctDavValueMin_ = 20;\n-  AlctDavValueMax_ = 30;\n-  // ODMB\n-  l1acc_dav_delay_ = -1;\n-  alct_dav_delay_ = -1;\n-  tmb_dav_delay_ = -1;\n-  // DCFEB\n-  pipeline_depth_a_ = -1;\n-  pipeline_depth_fine_a_ = -1;\n-  pipeline_depth_b_ = -1;\n-  pipeline_depth_fine_b_ = -1;\n+  for (int i=0;i<112;i++) ALCTWireScan_[i] = -1;\n+  //\n+  // ranges over which to analyze DMB histograms\n+  ScopeMin_        = 0;\n+  ScopeMax_        = 4;\n+  AffToL1aValueMin_= 110;\n+  AffToL1aValueMax_= 160;\n+  CfebDavValueMin_ = 0;\n+  CfebDavValueMax_ = 10;\n+  TmbDavValueMin_  = 0;\n+  TmbDavValueMax_  = 10;\n+  AlctDavValueMin_ = 20;\n+  AlctDavValueMax_ = 30;\n+  // ODMB\n+  l1acc_dav_delay_ = -1;\n+  alct_dav_delay_ = -1;\n+  tmb_dav_delay_ = -1;\n+  // DCFEB\n+  pipeline_depth_a_ = -1;\n+  pipeline_depth_fine_a_ = -1;\n+  pipeline_depth_b_ = -1;\n+  pipeline_depth_fine_b_ = -1;\n+\n+}\n+//\n+//\n+ChamberUtilities::~ChamberUtilities(){\n+  //\n+  //\n+}\n+/////////////////////////////////////////////////////////////////////////////////\n+// peripheral crate parameter measurements\n+/////////////////////////////////////////////////////////////////////////////////\n+//----------------------------------------------\n+// CFEB-TMB clock phases\n+//----------------------------------------------\n+void ChamberUtilities::CFEBTiming(){\n+  //\n+  // default with no argument is \"normal_scan\"\n+  //\n+  return CFEBTiming_with_Posnegs(normal_scan);\n+}\n+//\n+void ChamberUtilities::CFEBTiming(CFEBTiming_scanType scanType) {\n+  //\n+  return CFEBTiming_with_Posnegs(scanType);\n+}\n+//\n+    const int ChamberUtilities::CFEBPatterns[9][6] = {\n+      {5, 2, 0, -2, -4, -5},\n+      {-5, -2, 0, 2, 4, 5},\n+      {4, 2, 0, -2, -4, -4},\n+      {-4, -2, 0, 2, 4, 4},\n+      {3, 1, 0, -1, -2, -3},\n+      {-3, -1, 0, 1, 2, 3},\n+      {2, 1, 0, -1, -2, -2},\n+      {-2, -1, 0, 1, 2, 2},\n+      {0, 0, 0, 0, 0, 0}\n+    };\n+\n+    const int ChamberUtilities::DMBCounters[60] = {\n+      0x3f,\n+      0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,\n+      0x31,0x32,0x33,0x34,0x35,0x36,0x37,\n+      0x38,\n+      0x39,\n+      0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,\n+      0x4A,\n+      0x4B,\n+      0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,\n+      0x61,0x62,0x63,0x64,0x65,0x66,0x67,\n+      0x71,0x72,0x73,0x74,0x75,0x76,0x77,\n+      0x78,\n+      0x79,\n+      0x4F,\n+      0x5A,\n+      0x5B,\n+      0x5C,\n+      0x5D\n+    };\n+\n+    void ChamberUtilities::CFEBTiming_Configure(int * tof) {\n+      //\n+      // send output to std::cout except for the essential information\n+      thisTMB->RedirectOutput(&std::cout);\n+      thisDMB->RedirectOutput(&std::cout);\n+      thisCCB_->RedirectOutput(&std::cout);\n+      thisMPC->RedirectOutput(&std::cout);\n+      //\n+      // Get initial values, so we can go back to them at the end if we want....\n+      // -> Hard Reset to put all the values from the userPROM onto the TMB\n+      //thisCCB_->setCCBMode(CCB::VMEFPGA);\n+      //thisCCB_->hardReset();\n+      thisCCB_->setCCBMode(CCB::DLOG);\n+      //\n+      thisTMB->ReadRegister(vme_ddd1_adr); // Get phase and TOF delay from hardware\n+      thisTMB->ReadRegister(vme_ddd2_adr); //\n+      int initial_cfeb_tof_delay[5] = {thisTMB->GetReadCfeb0TOFDelay(),\n+\tthisTMB->GetReadCfeb1TOFDelay(),\n+\tthisTMB->GetReadCfeb2TOFDelay(),\n+\tthisTMB->GetReadCfeb3TOFDelay(),\n+\tthisTMB->GetReadCfeb4TOFDelay()};\n+      //\n+      thisTMB->ReadRegister(phaser_cfeb0_rxd_adr); // Get phaser information\n+      thisTMB->ReadRegister(phaser_cfeb1_rxd_adr); //\n+      thisTMB->ReadRegister(phaser_cfeb2_rxd_adr); //\n+      thisTMB->ReadRegister(phaser_cfeb3_rxd_adr); //\n+      thisTMB->ReadRegister(phaser_cfeb4_rxd_adr); //\n+      int initial_cfeb_phase[5] = { thisTMB->GetReadCfeb0RxClockDelay(),\n+\tthisTMB->GetReadCfeb1RxClockDelay(),\n+\tthisTMB->GetReadCfeb2RxClockDelay(),\n+\tthisTMB->GetReadCfeb3RxClockDelay(),\n+\tthisTMB->GetReadCfeb4RxClockDelay() };\n+      int initial_cfeb_posneg[5]= { thisTMB->GetReadCfeb0RxPosNeg(),\n+\tthisTMB->GetReadCfeb1RxPosNeg(),\n+\tthisTMB->GetReadCfeb2RxPosNeg(),\n+\tthisTMB->GetReadCfeb3RxPosNeg(),\n+\tthisTMB->GetReadCfeb4RxPosNeg() };\n+      //\n+      thisTMB->ReadRegister(seq_trig_en_adr);\n+      int initial_clct_pretrig_enable           = thisTMB->GetReadClctPatternTrigEnable();    //0x68\n+      //\n+      thisTMB->ReadRegister(tmb_trig_adr);\n+      int initial_clct_trig_enable              = thisTMB->GetReadTmbAllowClct();             //0x86\n+      //\n+      thisTMB->ReadRegister(seq_clct_adr);\n+      int initial_clct_halfstrip_pretrig_thresh = thisTMB->GetReadHsPretrigThresh();          //0x70\n+      int initial_clct_pattern_thresh           = thisTMB->GetReadMinHitsPattern();           //0x70\n+      //\n+      thisTMB->ReadRegister(layer_trg_mode_adr);\n+      int initial_layer_trig_enable             = thisTMB->GetReadEnableLayerTrigger();       //0xf0\n+      //\n+      thisTMB->ReadRegister(ccb_trig_adr);\n+      int initial_ignore_ccb_startstop          = thisTMB->GetReadIgnoreCcbStartStop();       //0x2c\n+      //\n+      // Set up for this test...\n+      thisTMB->SetClctPatternTrigEnable(1);\n+      thisTMB->SetClctExtTrigEnable(1);\n+      thisTMB->WriteRegister(seq_trig_en_adr);\n+      //\n+      thisTMB->SetTmbAllowClct(1);\n+      thisTMB->WriteRegister(tmb_trig_adr);\n+      //\n+      thisTMB->SetHsPretrigThresh(5);\n+      //thisTMB->SetMinHitsPattern(5); // 5 is used for actual patterns\n+      thisTMB->SetMinHitsPattern(1); // 1 used for simple test\n+      thisTMB->WriteRegister(seq_clct_adr);\n+      //\n+      thisTMB->SetIgnoreCcbStartStop(0);\n+      thisTMB->WriteRegister(ccb_trig_adr);\n+      //\n+      thisTMB->SetEnableLayerTrigger(0);\n+      thisTMB->WriteRegister(layer_trg_mode_adr);\n+      //\n+      int test_cfeb_tof_delay[5] = { thisTMB->GetCfeb0TOFDelay(),\n+\tthisTMB->GetCfeb1TOFDelay(),\n+\tthisTMB->GetCfeb2TOFDelay(),\n+\tthisTMB->GetCfeb3TOFDelay(),\n+\tthisTMB->GetCfeb4TOFDelay() };\n+      //\n+      for (int i=0; i<5; i++) {\n+\tif (initial_cfeb_tof_delay[i] != test_cfeb_tof_delay[i]) {\n+\t  (*MyOutput_) << \"WARNING: value in userPROM cfeb\" << i << \"_tof_delay = \" << initial_cfeb_tof_delay[i]\n+\t    << \" is not the same as the test value = \" << test_cfeb_tof_delay[i]\n+\t    << std::endl;\n+\t  std::cout    << \"WARNING: value in userPROM cfeb\" << i << \"_tof_delay = \" << initial_cfeb_tof_delay[i]\n+\t    << \" is not the same as the test value = \" << test_cfeb_tof_delay[i]\n+\t    << std::endl;\n+\t}\n+      }\n+      //\n+      if(tof == NULL) {\n+\tthisTMB->SetCfeb0TOFDelay(test_cfeb_tof_delay[0]);\n+\tthisTMB->SetCfeb1TOFDelay(test_cfeb_tof_delay[1]);\n+\tthisTMB->SetCfeb2TOFDelay(test_cfeb_tof_delay[2]);\n+\tthisTMB->SetCfeb3TOFDelay(test_cfeb_tof_delay[3]);\n+\tthisTMB->SetCfeb4TOFDelay(test_cfeb_tof_delay[4]);\n+      }\n+      else {\n+\tthisTMB->SetCfeb0TOFDelay(tof[0]);\n+\tthisTMB->SetCfeb1TOFDelay(tof[1]);\n+\tthisTMB->SetCfeb2TOFDelay(tof[2]);\n+\tthisTMB->SetCfeb3TOFDelay(tof[3]);\n+\tthisTMB->SetCfeb4TOFDelay(tof[4]);\n+      }\n+      thisTMB->WriteRegister(vme_ddd1_adr); // Write phase and TOF delay to hardware\n+      thisTMB->WriteRegister(vme_ddd2_adr); //\n+\n+      //New lines from Stan's code\n+      //{\n+      thisTMB->SetFifoMode(1);\n+      thisTMB->SetFifoTbins(30);\n+      thisTMB->SetFifoPreTrig(5);\n+      thisTMB->SetFifoNoRawHits(0);\n+      thisTMB->WriteRegister(emu::pc::seq_fifo_adr);\n+\n+      // thisTMB->SetL1aDelay(109);\n+      //thisTMB->WriteRegister(emu::pc::seq_l1a_adr);\n+\n+      int TimeDelay = 8;\n+\n+      //printf(\" TimeDelay %d \\n\",TimeDelay);\n+      std::cout << \" TimeDelay \" << TimeDelay << std::endl;\n+      thisTMB->tmb_clk_delays(TimeDelay,0);\n+      thisTMB->tmb_clk_delays(TimeDelay,1);\n+      thisTMB->tmb_clk_delays(TimeDelay,2);\n+      thisTMB->tmb_clk_delays(TimeDelay,3);\n+      thisTMB->tmb_clk_delays(TimeDelay,4);\n+      //}\n+\n+\n+      thisTMB->FireDDDStateMachine();\n+      //\n+      comparing_with_clct_ = true;\n+      thisTMB->StartTTC();\n+      ::sleep(1);\n+    }\n+\n+    void ChamberUtilities::SetCfebRxPosNeg(int posneg) {\n+      thisTMB->SetCfeb0RxPosNeg(posneg);\n+      thisTMB->SetCfeb1RxPosNeg(posneg);\n+      thisTMB->SetCfeb2RxPosNeg(posneg);\n+      thisTMB->SetCfeb3RxPosNeg(posneg);\n+      thisTMB->SetCfeb4RxPosNeg(posneg);\n+      thisTMB->SetCfeb5RxPosNeg(posneg);\n+      thisTMB->SetCfeb6RxPosNeg(posneg);\n+      //usleep(10000);\n+    }\n+\n+    void ChamberUtilities::SetCfebRxClockDelay(int delay) {\n+      thisTMB->SetCfeb0RxClockDelay(delay); \t\t// Set delay in TMB object\n+      thisTMB->WriteRegister(phaser_cfeb0_rxd_adr);\t// Write delay to hardware\n+      thisTMB->FirePhaser(phaser_cfeb0_rxd_adr);\t\t// Load delay\n+      //\n+      thisTMB->SetCfeb1RxClockDelay(delay);\n+      thisTMB->WriteRegister(phaser_cfeb1_rxd_adr);\n+      thisTMB->FirePhaser(phaser_cfeb1_rxd_adr);\n+      //\n+      thisTMB->SetCfeb2RxClockDelay(delay);\n+      thisTMB->WriteRegister(phaser_cfeb2_rxd_adr);\n+      thisTMB->FirePhaser(phaser_cfeb2_rxd_adr);\n+      //\n+      thisTMB->SetCfeb3RxClockDelay(delay);\n+      thisTMB->WriteRegister(phaser_cfeb3_rxd_adr);\n+      thisTMB->FirePhaser(phaser_cfeb3_rxd_adr);\n+      //\n+      thisTMB->SetCfeb4RxClockDelay(delay);\n+      thisTMB->WriteRegister(phaser_cfeb4_rxd_adr);\n+      thisTMB->FirePhaser(phaser_cfeb4_rxd_adr);\n+      //\n+      if(thisTMB->GetHardwareVersion() == 2) {\n+\tthisTMB->SetCfeb5RxClockDelay(delay);\n+\tthisTMB->WriteRegister(phaser_cfeb5_rxd_adr);\n+\tthisTMB->FirePhaser(phaser_cfeb5_rxd_adr);\n+\t//\n+\tthisTMB->SetCfeb6RxClockDelay(delay);\n+\tthisTMB->WriteRegister(phaser_cfeb6_rxd_adr);\n+\tthisTMB->FirePhaser(phaser_cfeb6_rxd_adr);\n+      }\n+      //usleep(10000);\n+    }\n+    //\n+    template <size_t XS_per_CFEB>\n+      int ChamberUtilities::GetInputXStrip(int output_xstrip) {\n+\tconst int Min_CFEB_in_non_me11 = 0;\n+\tconst int Max_CFEB_in_non_me11 = 4;\n+\tconst int Min_CFEB_in_region_a = 0;\n+\tconst int Max_CFEB_in_region_a = 3;\n+\tconst int Min_CFEB_in_region_b = 4;\n+\tconst int Max_CFEB_in_region_b = 6;\n+\tconst int Max_XS_in_CFEB = XS_per_CFEB - 1;\n+\n+\tint region = output_xstrip / XS_per_CFEB;\n+\tint phase = output_xstrip % XS_per_CFEB;\n+\tint input_xs = -1;\n+\tint tmb_compile_type = thisTMB->GetReadTMBFirmwareCompileType();\n+\tif(tmb_compile_type == 0xa) {\n+\t  if(region >= Min_CFEB_in_non_me11 && region <= Max_CFEB_in_non_me11)\n+\t    input_xs = phase;\n+\t}\n+\telse if(tmb_compile_type == 0xb) {\n+\t  if(region >= Min_CFEB_in_non_me11 && region <= Max_CFEB_in_non_me11)\n+\t    input_xs = Max_XS_in_CFEB - phase;\n+\t}\n+\telse if(tmb_compile_type == 0xc) {\n+\t  if(region >= Min_CFEB_in_region_a && region <= Max_CFEB_in_region_a) {\n+\t    input_xs = phase;\n+\t  }\n+\t  else if(region >= Min_CFEB_in_region_b && region <= Max_CFEB_in_region_b) {\n+\t    input_xs = Max_XS_in_CFEB - phase;\n+\t  }\n+\t}\n+\telse if(tmb_compile_type == 0xd) {\n+\t  if(region >= Min_CFEB_in_region_a && region <= Max_CFEB_in_region_a) {\n+\t    input_xs = Max_XS_in_CFEB - phase;\n+\t  }\n+\t  else if(region >= Min_CFEB_in_region_b && region <= Max_CFEB_in_region_b) {\n+\t    input_xs = phase;\n+\t  }\n+\t}\n+\treturn input_xs;\n+      }\n+    //\n+    template <size_t XS_per_CFEB>\n+      int ChamberUtilities::GetInputCFEBByX(int output_xstrip) {\n+\tconst int Min_CFEB_in_non_me11 = 0;\n+\tconst int Max_CFEB_in_non_me11 = 4;\n+\tconst int Min_CFEB_in_region_a = 0;\n+\tconst int Max_CFEB_in_region_a = 3;\n+\tconst int Min_CFEB_in_region_b = 4;\n+\tconst int Max_CFEB_in_region_b = 6;\n+\n+\tint region = output_xstrip / XS_per_CFEB;\n+\tint cfeb = -1;\n+\tint tmb_compile_type = thisTMB->GetReadTMBFirmwareCompileType();\n+\tif(tmb_compile_type == 0xa) {\n+\t  if(region >= Min_CFEB_in_non_me11 && region <= Max_CFEB_in_non_me11)\n+\t    cfeb = region;\n+\t}\n+\telse if(tmb_compile_type == 0xb) {\n+\t  if(region >= Min_CFEB_in_non_me11 && region <= Max_CFEB_in_non_me11)\n+\t    cfeb = Max_CFEB_in_non_me11 - region;\n+\t}\n+\telse if(tmb_compile_type == 0xc) {\n+\t  if(region >= Min_CFEB_in_region_a && region <= Max_CFEB_in_region_a) {\n+\t    cfeb = region;\n+\t  }\n+\t  else if(region >= Min_CFEB_in_region_b && region <= Max_CFEB_in_region_b) {\n+\t    cfeb = Min_CFEB_in_region_b + (Max_CFEB_in_region_b - region);\n+\t  }\n+\t}\n+\telse if(tmb_compile_type == 0xd) {\n+\t  if(region >= Min_CFEB_in_region_a && region <= Max_CFEB_in_region_a) {\n+\t    cfeb = Min_CFEB_in_region_a + (Max_CFEB_in_region_a - region);\n+\t  }\n+\t  else if(region >= Min_CFEB_in_region_b && region <= Max_CFEB_in_region_b) {\n+\t    cfeb = region;\n+\t  }\n+\t}\n+\treturn cfeb;\n+      }\n+    //\n+    template <size_t XS_per_CFEB>\n+      int ChamberUtilities::GetOutputXStrip(int cfeb, int input_xstrip) {\n+\tconst int Bad_HS = -1;\n+\tconst int Min_CFEB_in_non_me11 = 0;\n+\tconst int Max_CFEB_in_non_me11 = 4;\n+\tconst int N_CFEB_in_non_me11 = Max_CFEB_in_non_me11 - Min_CFEB_in_non_me11 + 1;\n+\tconst int Min_XS_in_non_me11 = 0;\n+\tconst int Max_XS_in_non_me11 = N_CFEB_in_non_me11*XS_per_CFEB - 1;\n+\tconst int Min_CFEB_in_region_a = 0;\n+\tconst int Max_CFEB_in_region_a = 3;\n+\tconst int Min_XS_in_region_a = Min_CFEB_in_region_a*XS_per_CFEB;\n+\tconst int Max_XS_in_region_a = (Max_CFEB_in_region_a + 1)*XS_per_CFEB - 1;\n+\tconst int Min_CFEB_in_region_b = 4;\n+\tconst int Max_CFEB_in_region_b = 6;\n+\tconst int Min_XS_in_region_b = Min_CFEB_in_region_b*XS_per_CFEB;\n+\tconst int Max_XS_in_region_b = (Max_CFEB_in_region_b + 1)*XS_per_CFEB - 1;\n+\tint output_xs = Bad_HS;\n+\tint tmb_compile_type = thisTMB->GetReadTMBFirmwareCompileType();\n+\tif(tmb_compile_type == 0xa) {\n+\t  if(cfeb >= Min_CFEB_in_non_me11 && cfeb <= Max_CFEB_in_non_me11)\n+\t    output_xs = Min_XS_in_non_me11 + (XS_per_CFEB*cfeb + input_xstrip);\n+\t  if(!(output_xs >= Min_XS_in_non_me11 && output_xs <= Max_XS_in_non_me11))\n+\t    output_xs = Bad_HS;\n+\t}\n+\telse if(tmb_compile_type == 0xb) {\n+\t  if(cfeb >= Min_CFEB_in_non_me11 && cfeb <= Max_CFEB_in_non_me11)\n+\t    output_xs = Max_XS_in_non_me11 - (XS_per_CFEB*cfeb + input_xstrip); \n+\t  if(!(output_xs >= Min_XS_in_non_me11 && output_xs <= Max_XS_in_non_me11))\n+\t    output_xs = Bad_HS;\n+\t}\n+\telse if(tmb_compile_type == 0xc) {\n+\t  if(cfeb >= Min_CFEB_in_region_a && cfeb <= Max_CFEB_in_region_a)\n+\t    output_xs = Min_XS_in_region_a + (XS_per_CFEB*(cfeb - Min_CFEB_in_region_a) + input_xstrip);\n+\t  else if(cfeb >= Min_CFEB_in_region_b && cfeb <= Max_CFEB_in_region_b)\n+\t    output_xs = Max_XS_in_region_b - (XS_per_CFEB*(cfeb - Min_CFEB_in_region_b) + input_xstrip);\n+\t  if(!(output_xs >= Min_XS_in_region_a && output_xs <= Max_XS_in_region_b))\n+\t    output_xs = Bad_HS;\n+\t}\n+\telse if(tmb_compile_type == 0xd) {\n+\t  if(cfeb >= Min_CFEB_in_region_a && cfeb <= Max_CFEB_in_region_a)\n+\t    output_xs = Max_XS_in_region_a - (XS_per_CFEB*(cfeb - Min_CFEB_in_region_a) + input_xstrip);\n+\t  else if(cfeb >= Min_CFEB_in_region_b && cfeb <= Max_CFEB_in_region_b)\n+\t    output_xs = Min_XS_in_region_b + (XS_per_CFEB*(cfeb - Min_CFEB_in_region_b) + input_xstrip);\n+\t  if(!(output_xs >= Min_XS_in_region_a && output_xs <= Max_XS_in_region_b))\n+\t    output_xs = Bad_HS;\n+\t}\n+\n+\treturn output_xs;\n+      }\n+    //\n+    inline void ChamberUtilities::CFEBTiming_PrintConfiguration(CFEBTiming_Configuration & config) {\n+      (*MyOutput_) << std::setw(23) << \"tmb_internal_l1a: \" << std::setw(4) << config.tmb_internal_l1a << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"clct_pattern_trig_en: \" << std::setw(4) << config.clct_pattern_trig_en << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"clct_ext_trig_en: \" << std::setw(4) << config.clct_ext_trig_en << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"tmb_allow_clct: \" << std::setw(4) << config.tmb_allow_clct << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"hs_pretrig_hit_thresh: \" << std::setw(4) << config.hs_pretrig_hit_thresh << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"min_hits_pattern: \" << std::setw(4) << config.min_hits_pattern << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"ignore_ccb_startstop: \" << std::setw(4) << config.ignore_ccb_startstop << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"layer_trigger_en: \" << std::setw(4) << config.layer_trigger_en << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"fifo_mode: \" << std::setw(4) << config.fifo_mode << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"fifo_tbins: \" << std::setw(4) << config.fifo_tbins << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"fifo_pretrig: \" << std::setw(4) << config.fifo_pretrig << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"fifo_no_hits_raw: \" << std::setw(4) << config.fifo_no_hits_raw << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"ccb_ext_trig_delay: \" << std::setw(4) << config.ccb_ext_trig_delay << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"tmb_l1a_delay: \" << std::setw(4) << config.tmb_l1a_delay << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"cfeb_rx_posneg: \" << std::setw(4) << config.cfeb_rx_posneg << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"cfeb_rx_clock_delay: \" << std::setw(4) << config.cfeb_rx_clock_delay << std::endl;\n+      (*MyOutput_) << std::setw(23) << \"cfeb_clock_phase: \" << std::setw(4) << config.cfeb_clock_phase << std::endl;\n+    }\n+    //\n+    inline bool ChamberUtilities::CFEBTiming_CheckCLCT(int cfeb, unsigned int layer_mask, unsigned int pattern, unsigned int halfstrip) {\n+      bool is_good = true;\n+      unsigned int n_layers = 0;\n+      for(int i=0; i<6; ++i) {\n+\tn_layers += (layer_mask >> i) & 0x1;\n+      }\n+      thisTMB->DecodeCLCT();\n+      thisTMB->GetCLCT0keyHalfStrip();\n+      is_good &= thisTMB->GetCLCT0Nhit() == n_layers;\n+      is_good &= thisTMB->GetCLCT0PatternId() == pattern;\n+      return is_good;\n+    }\n+    //\n+    inline void ChamberUtilities::CFEBTiming_ReadConfiguration(CFEBTiming_Configuration & config) {\n+      if(is_me11_) {\n+\tthisTMB->ReadRegister(seq_l1a_adr);\n+\tconfig.tmb_internal_l1a = thisTMB->GetInternalL1a();\n+\n+\tthisTMB->ReadRegister(seq_trig_en_adr);\n+\tconfig.clct_pattern_trig_en = thisTMB->GetReadClctPatternTrigEnable();\n+\tconfig.clct_ext_trig_en = thisTMB->GetReadClctExtTrigEnable();\n+\n+      }\n+\n+      thisTMB->ReadRegister(tmb_trig_adr);\n+      config.tmb_allow_clct = thisTMB->GetReadTmbAllowClct();\n+\n+      thisTMB->ReadRegister(seq_clct_adr);\n+      config.hs_pretrig_hit_thresh = thisTMB->GetReadHsPretrigThresh();\n+      config.min_hits_pattern = thisTMB->GetReadMinHitsPattern();\n+\n+      thisTMB->ReadRegister(ccb_trig_adr);\n+      config.ignore_ccb_startstop = thisTMB->GetReadIgnoreCcbStartStop();\n+\n+      thisTMB->ReadRegister(layer_trg_mode_adr);\n+      config.layer_trigger_en = thisTMB->GetReadEnableLayerTrigger();\n+\n+\n+      thisTMB->ReadRegister(seq_fifo_adr);\n+      config.fifo_mode = thisTMB->GetReadFifoMode();\n+      config.fifo_tbins = thisTMB->GetReadFifoTbins();\n+      config.fifo_pretrig = thisTMB->GetReadFifoPreTrig();\n+      config.fifo_no_hits_raw = thisTMB->GetReadFifoNoRawHits();\n+\n+      if(is_me11_) {\n+\tunsigned csrb5 = thisCCB_->ReadRegister(CCB::CSRB5);\n+\tconfig.ccb_ext_trig_delay = (csrb5 >> 8) & 0xff;\n+\n+\tthisTMB->ReadRegister(seq_l1a_adr);\n+\tconfig.tmb_l1a_delay = thisTMB->GetL1aDelay();\n+      }\n+\n+      thisTMB->ReadRegister(phaser_cfeb0_rxd_adr); // Get phaser information\n+      config.cfeb_rx_posneg = thisTMB->GetReadCfeb0RxPosNeg();\n+      config.cfeb_rx_clock_delay = thisTMB->GetReadCfeb0RxClockDelay();\n+    }\n+    //\n+    inline bool ChamberUtilities::CFEBTiming_CheckConfiguration(const CFEBTiming_Configuration & orig) {\n+      bool same = true;\n+      CFEBTiming_Configuration read(orig);\n+      CFEBTiming_ReadConfiguration(read);\n+      CFEBTiming_PrintConfiguration(read);\n+      std::cout << std::dec;\n+      if(is_me11_ && (read.tmb_internal_l1a != orig.tmb_internal_l1a)) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD tmb_internal_l1a: EXPECTED: \" << std::setw(4) << orig.tmb_internal_l1a << \" | READ: \" << std::setw(4) << read.tmb_internal_l1a << std::endl;\n+\tsame = false;\n+      }\n+      if(is_me11_ && (read.clct_pattern_trig_en != orig.clct_pattern_trig_en)) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD clct_pattern_trig_en: EXPECTED: \" << std::setw(4) << orig.clct_pattern_trig_en << \" | READ: \" << std::setw(4) << read.clct_pattern_trig_en << std::endl;\n+\tsame = false;\n+      }\n+      if(is_me11_ && (read.clct_ext_trig_en != orig.clct_ext_trig_en)) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD clct_ext_trig_en: EXPECTED: \" << std::setw(4) << orig.clct_ext_trig_en << \" | READ: \" << std::setw(4) << read.clct_ext_trig_en << std::endl;\n+\tsame = false;\n+      }\n+      if(read.tmb_allow_clct != orig.tmb_allow_clct) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD tmb_allow_clct: EXPECTED: \" << std::setw(4) << orig.tmb_allow_clct << \" | READ: \" << std::setw(4) << read.tmb_allow_clct << std::endl;\n+\tsame = false;\n+      }\n+      if(read.hs_pretrig_hit_thresh != orig.hs_pretrig_hit_thresh) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD hs_pretrig_hit_thresh: EXPECTED: \" << std::setw(4) << orig.hs_pretrig_hit_thresh << \" | READ: \" << std::setw(4) << read.hs_pretrig_hit_thresh << std::endl;\n+\tsame = false;\n+      }\n+      if(read.min_hits_pattern != orig.min_hits_pattern) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD min_hits_pattern: EXPECTED: \" << std::setw(4) << orig.min_hits_pattern << \" | READ: \" << std::setw(4) << read.min_hits_pattern << std::endl;\n+\tsame = false;\n+      }\n+      if(read.ignore_ccb_startstop != orig.ignore_ccb_startstop) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD ignore_ccb_startstop: EXPECTED: \" << std::setw(4) << orig.ignore_ccb_startstop << \" | READ: \" << std::setw(4) << read.ignore_ccb_startstop << std::endl;\n+\tsame = false;\n+      }\n+      if(read.layer_trigger_en != orig.layer_trigger_en) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD layer_trigger_en: EXPECTED: \" << std::setw(4) << orig.layer_trigger_en << \" | READ: \" << std::setw(4) << read.layer_trigger_en << std::endl;\n+\tsame = false;\n+      }\n+      if(read.fifo_mode != orig.fifo_mode) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD fifo_mode: EXPECTED: \" << std::setw(4) << orig.fifo_mode << \" | READ: \" << std::setw(4) << read.fifo_mode << std::endl;\n+\tsame = false;\n+      }\n+      if(read.fifo_tbins != orig.fifo_tbins) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD fifo_tbins: EXPECTED: \" << std::setw(4) << orig.fifo_tbins << \" | READ: \" << std::setw(4) << read.fifo_tbins << std::endl;\n+\tsame = false;\n+      }\n+      if(read.fifo_pretrig != orig.fifo_pretrig) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD fifo_pretrig: EXPECTED: \" << std::setw(4) << orig.fifo_pretrig << \" | READ: \" << std::setw(4) << read.fifo_pretrig << std::endl;\n+\tsame = false;\n+      }\n+      if(read.fifo_no_hits_raw != orig.fifo_no_hits_raw) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD fifo_no_hits_raw: EXPECTED: \" << std::setw(4) << orig.fifo_no_hits_raw << \" | READ: \" << std::setw(4) << read.fifo_no_hits_raw << std::endl;\n+\tsame = false;\n+      }\n+      if(is_me11_ && (read.ccb_ext_trig_delay != orig.ccb_ext_trig_delay)) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD ccb_ext_trig_delay: EXPECTED: \" << std::setw(4) << orig.ccb_ext_trig_delay << \" | READ: \" << std::setw(4) << read.ccb_ext_trig_delay << std::endl;\n+\tsame = false;\n+      }\n+      if(is_me11_ && (read.tmb_l1a_delay != orig.tmb_l1a_delay)) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD tmb_l1a_delay: EXPECTED: \" << std::setw(4) << orig.tmb_l1a_delay << \" | READ: \" << std::setw(4) << read.tmb_l1a_delay << std::endl;\n+\tsame = false;\n+      }\n+      if(read.cfeb_rx_posneg != orig.cfeb_rx_posneg) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD cfeb_rx_posneg: EXPECTED: \" << std::setw(4) << orig.cfeb_rx_posneg << \" | READ: \" << std::setw(4) << read.cfeb_rx_posneg << std::endl;\n+\tsame = false;\n+      }\n+      if(read.cfeb_rx_clock_delay != orig.cfeb_rx_clock_delay) {\n+\t(*MyOutput_) << std::setw(37) << \"BAD cfeb_rx_clock_delay: EXPECTED: \" << std::setw(4) << orig.cfeb_rx_clock_delay << \" | READ: \" << std::setw(4) << read.cfeb_rx_clock_delay << std::endl;\n+\tsame = false;\n+      }\n+      return same;\n+    }\n+    //\n+    inline void ChamberUtilities::ConfigureTMB(const CFEBTiming_Configuration & config, int * cfeb_tof_delay) {\n+\n+      usleep(1000);\n+\n+      // Set up for this test...\n+      if(is_me11_) thisTMB->SetClctPatternTrigEnable(config.clct_pattern_trig_en);\n+      thisTMB->SetClctExtTrigEnable(config.clct_ext_trig_en);\n+      thisTMB->WriteRegister(seq_trig_en_adr);\n+\n+      usleep(1000);\n+\n+      thisTMB->SetTmbAllowClct(config.tmb_allow_clct);\n+      thisTMB->WriteRegister(tmb_trig_adr);\n+\n+      usleep(1000);\n+\n+      thisTMB->SetHsPretrigThresh(config.hs_pretrig_hit_thresh);\n+      thisTMB->SetMinHitsPattern(config.min_hits_pattern);\n+      thisTMB->WriteRegister(seq_clct_adr);\n+\n+      usleep(1000);\n+\n+      thisTMB->SetIgnoreCcbStartStop(config.ignore_ccb_startstop);\n+      thisTMB->WriteRegister(ccb_trig_adr);\n+\n+      usleep(1000);\n+\n+      thisTMB->SetEnableLayerTrigger(config.layer_trigger_en);\n+      thisTMB->WriteRegister(layer_trg_mode_adr);\n+\n+      usleep(1000);\n+\n+      int test_cfeb_tof_delay[5] = { thisTMB->GetCfeb0TOFDelay(),\n+\tthisTMB->GetCfeb1TOFDelay(),\n+\tthisTMB->GetCfeb2TOFDelay(),\n+\tthisTMB->GetCfeb3TOFDelay(),\n+\tthisTMB->GetCfeb4TOFDelay()\n+      };\n+\n+      if(cfeb_tof_delay == NULL)\n+\tcfeb_tof_delay = test_cfeb_tof_delay;\n+\n+      thisTMB->SetCfeb0TOFDelay(cfeb_tof_delay[0]);\n+      thisTMB->SetCfeb1TOFDelay(cfeb_tof_delay[1]);\n+      thisTMB->SetCfeb2TOFDelay(cfeb_tof_delay[2]);\n+      thisTMB->SetCfeb3TOFDelay(cfeb_tof_delay[3]);\n+      thisTMB->SetCfeb4TOFDelay(cfeb_tof_delay[4]);\n+      thisTMB->WriteRegister(vme_ddd1_adr); // Write phase and TOF delay to hardware\n+      usleep(1000);\n+      thisTMB->WriteRegister(vme_ddd2_adr); //\n+      usleep(1000);\n+\n+      if(is_me11_) {\n+\t// Begin new lines from Stan's code\n+\tthisTMB->SetFifoMode(config.fifo_mode);\n+\tthisTMB->SetFifoTbins(config.fifo_tbins);\n+\tthisTMB->SetFifoPreTrig(config.fifo_pretrig);\n+\tthisTMB->SetFifoNoRawHits(config.fifo_no_hits_raw);\n+\tthisTMB->WriteRegister(emu::pc::seq_fifo_adr);\n+      }\n+\n+      usleep(1000);\n+\n+      // End new lines from Stan's code\n+\n+      thisTMB->WriteRegister(vme_dddoe_adr);\n+\n+      thisTMB->FireDDDStateMachine();\n+      //\n+      comparing_with_clct_ = true;\n+      thisTMB->StartTTC();\n+      sleep(1);\n+      usleep(1000);\n+    }\n+    //\n+    inline void ChamberUtilities::CFEBTiming_ConfigureLevel(CFEBTiming_Configuration & config, int level, int after) {\n+      //(*MyOutput_) << \"CFEBTiming Configure Level \" << level << std::endl;\n+\n+      if(level < 0 | level == 0 | (after & level <= 0)) {\n+\tthisCCB_->setCCBMode(CCB::VMEFPGA);\n+\tthisCCB_->hardReset();\n+\tthisCCB_->setCCBMode(CCB::DLOG);\n+\n+\tSetDCFEBsPipelineDepth(config.cfeb_pipeline_depth); // Set pipeline depth, does not have to be exact (~60)\n+\tusleep(100);\n+\tthisTMB->tmb_hard_reset_tmb_fpga(); // Hard reset the tmb to return to default settings\n+\tusleep(100);\n+\tCFEBTiming_ConfigureODMB(); // Do some odmb configuration?\n+\tusleep(100);\n+\tthisCCB_->l1aReset(); // Send a reset?\n+\tusleep(100);\n+\tResyncDCFEBs(); // Resync the dcfebs, apparently this is needed after the odmb config\n+\tusleep(100);\n+\tthisCCB_->EnableL1aFromDmbCfebCalibX(); // Enable pulsing of the dcfebs\n+\tusleep(100);\n+\t//SetODMBPedestalMode(); // Tell the odmb to always accept data, regardless of timing\n+\tusleep(100);\n+\tthisDMB->set_dac(config.dac, 0); // Set the pulse height\n+\tusleep(100);\n+\tthisDMB->set_comp_thresh(config.comp_thresh); // Set the comparator chip threshold\n+\tusleep(100);\n+\tif(thisDMB->GetHardwareVersion() < 2)\n+\t  thisDMB->settrgsrc(0); // disable DMB's own trigger, LCT\n+\tusleep(100);\n+      }\n+      if(level < 0 | level == 1 | (after & level <= 1)) {\n+\tthisCCB_->setCCBMode(CCB::DLOG);\n+\tConfigureTMB(config);\n+\tusleep(1000);\n+      }\n+      if(level == 2) {\n+\tif(is_me11_) {\n+\t  for(int cfeb=0; cfeb<thisDMB->cfebs_.size(); ++cfeb) {\n+\t    if((config.cfeb_mask & 0x7f) >> thisDMB->cfebs_[cfeb].number()) {\n+\n+\t      // Should not set dcfeb_clock_phase with the following function for regular scan, but should pick up the dcfeb_clock_phase that is set in xml\n+\t      thisDMB->dcfeb_fine_delay(thisDMB->cfebs_[cfeb], config.cfeb_clock_phase);\n+\n+\t      char tmp[2];\n+\t      thisDMB->autoload_select_readback_wrd(thisDMB->cfebs_[cfeb], 10);\n+\t      thisDMB->autoload_readback_wrd(thisDMB->cfebs_[cfeb], tmp);\n+\t      config.cfeb_clock_phase = tmp[0];\n+\n+\t      (*MyOutput_) << \"DCFEB \"<< cfeb << \" clock phase = \" << config.cfeb_clock_phase << std::endl;\n+\n+\t    }\n+\t    usleep(1000);\n+\t  }\n+\t}\n+\n+\telse {\n+\t  // Should not set tof with the following functions for regular scan, but instead pick up the tof that is set in xml\n+\t  thisTMB->SetCfeb0TOFDelay(config.cfeb_clock_phase);\n+\t  thisTMB->SetCfeb1TOFDelay(config.cfeb_clock_phase);\n+\t  thisTMB->SetCfeb2TOFDelay(config.cfeb_clock_phase);\n+\t  thisTMB->SetCfeb3TOFDelay(config.cfeb_clock_phase);\n+\t  thisTMB->SetCfeb4TOFDelay(config.cfeb_clock_phase);\n+\n+\t  thisTMB->WriteRegister(vme_ddd1_adr);\n+\t  thisTMB->WriteRegister(vme_ddd2_adr);\n+\t  thisTMB->FireDDDStateMachine();\t\n+\t}\n+      }\n+      if(level < 0 | level == 3 | (after & level <= 3)) {\n+\tif(is_me11_) {\n+\t  SetTMBInternalL1A(config.tmb_internal_l1a); // Disable the tmb's internal l1a\n+\t  usleep(1000);\n+\t  if(config.clct_ext_trig_en)\n+\t    thisTMB->EnableClctExtTrig(); // Enable l1a trigger from ccb\n+\t  usleep(1000);\n+\t  //thisCCB_->SetExtTrigDelay(0); // Set external l1a delay in ccb\n+\t  thisCCB_->SetExtTrigDelay(config.ccb_ext_trig_delay); // Set external l1a delay in ccb\n+\t  usleep(1000);\n+\t  //SetTMBL1ADelay(80); // Set tmb l1a delay\n+\t  SetTMBL1ADelay(config.tmb_l1a_delay); // Set tmb l1a delay\n+\t  SetTMBL1ADelay(config.tmb_l1a_delay); // Set tmb l1a delay\n+\t  usleep(1000);\n+\t}\n+\tSetCfebRxPosNeg(config.cfeb_rx_posneg); // Set posneg\n+\tusleep(1000);\n+\tSetCfebRxClockDelay(config.cfeb_rx_clock_delay); // Set the Rx clock delay (largely doesn't matter, only 1 bad value) \n+\tusleep(1000);\n+\t//\tthisCCB_->hardReset();\n+      }\n+    }\n+    //\n+    void ChamberUtilities::CFEBTiming_PulseInject(bool is_inject_scan, int cfeb, unsigned int layer_mask, unsigned int pattern, unsigned int halfstrip, unsigned int n_pulses, unsigned int pulse_delay) {\n+      std::cout << \"Start: \" << __PRETTY_FUNCTION__  << std::endl;\n+      const int MaxCFEB = 5;\n+      const int MaxTimeDelay=25;\n+      const bool is_cfeb_scan = cfeb < 0;\n+\n+      char test_hs[6]; memset(test_hs, 0, sizeof(test_hs));// hs[0-6] is 1-32 have strips in layers 0-6\n+      int test_hs_int[6]; memset(test_hs_int, 0, sizeof(test_hs_int));\n+      int test_hs_int_orig[6]; memset(test_hs_int_orig, 0, sizeof(test_hs_int_orig));\n+\n+      int output_halfstrip = GetOutputHalfStrip(cfeb, halfstrip);\n+\n+      //\n+      if(is_inject_scan){\n+\t// Build half strip array (specify a half strip to pulse for each layer)\n+\tfor(int layer=0; layer<6; ++layer){\n+\t  int val = output_halfstrip+CFEBPatterns[pattern-0x2][layer];\n+\t  if(GetInputCFEBByHalfStrip(output_halfstrip) == cfeb) {\n+\t    test_hs_int[layer] = GetInputHalfStrip(output_halfstrip) & 0x1f;\n+\t    test_hs[layer] = test_hs_int[layer];\n+\t  }\n+\t}\n+\n+\tthisDMB->SetTMBTxMode(cfeb, 5); // Set the mode of the CFEB in question\n+\tusleep(100);\n+\tthisDMB->shift_all(KILL_CHAN);\n+\tthisDMB->buck_shift();\n+\tusleep(100);\n+\tthisDMB->SetTMBTxModeLayerMask(cfeb, layer_mask); // Set the layer mask\n+\tusleep(100);\n+\t(*MyOutput_) << \"Pulsing hs \" << test_hs_int[2] << std::endl;\n+\tthisDMB->SetTMBTxModeShiftLayers(cfeb, test_hs); // Set the half strip for each layer\n+\tusleep(100);\n+\tthisCCB_->inject(n_pulses, pulse_delay); // Inject the pattern of half strips to the CFEB\n+\tusleep(100);\n+\tthisDMB->SetTMBTxMode(cfeb, 0); // Return mode to original state\n+\tusleep(100);\n+      }\n+      else {\n+\t// Build half strip array (specify a half strip to pulse for each layer)\n+\tfor(int layer=0; layer<6; ++layer){\n+\t  int val = output_halfstrip+CFEBPatterns[pattern-0x2][layer];\n+\t  test_hs_int[layer] = val;\n+\t  test_hs_int_orig[layer] = halfstrip+CFEBPatterns[pattern-0x2][layer];\n+\t}\n+\tif(true) {\n+\t  PulseHalfstrips(test_hs_int);\n+\t}\n+\telse {\n+\t  PulseCFEB(test_hs_int_orig,0x1<<cfeb);\n+\t  //LoadCFEB(test_hs_int_orig, 0x1<<cfeb, 0);\n+\t  //\n+\t  //thisCCB_->inject(1,0x4f);\n+\t}\n+      }\n+      std::cout << \"End: \" << __PRETTY_FUNCTION__  << std::endl;\n+    }\n+\n+    void ChamberUtilities::SetTMBL1ADelay(int delay) {\n+      //thisTMB->ReadRegister(ccb_trig_adr);\n+      //thisTMB->SetInternalL1aDelay(delay);\n+      //thisTMB->WriteRegister(ccb_trig_adr);\n+      thisTMB->ReadRegister(seq_l1a_adr);\n+      thisTMB->SetL1aDelay(delay);\n+      thisTMB->WriteRegister(seq_l1a_adr);\n+    }\n+\n+    int ChamberUtilities::GetTMBL1ADelay() {\n+      thisTMB->ReadRegister(seq_l1a_adr);\n+      //return thisTMB->GetInternalL1aDelay();\n+      return thisTMB->GetL1aDelay();\n+    }\n+\n+    void ChamberUtilities::SetTMBInternalL1A(int delay) {\n+      //thisTMB->ReadRegister(ccb_trig_adr);\n+      //thisTMB->SetInternalL1aDelay(delay);\n+      //thisTMB->WriteRegister(ccb_trig_adr);\n+      thisTMB->ReadRegister(seq_l1a_adr);\n+      thisTMB->SetInternalL1a(delay);\n+      thisTMB->WriteRegister(seq_l1a_adr);\n+    }\n+\n+    int ChamberUtilities::GetTMBInternalL1ADelay() {\n+      thisTMB->ReadRegister(seq_l1a_adr);\n+      //return thisTMB->GetInternalL1aDelay();\n+      return thisTMB->GetInternalL1a();\n+    }\n+\n+    void ChamberUtilities::ResyncDCFEBs() {\n+      char rcv[2];\n+      unsigned int addr;\n+      unsigned short int data;\n+      int irdwr;\n+      int slot_number;\n+\n+      if(thisDMB->GetHardwareVersion() == 2) {\n+\tslot_number = thisDMB->slot();\n+\n+\tunsigned int fw_version = thisDMB->odmb_firmware_version();\n+\tif(fw_version < 265) {\n+\t  //continue; // 265 == 0x0109\n+\n+\t  // Resync ODMB and DCFEB L1A Counters\n+\t  irdwr = 3;\n+\t  if((thisDMB->odmb_firmware_version() / 0x100) >= 3) {\n+\t    addr = 0x3014/*DCFEB_RESYNC*/ | (slot_number << 19);\n+\t    data = 0x0001;\n+\t  }\n+\t  else {\n+\t    addr = 0x3010/*DCFEB_REPROGRAM*/ | (slot_number << 19);\n+\t    data = 0x0002;\n+\t  }\n+\t  thisDMB->getCrate()->vmeController()->vme_controller(irdwr, addr, &data, rcv);\n+\t}\n+\tstd::cout << \" Calling Resync \" << std::endl;\n+      } // ODMB only\n+    }\n+\n+    void ChamberUtilities::SetDCFEBsPipelineDepth(int depth) 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