{"push_id":546021814,"size":10,"distinct_size":1,"ref":"refs/heads/hardened/current/unstable","head":"3265b82ff3e4134a51373397348d19b62a926eaf","before":"3d17590a2af9ad89d1ac5be51369e3ca1e318d4c","commits":[{"sha":"688468d31c0ac316df91f6b633e8ccf82deed7c8","author":{"email":"7ebbccbf2a9ebaa9338648798afddf195f6f1b63@FreeBSD.org","name":"imp"},"message":"On x86 force NEW_PCIB, since that's the default. While this option\nwould be picked up for kernel builds, it isn't picked up for\nold-fashioned builds. Without this option, PCI bus numbers are busted\nfor modules build iteratively.","distinct":false,"url":"https://api.github.com/repos/HardenedBSD/hardenedBSD/commits/688468d31c0ac316df91f6b633e8ccf82deed7c8"},{"sha":"6ea154d79358191f8b35a57387bfe5e064d385ef","author":{"email":"7ebbccbf2a9ebaa9338648798afddf195f6f1b63@FreeBSD.org","name":"imp"},"message":"Add a rather obnoxious warning if you don't have NEW_PCIB defined\nsince it's a total crap shoot if things will work.","distinct":false,"url":"https://api.github.com/repos/HardenedBSD/hardenedBSD/commits/6ea154d79358191f8b35a57387bfe5e064d385ef"},{"sha":"5a9676a3fd89f1bdeaf7fc81c8359fde923c94f0","author":{"email":"7ebbccbf2a9ebaa9338648798afddf195f6f1b63@FreeBSD.org","name":"imp"},"message":"Various interrelated fixes to make suspend / resume work better. We now\ncan suspend / resume and unload / load cbb and cardbus without errors\non my Lenovo T400, which wasn't possible before. Cards suspending\nand resuming in the CardBus slot not yet tested.\no Enable memory cycles to the bridge early (as part of the new\n  cbb_pci_bridge_init). This fixes the Bad VCC errors which were\n  caused by the code accessing the device registers with this\n  cleared. The suspend / resume process clears it.\no Refactor suspend / resume into bus specific code (though the ISA\n  code is just stubbed). This isn't strictly necessary, but makes\n  the initializaiton code more uniform and should be more bullet\n  proof in the face of variant behavior among cardbus bridges.\no Fixup comments in the power-up sequence to reflect reality. These\n  comments were written for one regime of power-up, but not updated\n  as things were revised.\no Add a paranoid small delay (100ms) to cover noisy cards powering\n  down.\no Fix some debugging prints to be easier to grep from dmesg.\n\nSponsored by: Netflix","distinct":false,"url":"https://api.github.com/repos/HardenedBSD/hardenedBSD/commits/5a9676a3fd89f1bdeaf7fc81c8359fde923c94f0"},{"sha":"530526c53d4ce488e1aebc3bd1e7f42490a8417a","author":{"email":"7b242d943fcf32e060e9005c389f6e64f0d376fc@FreeBSD.org","name":"hselasky"},"message":"Fix spelling.","distinct":false,"url":"https://api.github.com/repos/HardenedBSD/hardenedBSD/commits/530526c53d4ce488e1aebc3bd1e7f42490a8417a"},{"sha":"61bfd7e1b2c8d9ef553143272ef062f505db7a9b","author":{"email":"3bae1b7d571c203acfb4d62748e2c04607e018fd@FreeBSD.org","name":"jhibbits"},"message":"Add Altivec/VMX register support to ptrace.\n\nMFC after:\t2 weeks\nRelnotes:\tyes","distinct":false,"url":"https://api.github.com/repos/HardenedBSD/hardenedBSD/commits/61bfd7e1b2c8d9ef553143272ef062f505db7a9b"},{"sha":"6354209c5f275ac76f0f7ba57cc92ded7773a5fa","author":{"email":"3bae1b7d571c203acfb4d62748e2c04607e018fd@FreeBSD.org","name":"jhibbits"},"message":"Make use of the new Altivec ptrace support, to save the Altivec registers in\ngcore.\n\nMFC after:\t2 weeks\nRelnotes:\tyes","distinct":false,"url":"https://api.github.com/repos/HardenedBSD/hardenedBSD/commits/6354209c5f275ac76f0f7ba57cc92ded7773a5fa"},{"sha":"4091be74c6251d91f55098caf1a7ed06b1824534","author":{"email":"c4479bc4706e61360828478abdd0473c5b3be631@FreeBSD.org","name":"neel"},"message":"Fix typo (missing comma).\n\nMFC after:\t3 days","distinct":false,"url":"https://api.github.com/repos/HardenedBSD/hardenedBSD/commits/4091be74c6251d91f55098caf1a7ed06b1824534"},{"sha":"7d12e026a4c97d90e0ca4a2d85371c1a779a7667","author":{"email":"84b503db6d985a7240515b02455e8dc027cb5b7d@FreeBSD.org","name":"mav"},"message":"Reimplement TRIM throttling added in r248577.\n\nPrevious throttling implementation approached problem from the wrong side.\nIt significantly limited useful delaying of TRIM requests and aggregation\npotential, while not so much controlled TRIM burstiness under heavy load.\n\nWith this change random 4K write benchmarks (probably the worst case for\nTRIM) show me IOPS increase by 20%, average latency reduction by 30%, peak\nTRIM bursts reduction by 3 times and same peak TRIM map size (memory usage).\n\nAlso the new logic does not force map size down so heavily, really allowing\nto keep deleted data for 32 TXG or 30 seconds under moderate load.  It was\npractically impossible with old throttling logic, which pushed map down to\nonly 64 segments.\n\nReviewed by:\tsmh\nMFC after:\t2 weeks\nSponsored by:\tiXsystems, Inc.","distinct":false,"url":"https://api.github.com/repos/HardenedBSD/hardenedBSD/commits/7d12e026a4c97d90e0ca4a2d85371c1a779a7667"},{"sha":"7d9825ceb8afad081d5cdc703a55f092f26cd1d9","author":{"email":"b0125fa187132d47dbe983b53b8ad9c1146edd9c@hardenedbsd.org","name":"Oliver Pinter +"},"message":"Merge remote-tracking branch 'freebsd/master' into hardened/current/master","distinct":false,"url":"https://api.github.com/repos/HardenedBSD/hardenedBSD/commits/7d9825ceb8afad081d5cdc703a55f092f26cd1d9"},{"sha":"3265b82ff3e4134a51373397348d19b62a926eaf","author":{"email":"b0125fa187132d47dbe983b53b8ad9c1146edd9c@hardenedbsd.org","name":"Oliver Pinter +"},"message":"Merge remote-tracking branch 'origin/hardened/current/master' into hardened/current/unstable","distinct":true,"url":"https://api.github.com/repos/HardenedBSD/hardenedBSD/commits/3265b82ff3e4134a51373397348d19b62a926eaf"}]}