{"action":"closed","issue":{"url":"https://api.github.com/repos/LeventErkok/sbv/issues/95","labels_url":"https://api.github.com/repos/LeventErkok/sbv/issues/95/labels{/name}","comments_url":"https://api.github.com/repos/LeventErkok/sbv/issues/95/comments","events_url":"https://api.github.com/repos/LeventErkok/sbv/issues/95/events","html_url":"https://github.com/LeventErkok/sbv/issues/95","id":42786941,"number":95,"title":"Verilog support?","user":{"login":"weaversa","id":7407930,"avatar_url":"https://avatars.githubusercontent.com/u/7407930?v=3","gravatar_id":"","url":"https://api.github.com/users/weaversa","html_url":"https://github.com/weaversa","followers_url":"https://api.github.com/users/weaversa/followers","following_url":"https://api.github.com/users/weaversa/following{/other_user}","gists_url":"https://api.github.com/users/weaversa/gists{/gist_id}","starred_url":"https://api.github.com/users/weaversa/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/weaversa/subscriptions","organizations_url":"https://api.github.com/users/weaversa/orgs","repos_url":"https://api.github.com/users/weaversa/repos","events_url":"https://api.github.com/users/weaversa/events{/privacy}","received_events_url":"https://api.github.com/users/weaversa/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":{"login":"LeventErkok","id":549449,"avatar_url":"https://avatars.githubusercontent.com/u/549449?v=3","gravatar_id":"","url":"https://api.github.com/users/LeventErkok","html_url":"https://github.com/LeventErkok","followers_url":"https://api.github.com/users/LeventErkok/followers","following_url":"https://api.github.com/users/LeventErkok/following{/other_user}","gists_url":"https://api.github.com/users/LeventErkok/gists{/gist_id}","starred_url":"https://api.github.com/users/LeventErkok/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/LeventErkok/subscriptions","organizations_url":"https://api.github.com/users/LeventErkok/orgs","repos_url":"https://api.github.com/users/LeventErkok/repos","events_url":"https://api.github.com/users/LeventErkok/events{/privacy}","received_events_url":"https://api.github.com/users/LeventErkok/received_events","type":"User","site_admin":false},"milestone":null,"comments":7,"created_at":"2014-09-15T15:49:24Z","updated_at":"2015-07-12T22:37:36Z","closed_at":"2015-07-12T22:37:36Z","body":"I see that SBV can be used to compile down to straight-line C using `compileToC` and `compileToCLib`. The old version of Cryptol also had a way to translate SBV to Verilog, so I am guessing that you are familiar with it. If you reimplemented the translation to Verilog, I would try and get the Cryptol folks to make use of it. This is pertinent now that `abc` supports word-level designs! So, w/out AIGs, this could be a way to interface w/ 'abc'.\r\n"}}