{"push_id":826974091,"size":1000,"distinct_size":0,"ref":"refs/heads/arm/omap","head":"3ca9299e7dc65f2d8242cd7804818a8e840b5a26","before":"e203db293863fa15b4b1917d4398fb5bd63c4e88","commits":[{"sha":"2998272275fc31fc3d478ef9c95e7eaef67dafa3","author":{"email":"41bb5944f244750b7cf0394140496972a3f1bee3@intel.com","name":"Adrian Hunter"},"message":"perf tests: Fix task exit test setting maps\n\nThe test titled \"Test number of exit event of a simple workload\" was\nsetting cpu/thread maps directly.  Make it use the proper function\nperf_evlist__set_maps() especially now that it also propagates the maps.\n\nSigned-off-by: Adrian Hunter <adrian.hunter@intel.com>\nAcked-by: Jiri Olsa <jolsa@kernel.org>\nCc: Kan Liang <kan.liang@intel.com>\nLink: http://lkml.kernel.org/r/1441699142-18905-14-git-send-email-adrian.hunter@intel.com\nSigned-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/2998272275fc31fc3d478ef9c95e7eaef67dafa3"},{"sha":"c5e6bd2ed3e81df443e4ae11e95ed71ff77bf9e5","author":{"email":"41bb5944f244750b7cf0394140496972a3f1bee3@intel.com","name":"Adrian Hunter"},"message":"perf tests: Fix software clock events test setting maps\n\nThe test titled \"Test software clock events have valid period values\"\nwas setting cpu/thread maps directly.  Make it use the proper function\nperf_evlist__set_maps() especially now that it also propagates the maps.\n\nSigned-off-by: Adrian Hunter <adrian.hunter@intel.com>\nAcked-by: Jiri Olsa <jolsa@kernel.org>\nCc: Kan Liang <kan.liang@intel.com>\nLink: http://lkml.kernel.org/r/1441699142-18905-15-git-send-email-adrian.hunter@intel.com\nSigned-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/c5e6bd2ed3e81df443e4ae11e95ed71ff77bf9e5"},{"sha":"2314ee4d444e28d4670ff80c84df68c25887decb","author":{"email":"a38ad1fbd0b3373e0c012f4d28e16dbce652d487@linaro.org","name":"Leo Yan"},"message":"arm64: enable generic idle loop\n\nEnable generic idle loop for ARM64, so can support for hlt/nohlt\ncommand line options to override default idle loop behavior.\n\nAcked-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Leo Yan <leo.yan@linaro.org>\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/2314ee4d444e28d4670ff80c84df68c25887decb"},{"sha":"d10bcd473301888f957ec4b6b12aa3621be78d59","author":{"email":"b913f13ef92ac157955c954ccaaff7be065faba4@arm.com","name":"Will Deacon"},"message":"arm64: head.S: initialise mdcr_el2 in el2_setup\n\nWhen entering the kernel at EL2, we fail to initialise the MDCR_EL2\nregister which controls debug access and PMU capabilities at EL1.\n\nThis patch ensures that the register is initialised so that all traps\nare disabled and all the PMU counters are available to the host. When a\nguest is scheduled, KVM takes care to configure trapping appropriately.\n\nCc: <stable@vger.kernel.org>\nAcked-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/d10bcd473301888f957ec4b6b12aa3621be78d59"},{"sha":"8453fecbecae26edb3f278627376caab05d9a88d","author":{"email":"808efd45667dbd241e4e026b5673172419ecb43e@redhat.com","name":"Jason Wang"},"message":"kvm: don't try to register to KVM_FAST_MMIO_BUS for non mmio eventfd\n\nWe only want zero length mmio eventfd to be registered on\nKVM_FAST_MMIO_BUS. So check this explicitly when arg->len is zero to\nmake sure this.\n\nCc: stable@vger.kernel.org\nCc: Gleb Natapov <gleb@kernel.org>\nCc: Paolo Bonzini <pbonzini@redhat.com>\nSigned-off-by: Jason Wang <jasowang@redhat.com>\nReviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/8453fecbecae26edb3f278627376caab05d9a88d"},{"sha":"85da11ca587c8eb73993a1b503052391a73586f9","author":{"email":"808efd45667dbd241e4e026b5673172419ecb43e@redhat.com","name":"Jason Wang"},"message":"kvm: factor out core eventfd assign/deassign logic\n\nThis patch factors out core eventfd assign/deassign logic and leaves\nthe argument checking and bus index selection to callers.\n\nCc: stable@vger.kernel.org\nCc: Gleb Natapov <gleb@kernel.org>\nCc: Paolo Bonzini <pbonzini@redhat.com>\nSigned-off-by: Jason Wang <jasowang@redhat.com>\nReviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/85da11ca587c8eb73993a1b503052391a73586f9"},{"sha":"eefd6b06b17c5478e7c24bea6f64beaa2c431ca6","author":{"email":"808efd45667dbd241e4e026b5673172419ecb43e@redhat.com","name":"Jason Wang"},"message":"kvm: fix double free for fast mmio eventfd\n\nWe register wildcard mmio eventfd on two buses, once for KVM_MMIO_BUS\nand once on KVM_FAST_MMIO_BUS but with a single iodev\ninstance. This will lead to an issue: kvm_io_bus_destroy() knows\nnothing about the devices on two buses pointing to a single dev. Which\nwill lead to double free[1] during exit. Fix this by allocating two\ninstances of iodevs then registering one on KVM_MMIO_BUS and another\non KVM_FAST_MMIO_BUS.\n\nCPU: 1 PID: 2894 Comm: qemu-system-x86 Not tainted 3.19.0-26-generic #28-Ubuntu\nHardware name: LENOVO 2356BG6/2356BG6, BIOS G7ET96WW (2.56 ) 09/12/2013\ntask: ffff88009ae0c4b0 ti: ffff88020e7f0000 task.ti: ffff88020e7f0000\nRIP: 0010:[<ffffffffc07e25d8>]  [<ffffffffc07e25d8>] ioeventfd_release+0x28/0x60 [kvm]\nRSP: 0018:ffff88020e7f3bc8  EFLAGS: 00010292\nRAX: dead000000200200 RBX: ffff8801ec19c900 RCX: 000000018200016d\nRDX: ffff8801ec19cf80 RSI: ffffea0008bf1d40 RDI: ffff8801ec19c900\nRBP: ffff88020e7f3bd8 R08: 000000002fc75a01 R09: 000000018200016d\nR10: ffffffffc07df6ae R11: ffff88022fc75a98 R12: ffff88021e7cc000\nR13: ffff88021e7cca48 R14: ffff88021e7cca50 R15: ffff8801ec19c880\nFS:  00007fc1ee3e6700(0000) GS:ffff88023e240000(0000) knlGS:0000000000000000\nCS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033\nCR2: 00007f8f389d8000 CR3: 000000023dc13000 CR4: 00000000001427e0\nStack:\nffff88021e7cc000 0000000000000000 ffff88020e7f3be8 ffffffffc07e2622\nffff88020e7f3c38 ffffffffc07df69a ffff880232524160 ffff88020e792d80\n 0000000000000000 ffff880219b78c00 0000000000000008 ffff8802321686a8\nCall Trace:\n[<ffffffffc07e2622>] ioeventfd_destructor+0x12/0x20 [kvm]\n[<ffffffffc07df69a>] kvm_put_kvm+0xca/0x210 [kvm]\n[<ffffffffc07df818>] kvm_vcpu_release+0x18/0x20 [kvm]\n[<ffffffff811f69f7>] __fput+0xe7/0x250\n[<ffffffff811f6bae>] ____fput+0xe/0x10\n[<ffffffff81093f04>] task_work_run+0xd4/0xf0\n[<ffffffff81079358>] do_exit+0x368/0xa50\n[<ffffffff81082c8f>] ? recalc_sigpending+0x1f/0x60\n[<ffffffff81079ad5>] do_group_exit+0x45/0xb0\n[<ffffffff81085c71>] get_signal+0x291/0x750\n[<ffffffff810144d8>] do_signal+0x28/0xab0\n[<ffffffff810f3a3b>] ? do_futex+0xdb/0x5d0\n[<ffffffff810b7028>] ? __wake_up_locked_key+0x18/0x20\n[<ffffffff810f3fa6>] ? SyS_futex+0x76/0x170\n[<ffffffff81014fc9>] do_notify_resume+0x69/0xb0\n[<ffffffff817cb9af>] int_signal+0x12/0x17\nCode: 5d c3 90 0f 1f 44 00 00 55 48 89 e5 53 48 89 fb 48 83 ec 08 48 8b 7f 20 e8 06 d6 a5 c0 48 8b 43 08 48 8b 13 48 89 df 48 89 42 08 <48> 89 10 48 b8 00 01 10 00 00\n RIP  [<ffffffffc07e25d8>] ioeventfd_release+0x28/0x60 [kvm]\n RSP <ffff88020e7f3bc8>\n\nCc: stable@vger.kernel.org\nCc: Gleb Natapov <gleb@kernel.org>\nCc: Paolo Bonzini <pbonzini@redhat.com>\nSigned-off-by: Jason Wang <jasowang@redhat.com>\nReviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/eefd6b06b17c5478e7c24bea6f64beaa2c431ca6"},{"sha":"8f4216c7d28976f7ec1b2bcbfa0a9f787133c45e","author":{"email":"808efd45667dbd241e4e026b5673172419ecb43e@redhat.com","name":"Jason Wang"},"message":"kvm: fix zero length mmio searching\n\nCurrently, if we had a zero length mmio eventfd assigned on\nKVM_MMIO_BUS. It will never be found by kvm_io_bus_cmp() since it\nalways compares the kvm_io_range() with the length that guest\nwrote. This will cause e.g for vhost, kick will be trapped by qemu\nuserspace instead of vhost. Fixing this by using zero length if an\niodevice is zero length.\n\nCc: stable@vger.kernel.org\nCc: Gleb Natapov <gleb@kernel.org>\nCc: Paolo Bonzini <pbonzini@redhat.com>\nSigned-off-by: Jason Wang <jasowang@redhat.com>\nReviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/8f4216c7d28976f7ec1b2bcbfa0a9f787133c45e"},{"sha":"da92b4eb7e2ec9866f14a0c8f453788e8052dee7","author":{"email":"68ee766e574f18b34b683085865827393efe88bd@linux.intel.com","name":"Jiang Liu"},"message":"powerpc, irq: Use access helper irq_data_get_affinity_mask()\n\nUse access helper irq_data_get_affinity_mask() so we can move the\naffinity mask to irq_common_data.\n\nSigned-off-by: Jiang Liu <jiang.liu@linux.intel.com>\nCc: Benjamin Herrenschmidt <benh@kernel.crashing.org>\nCc: Michael Ellerman <mpe@ellerman.id.au>\nCc: linuxppc-dev@lists.ozlabs.org\nLink: http://lkml.kernel.org/r/1433145945-789-25-git-send-email-jiang.liu@linux.intel.com\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/da92b4eb7e2ec9866f14a0c8f453788e8052dee7"},{"sha":"dc2ec62f75fd9be78d07b3b453aeb0d201ead419","author":{"email":"00e4cf8f46a57000a44449bf9dd8cbbcc209fd2a@linutronix.de","name":"Thomas Gleixner"},"message":"net/mlx4_en: Use access helper irq_data_get_affinity_mask()\n\nThis is a preparatory patch for moving irq_data struct members. Search\nand replace was done with coccinelle\n\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>\nCc: Julia Lawall <Julia.Lawall@lip6.fr>\nCc: Jiang Liu <jiang.liu@linux.intel.com>\nCc: Amir Vadai <amirv@mellanox.com>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/dc2ec62f75fd9be78d07b3b453aeb0d201ead419"},{"sha":"e4084a16bbe07957811c75dfb7c9bf25c5862ba0","author":{"email":"a16cc0c82647c52d401177f8e50567df5499e36c@arm.com","name":"Marc Zyngier"},"message":"platform-msi: Do not cache msi_desc in handler_data\n\nThe current implementation of platform MSI caches the msi_desc\npointer in irq_data::handler_data. This is a bit silly, as\nwe also have irq_data::msi_desc, which is perfectly valid.\n\nRemove the useless assignment and simplify the whole flow.\n\nReported-by: Ma Jun <majun258@huawei.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>\nReviewed-by: Jiang Liu <jiang.liu@linux.intel.com>\nLink: http://lkml.kernel.org/r/1442147824-20971-1-git-send-email-marc.zyngier@arm.com\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/e4084a16bbe07957811c75dfb7c9bf25c5862ba0"},{"sha":"12e14066f4835f5ee1ca795f0309415b54c067a9","author":{"email":"a16cc0c82647c52d401177f8e50567df5499e36c@arm.com","name":"Marc Zyngier"},"message":"irqchip/GIC: Add workaround for aliased GIC400\n\nThe GICv2 architecture mandates that the two 4kB GIC regions are\ncontiguous, and on two separate physical pages (so that access to\nthe second page can be trapped by a hypervisor). This doesn't work\nvery well when PAGE_SIZE is 64kB.\n\nA relatively common hack^Wway to work around this is to alias each\n4kB region over its own 64kB page. Of course in this case, the base\naddress you want to use is not really the begining of the region,\nbut base + 60kB (so that you get a contiguous 8kB region over two\ndistinct pages).\n\nNormally, this would be described in DT with a new property, but\nsome HW is already out there, and the firmware makes sure that\nit will override whatever you put in the GIC node. Duh. And of course,\nsaid firmware source code is not available, despite being based\non u-boot.\n\nThe workaround is to detect the case where the CPU interface size\nis set to 128kB, and verify the aliasing by checking that the ID\nregister for GIC400 (which is the only GIC wired this way so far)\nis the same at base and base + 0xF000. In this case, we update\nthe GIC base address and let it roll.\n\nAnd if you feel slightly sick by looking at this, rest assured that\nI do too...\n\nReported-by: Julien Grall <julien.grall@citrix.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>\nCc: linux-arm-kernel@lists.infradead.org\nCc: Stuart Yoder <stuart.yoder@freescale.com>\nCc: Pavel Fedin <p.fedin@samsung.com>\nCc: Jason Cooper <jason@lakedaemon.net>\nLink: http://lkml.kernel.org/r/1442142873-20213-2-git-send-email-marc.zyngier@arm.com\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/12e14066f4835f5ee1ca795f0309415b54c067a9"},{"sha":"5a9a8915c8888b615521b17d70a4342187eae60b","author":{"email":"a16cc0c82647c52d401177f8e50567df5499e36c@arm.com","name":"Marc Zyngier"},"message":"irqchip/gic-v3-its: Add missing cache flushes\n\nWhen the ITS is configured for non-cacheable transactions, make sure\nthat the allocated, zeroed memory is flushed to the Point of\nCoherency, allowing the ITS to observe the zeros instead of random\ngarbage (or even get its own data overwritten by zeros being evicted\nfrom the cache...).\n\nFixes: 241a386c7dbb \"irqchip: gicv3-its: Use non-cacheable accesses when no shareability\"\nReported-and-tested-by: Stuart Yoder <stuart.yoder@freescale.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>\nCc: linux-arm-kernel@lists.infradead.org\nCc: Pavel Fedin <p.fedin@samsung.com>\nCc: Jason Cooper <jason@lakedaemon.net>\nLink: http://lkml.kernel.org/r/1442142873-20213-3-git-send-email-marc.zyngier@arm.com\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/5a9a8915c8888b615521b17d70a4342187eae60b"},{"sha":"157add60cb35913b8a848a3d7e6456b8ed134796","author":{"email":"8021705951b47b55cfb09d1ff23e995dd363984f@samsung.com","name":"Pavel Fedin"},"message":"irqchip/GICv2m: Fix GICv2m build warning on 32 bits\n\nAfter GICv2m was enabled for 32-bit ARM kernel, a warning popped up:\n\ndrivers/irqchip/irq-gic-v2m.c: In function gicv2m_compose_msi_msg:\ndrivers/irqchip/irq-gic-v2m.c:100:2: warning: right shift count >= width\nof type [enabled by default]\n  msg->address_hi = (u32) (addr >> 32);\n  ^\n\nThis patch fixes it by using proper macros for splitting up the value.\n\nSigned-off-by: Pavel Fedin <p.fedin@samsung.com>\nReviewed-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>\nCc: linux-arm-kernel@lists.infradead.org\nCc: Stuart Yoder <stuart.yoder@freescale.com>\nCc: Jason Cooper <jason@lakedaemon.net>\nLink: http://lkml.kernel.org/r/1442142873-20213-4-git-send-email-marc.zyngier@arm.com\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/157add60cb35913b8a848a3d7e6456b8ed134796"},{"sha":"b1370658804510f6a1c0517a8ff1c9534d371edd","author":{"email":"a1ff81395f7e6bf5b509fe9aab06bf3419493e1d@glider.be","name":"Geert Uytterhoeven"},"message":"irqchip/renesas-irqc: Use a separate lockdep class\n\nThe renesas-irqc interrupt controller is cascaded to the GIC. Hence when\npropagating wake-up settings to its parent interrupt controller, the\nfollowing lockdep warning is printed:\n\n    =============================================\n    [ INFO: possible recursive locking detected ]\n    4.2.0-ape6evm-10725-g50fcd7643c034198 #280 Not tainted\n    ---------------------------------------------\n    s2ram/1072 is trying to acquire lock:\n    (&irq_desc_lock_class){-.-...}, at: [<c008d3fc>] __irq_get_desc_lock+0x58/0x98\n\n    but task is already holding lock:\n    (&irq_desc_lock_class){-.-...}, at: [<c008d3fc>] __irq_get_desc_lock+0x58/0x98\n\n    other info that might help us debug this:\n    Possible unsafe locking scenario:\n\n\t  CPU0\n\t  ----\n     lock(&irq_desc_lock_class);\n     lock(&irq_desc_lock_class);\n\n    *** DEADLOCK ***\n\n    May be due to missing lock nesting notation\n\n    6 locks held by s2ram/1072:\n    #0:  (sb_writers#7){.+.+.+}, at: [<c012eb14>] __sb_start_write+0xa0/0xa8\n    #1:  (&of->mutex){+.+.+.}, at: [<c019396c>] kernfs_fop_write+0x4c/0x1bc\n    #2:  (s_active#24){.+.+.+}, at: [<c0193974>] kernfs_fop_write+0x54/0x1bc\n    #3:  (pm_mutex){+.+.+.}, at: [<c008213c>] pm_suspend+0x10c/0x510\n    #4:  (&dev->mutex){......}, at: [<c02af3c4>] __device_suspend+0xdc/0x2cc\n    #5:  (&irq_desc_lock_class){-.-...}, at: [<c008d3fc>] __irq_get_desc_lock+0x58/0x98\n\n    stack backtrace:\n    CPU: 0 PID: 1072 Comm: s2ram Not tainted 4.2.0-ape6evm-10725-g50fcd7643c034198 #280\n    Hardware name: Generic R8A73A4 (Flattened Device Tree)\n    [<c0018078>] (unwind_backtrace) from [<c00144f0>] (show_stack+0x10/0x14)\n    [<c00144f0>] (show_stack) from [<c0451f14>] (dump_stack+0x88/0x98)\n    [<c0451f14>] (dump_stack) from [<c007b29c>] (__lock_acquire+0x15cc/0x20e4)\n    [<c007b29c>] (__lock_acquire) from [<c007c6e0>] (lock_acquire+0xac/0x12c)\n    [<c007c6e0>] (lock_acquire) from [<c0457c00>] (_raw_spin_lock_irqsave+0x40/0x54)\n    [<c0457c00>] (_raw_spin_lock_irqsave) from [<c008d3fc>] (__irq_get_desc_lock+0x58/0x98)\n    [<c008d3fc>] (__irq_get_desc_lock) from [<c008ebbc>] (irq_set_irq_wake+0x20/0xf8)\n    [<c008ebbc>] (irq_set_irq_wake) from [<c0260770>] (irqc_irq_set_wake+0x20/0x4c)\n    [<c0260770>] (irqc_irq_set_wake) from [<c008ec28>] (irq_set_irq_wake+0x8c/0xf8)\n    [<c008ec28>] (irq_set_irq_wake) from [<c02cb8c0>] (gpio_keys_suspend+0x74/0xc0)\n    [<c02cb8c0>] (gpio_keys_suspend) from [<c02ae8cc>] (dpm_run_callback+0x54/0x124)\n\nAvoid this false positive by using a separate lockdep class for IRQC\ninterrupts.\n\nSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>\nCc: Grygorii Strashko <grygorii.strashko@ti.com>\nCc: Magnus Damm <magnus.damm@gmail.com>\nCc: Jason Cooper <jason@lakedaemon.net>\nLink: http://lkml.kernel.org/r/1441798974-25716-2-git-send-email-geert%2Brenesas@glider.be\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/b1370658804510f6a1c0517a8ff1c9534d371edd"},{"sha":"769b5cf78e6c653c2f513649ee6c4e7a06723872","author":{"email":"a1ff81395f7e6bf5b509fe9aab06bf3419493e1d@glider.be","name":"Geert Uytterhoeven"},"message":"irqchip/renesas-intc-irqpin: Use a separate lockdep class\n\nThe renesas-intc-irqpin interrupt controller is cascaded to the GIC.\nHence when propagating wake-up settings to its parent interrupt\ncontroller, the following lockdep warning is printed:\n\n    =============================================\n    [ INFO: possible recursive locking detected ]\n    4.2.0-armadillo-10725-g50fcd7643c034198 #781 Not tainted\n    ---------------------------------------------\n    s2ram/1179 is trying to acquire lock:\n    (&irq_desc_lock_class){-.-...}, at: [<c005bb54>] __irq_get_desc_lock+0x78/0x94\n\n    but task is already holding lock:\n    (&irq_desc_lock_class){-.-...}, at: [<c005bb54>] __irq_get_desc_lock+0x78/0x94\n\n    other info that might help us debug this:\n    Possible unsafe locking scenario:\n\n\t  CPU0\n\t  ----\n     lock(&irq_desc_lock_class);\n     lock(&irq_desc_lock_class);\n\n    *** DEADLOCK ***\n\n    May be due to missing lock nesting notation\n\n    7 locks held by s2ram/1179:\n    #0:  (sb_writers#7){.+.+.+}, at: [<c00c9708>] __sb_start_write+0x64/0xb8\n    #1:  (&of->mutex){+.+.+.}, at: [<c0125a00>] kernfs_fop_write+0x78/0x1a0\n    #2:  (s_active#23){.+.+.+}, at: [<c0125a08>] kernfs_fop_write+0x80/0x1a0\n    #3:  (autosleep_lock){+.+.+.}, at: [<c0058244>] pm_autosleep_lock+0x18/0x20\n    #4:  (pm_mutex){+.+.+.}, at: [<c0057e50>] pm_suspend+0x54/0x248\n    #5:  (&dev->mutex){......}, at: [<c0243a20>] __device_suspend+0xdc/0x240\n    #6:  (&irq_desc_lock_class){-.-...}, at: [<c005bb54>] __irq_get_desc_lock+0x78/0x94\n\n    stack backtrace:\n    CPU: 0 PID: 1179 Comm: s2ram Not tainted 4.2.0-armadillo-10725-g50fcd7643c034198\n\n    Hardware name: Generic R8A7740 (Flattened Device Tree)\n    [<c00129f4>] (dump_backtrace) from [<c0012bec>] (show_stack+0x18/0x1c)\n    [<c0012bd4>] (show_stack) from [<c03f5d94>] (dump_stack+0x20/0x28)\n    [<c03f5d74>] (dump_stack) from [<c00514d4>] (__lock_acquire+0x67c/0x1b88)\n    [<c0050e58>] (__lock_acquire) from [<c0052df8>] (lock_acquire+0x9c/0xbc)\n    [<c0052d5c>] (lock_acquire) from [<c03fb068>] (_raw_spin_lock_irqsave+0x44/0x58)\n    [<c03fb024>] (_raw_spin_lock_irqsave) from [<c005bb54>] (__irq_get_desc_lock+0x78/0x94\n    [<c005badc>] (__irq_get_desc_lock) from [<c005c3d8>] (irq_set_irq_wake+0x28/0x100)\n    [<c005c3b0>] (irq_set_irq_wake) from [<c01e50d0>] (intc_irqpin_irq_set_wake+0x24/0x4c)\n    [<c01e50ac>] (intc_irqpin_irq_set_wake) from [<c005c17c>] (set_irq_wake_real+0x3c/0x50\n    [<c005c140>] (set_irq_wake_real) from [<c005c414>] (irq_set_irq_wake+0x64/0x100)\n    [<c005c3b0>] (irq_set_irq_wake) from [<c02a19b4>] (gpio_keys_suspend+0x60/0xa0)\n    [<c02a1954>] (gpio_keys_suspend) from [<c023b750>] (platform_pm_suspend+0x3c/0x5c)\n\nAvoid this false positive by using a separate lockdep class for INTC\nExternal IRQ Pin interrupts.\n\nSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>\nCc: Grygorii Strashko <grygorii.strashko@ti.com>\nCc: Magnus Damm <magnus.damm@gmail.com>\nCc: Jason Cooper <jason@lakedaemon.net>\nLink: http://lkml.kernel.org/r/1441798974-25716-3-git-send-email-geert%2Brenesas@glider.be\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/769b5cf78e6c653c2f513649ee6c4e7a06723872"},{"sha":"f4e209cdc7a00f934007f40cf885471799073b0d","author":{"email":"a1ff81395f7e6bf5b509fe9aab06bf3419493e1d@glider.be","name":"Geert Uytterhoeven"},"message":"irqchip/renesas-intc-irqpin: Propagate wake-up settings to parent\n\nThe renesas-intc-irqpin interrupt controller is cascaded to the GIC, but\nits driver doesn't propagate wake-up settings to the parent interrupt\ncontroller.\n\nSince commit aec89ef72ba6c944 (\"irqchip/gic: Enable SKIP_SET_WAKE and\nMASK_ON_SUSPEND\"), the GIC driver masks interrupts during suspend, and\nwake-up through gpio-keys now fails on r8a7740/armadillo and\nsh73a0/kzm9g.\n\nFix this by propagating wake-up settings to the parent interrupt\ncontroller. There's no need to handle irq_set_irq_wake() failures, as\nthe renesas-intc-irqpin interrupt controller is always cascaded to a\nGIC, and the GIC driver always sets SKIP_SET_WAKE since the\naforementioned commit.\n\nSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>\nCc: Sudeep Holla <sudeep.holla@arm.com>\nCc: Magnus Damm <magnus.damm@gmail.com>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Marc Zyngier <marc.zyngier@arm.com>\nLink: http://lkml.kernel.org/r/1441731636-17610-2-git-send-email-geert%2Brenesas@glider.be\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/f4e209cdc7a00f934007f40cf885471799073b0d"},{"sha":"4cd7863ecb90010533c178fba6ecc84d5529b402","author":{"email":"a1ff81395f7e6bf5b509fe9aab06bf3419493e1d@glider.be","name":"Geert Uytterhoeven"},"message":"irqchip/renesas-irqc: Propagate wake-up settings to parent\n\nThe renesas-irqc interrupt controller is cascaded to the GIC, but its\ndriver doesn't propagate wake-up settings to the parent interrupt\ncontroller.\n\nSince commit aec89ef72ba6c944 (\"irqchip/gic: Enable SKIP_SET_WAKE and\nMASK_ON_SUSPEND\"), the GIC driver masks interrupts during suspend, and\nwake-up through gpio-keys now fails on r8a73a4/ape6evm.\n\nFix this by propagating wake-up settings to the parent interrupt\ncontroller. There's no need to handle irq_set_irq_wake() failures, as\nthe renesas-irqc interrupt controller is always cascaded to a GIC, and\nthe GIC driver always sets SKIP_SET_WAKE since the aforementioned\ncommit.\n\nSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>\nCc: Sudeep Holla <sudeep.holla@arm.com>\nCc: Magnus Damm <magnus.damm@gmail.com>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Marc Zyngier <marc.zyngier@arm.com>\nLink: http://lkml.kernel.org/r/1441731636-17610-3-git-send-email-geert%2Brenesas@glider.be\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/4cd7863ecb90010533c178fba6ecc84d5529b402"},{"sha":"3829c664b1eec243f2a355829efa40f0f414de8d","author":{"email":"00e4cf8f46a57000a44449bf9dd8cbbcc209fd2a@linutronix.de","name":"Thomas Gleixner"},"message":"genirq: Remove stale comment\n\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/3829c664b1eec243f2a355829efa40f0f414de8d"},{"sha":"6584d84c3e504c76ad291cc2e381bbeed59798ab","author":{"email":"e95201b3dedc55fa134e790f35b68c6a0e799b94@arm.com","name":"Huang Shijie"},"message":"genirq: Update the comment for generic_handle_irq_desc\n\n__do_IRQ() was removed by commit 1c77ff2 \"genirq: Remove __do_IRQ\",\nbut the comment referring to __do_IRQ() was left.\n\nUpdate the comment for generic_handle_irq_desc().\n\nSigned-off-by: Huang Shijie <shijie.huang@arm.com>\nCc: jiang.liu@linux.intel.com\nCc: peterz@infradead.org\nCc: rafael.j.wysocki@intel.com\nCc: jason@lakedaemon.net\nCc: marc.zyngier@arm.com\nLink: http://lkml.kernel.org/r/1441074950-3893-1-git-send-email-shijie.huang@arm.com\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/joergroedel/linux-iommu/commits/6584d84c3e504c76ad291cc2e381bbeed59798ab"}]}