{"push_id":769688607,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"af7c00f21360208a4f87a1bcd01f5f268037e1b7","before":"b6566b103fac04e33fbf12b95ca9fb49295da791","commits":[{"sha":"af7c00f21360208a4f87a1bcd01f5f268037e1b7","author":{"email":"4a8dfeb3a1c6b90c15fd5a5a91e8e25ea46ffe0b@rotateright.com","name":"Sanjay Patel"},"message":"make fast unaligned memory accesses implicit with SSE4.2 or SSE4a\n\nThis is a follow-on from the discussion in http://reviews.llvm.org/D12154.\n\nThis change allows memset/memcpy to use SSE or AVX memory accesses for any chip that has\ngenerally fast unaligned memory ops.\n\nA motivating use case for this change is a clang invocation that doesn't explicitly set\nthe CPU, but does target a feature that we know only exists on a CPU that supports fast\nunaligned memops. For example:\n$ clang -O1 foo.c -mavx\n\nThis resolves a difference in lowering noted in PR24449:\nhttps://llvm.org/bugs/show_bug.cgi?id=24449\n\nBefore this patch, we used different store types depending on whether the example can be\nlowered as a memset or not.\n\nDifferential Revision: http://reviews.llvm.org/D12288\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245950 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/af7c00f21360208a4f87a1bcd01f5f268037e1b7"}]}