{"action":"created","comment":{"url":"https://api.github.com/repos/mbedmicro/pyOCD/pulls/comments/47971199","id":47971199,"diff_hunk":"@@ -876,11 +665,15 @@ def readCoreRegistersRaw(self, reg_list):\n         reg_vals = []\n         for reg, reg_cb, dhcsr_cb in zip(reg_list, reg_cb_list, dhcsr_cb_list):\n             dhcsr_val = dhcsr_cb()\n-            assert dhcsr_val & CortexM.S_REGRDY\n+#            assert dhcsr_val & CortexM.S_REGRDY\n             val = reg_cb()\n \n-            # Special handling for registers that are combined\n-            # into a single DCRSR number.\n+            # If we couldn't read the register, stuff a dummy zero in the return value list.\n+            if (dhcsr_val & CortexM.S_REGRDY) == 0:\n+                reg_vals.append(0)","path":"pyOCD/coresight/cortex_m.py","position":572,"original_position":572,"commit_id":"d2abcce416d50b8c2fbf1de4627d8d9502a27060","original_commit_id":"d2abcce416d50b8c2fbf1de4627d8d9502a27060","user":{"login":"c1728p9","id":2916772,"avatar_url":"https://avatars.githubusercontent.com/u/2916772?v=3","gravatar_id":"","url":"https://api.github.com/users/c1728p9","html_url":"https://github.com/c1728p9","followers_url":"https://api.github.com/users/c1728p9/followers","following_url":"https://api.github.com/users/c1728p9/following{/other_user}","gists_url":"https://api.github.com/users/c1728p9/gists{/gist_id}","starred_url":"https://api.github.com/users/c1728p9/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/c1728p9/subscriptions","organizations_url":"https://api.github.com/users/c1728p9/orgs","repos_url":"https://api.github.com/users/c1728p9/repos","events_url":"https://api.github.com/users/c1728p9/events{/privacy}","received_events_url":"https://api.github.com/users/c1728p9/received_events","type":"User","site_admin":false},"body":"Instead of adding a dummy value here, could an exception be raised?  The calling code could then catch the appropriate exception if they want to be able to recover from this.","created_at":"2015-12-17T22:33:40Z","updated_at":"2015-12-17T22:33:40Z","html_url":"https://github.com/mbedmicro/pyOCD/pull/216#discussion_r47971199","pull_request_url":"https://api.github.com/repos/mbedmicro/pyOCD/pulls/216","_links":{"self":{"href":"https://api.github.com/repos/mbedmicro/pyOCD/pulls/comments/47971199"},"html":{"href":"https://github.com/mbedmicro/pyOCD/pull/216#discussion_r47971199"},"pull_request":{"href":"https://api.github.com/repos/mbedmicro/pyOCD/pulls/216"}}},"pull_request":{"url":"https://api.github.com/repos/mbedmicro/pyOCD/pulls/216","id":52879614,"html_url":"https://github.com/mbedmicro/pyOCD/pull/216","diff_url":"https://github.com/mbedmicro/pyOCD/pull/216.diff","patch_url":"https://github.com/mbedmicro/pyOCD/pull/216.patch","issue_url":"https://api.github.com/repos/mbedmicro/pyOCD/issues/216","number":216,"state":"open","locked":false,"title":"Architectural refactoring","user":{"login":"flit","id":3116536,"avatar_url":"https://avatars.githubusercontent.com/u/3116536?v=3","gravatar_id":"","url":"https://api.github.com/users/flit","html_url":"https://github.com/flit","followers_url":"https://api.github.com/users/flit/followers","following_url":"https://api.github.com/users/flit/following{/other_user}","gists_url":"https://api.github.com/users/flit/gists{/gist_id}","starred_url":"https://api.github.com/users/flit/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/flit/subscriptions","organizations_url":"https://api.github.com/users/flit/orgs","repos_url":"https://api.github.com/users/flit/repos","events_url":"https://api.github.com/users/flit/events{/privacy}","received_events_url":"https://api.github.com/users/flit/received_events","type":"User","site_admin":false},"body":"Fairly significant changes to re-architect pyOCD's target and Cortex-M related code.\r\n\r\n- Created new pyOCD.coresight submodule. It has DebugPort and AccessPort classes, as well as classes for CortexM, FPB, DWT, breakpoints, and ROM table parsing.\r\n- CortexM class moved to pyOCD.coresight and simplified by using other coresight component classes such as AHB_AP and the breakpoints classes.\r\n- New CoreSightTarget subclass of Target that owns the DebugPort, AccessPort, and CortexM classes. It supports multiple cores. The existing target classes are now subclasses of CoreSightTarget rather than CortexM.\r\n- Factored breakpoints code that was in CortexM into a BreakpointsManager class and related classes.\r\n- CoreSight ROM tables are parsed during init, although they are not yet used to construct objects.\r\n- Additional CPU states are supported: reset, lockup, and sleep.\r\n- Debug resources are disabled and debug is powered down upon disconnect.\r\n- Memory reads are filtered to hide software breakpoints.\r\n\r\nThis changeset also includes some miscellaneous changes, as well:\r\n- pyocd-tool can execute arbitrary Python expressions via a \"$<python code>\" syntax.\r\n- Added \"core\" command to pyocd-tool to select the current core.\r\n- SVD files are associated with targets and the registers can be accessed via pyocd-tool.\r\n- hidapi USB backend was improved to fix issues with multiple connected boards and when another process already has a board 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