{"action":"created","comment":{"url":"https://api.github.com/repos/vecnatechnologies/rtems/pulls/comments/39892509","id":39892509,"diff_hunk":"@@ -0,0 +1,664 @@\n+/**\n+ * @file hal-can.c\n+ *\n+ * @ingroup can\n+ *\n+ * @brief CAN driver for the STM32xxxx series processors. Provides a \n+ * CAN driver that registers with cpukit/dev/can as a node in the \n+ * filesystem.\n+ *\n+ */\n+\n+/*\n+ * Copyright (c) 2015 Vecna Technologies, Inc.\n+ *\n+ * The license and distribution terms for this file may be\n+ * found in the file LICENSE in this distribution or at\n+ * http://www.rtems.com/license/LICENSE.\n+ */\n+\n+//================== STMF32 Support Functions =================================\n+#include <hal-can.h>\n+#include <dev/can/can-internal.h>\n+#include <rtems.h>\n+#include <hal-utils.h>\n+#include <stm32f-processor-specific.h>\n+\n+#include stm_processor_header(TARGET_STM_PROCESSOR_PREFIX)\n+#include stm_header(TARGET_STM_PROCESSOR_PREFIX, can)\n+#include stm_header(TARGET_STM_PROCESSOR_PREFIX, rcc)\n+#include stm_header(TARGET_STM_PROCESSOR_PREFIX, gpio)\n+\n+#include <math.h>\n+#include <rtems/irq-extension.h>\n+\n+// Internal functions to perform RX and TX\n+static int                stm32_can_init              (can_bus * self, long baudRate);\n+static int                stm32_can_de_init           (can_bus * self);\n+static void               stm32_can_gpio_init         (CAN_Instance canInstance);\n+static CAN_Timing_Values  rtems_can_get_timing_values (uint32_t desired_baud);\n+static CAN_Status         stm32_can_start_tx          (CAN_HandleTypeDef* hCanHandle, can_msg * msg);\n+static CAN_Status         stm32_can_start_rx          (CAN_HandleTypeDef *hCanHandle);\n+// Tasks\n+static rtems_task         stm32_rx_task               (rtems_task_argument arg);\n+static rtems_task         stm32_tx_task               (rtems_task_argument arg);\n+// ISRs\n+static void               stm32_can_isr               (void * arg);\n+static void               stm32_can_rx0_isr           (void * arg);\n+static void               stm32_can_rx1_isr           (void * arg);\n+\n+typedef struct stm32_can_bus stm32_can_bus;\n+typedef struct HandleWrapper HandleWrapper;\n+\n+struct HandleWrapper {\n+  CAN_HandleTypeDef handle;\n+  stm32_can_bus * bus;\n+};\n+\n+struct stm32_can_bus {\n+  can_bus base;\n+  HandleWrapper wrapper;\n+  CAN_Instance instance;\n+  CanTxMsgTypeDef TxMessage;\n+  CanRxMsgTypeDef RxMessage;\n+};\n+\n+/* Definition for CAN1 Pins */\n+//TODO Make this configurable and work for F7\n+#define CAN1_TX_PIN                    GPIO_PIN_9\n+#define CAN1_RX_PIN                    GPIO_PIN_8\n+#define CAN1_GPIO_PORT                 GPIOB\n+#define CAN1_AF                        GPIO_AF9_CAN1\n+\n+\n+/* Definition for CAN2 Pins */\n+#define CAN2_TX_PIN                    GPIO_PIN_6\n+#define CAN2_RX_PIN                    GPIO_PIN_5\n+#define CAN2_GPIO_PORT                 GPIOB\n+#define CAN2_AF                        GPIO_AF9_CAN2\n+\n+#define MAX_FILTERS                   14  \n+\n+CAN_Status stm32_can_start_tx\n+(\n+  CAN_HandleTypeDef* hCanHandle, \n+  can_msg * msg\n+)\n+{\n+  //TODO refactor this to not have so much STM32 stuff\n+  CAN_Status Status;\n+\n+  hCanHandle->pTxMsg->RTR     = CAN_RTR_DATA;\n+  hCanHandle->pTxMsg->IDE     = CAN_ID_STD;\n+\n+  hCanHandle->pTxMsg->StdId   = msg->id;\n+  hCanHandle->pTxMsg->DLC     = msg->len;\n+  memcpy(hCanHandle->pTxMsg->Data, msg->data, 8);\n+\n+  Status = HAL_CAN_Transmit_IT(hCanHandle);\n+  return Status;\n+}\n+\n+\n+CAN_Status stm32_can_start_rx\n+(\n+  CAN_HandleTypeDef *hCanHandle\n+)\n+{\n+  //TODO use both FIFOs\n+  CAN_Status Status;\n+  Status = HAL_CAN_Receive_IT(hCanHandle, 0);\n+  return Status;\n+}\n+\n+static int local_roundf\n+(\n+  float arg\n+)\n+{\n+  int ret = (int) arg;\n+\n+  if(arg > 0.0F) {\n+    if((arg - ret) >= 0.5) ret++;\n+  } else {\n+    if((arg - ret) <= -0.5) ret--;\n+  }\n+\n+  return ret;\n+}\n+\n+void HAL_CAN_RxCpltCallback\n+(\n+  CAN_HandleTypeDef *hCanHandle\n+)\n+{\n+  // Wakeup RX Task\n+  rtems_status_code sc;\n+  stm32_can_bus * bus = (((HandleWrapper *) hCanHandle)->bus);\n+  volatile int a;\n+  sc = rtems_event_transient_send(bus->base.rx_task_id);\n+  a++;\n+}\n+\n+\n+rtems_task stm32_rx_task\n+(\n+  rtems_task_argument arg\n+)\n+{\n+  rtems_status_code sc;\n+  can_msg msg;\n+  size_t len;\n+\n+  stm32_can_bus * bus = (stm32_can_bus *) arg;\n+  CAN_HandleTypeDef * hCanHandle = (CAN_HandleTypeDef * ) &bus->wrapper;\n+\n+  while (1) {\n+    // Schedule a read\n+    stm32_can_start_rx(hCanHandle);\n+\n+\n+\n+    // Wait for interrupt\n+    sc = rtems_event_transient_receive(RTEMS_WAIT, RTEMS_NO_TIMEOUT);\n+    _Assert(sc == RTEMS_SUCCESSFUL);\n+\n+    //TODO consider 29 bit ids\n+    msg.id = hCanHandle->pRxMsg->StdId;\n+    msg.len = hCanHandle->pRxMsg->DLC;\n+    memcpy(&msg.data, &hCanHandle->pRxMsg->Data, msg.len);\n+    // Pass message along to stack\n+    rtems_message_queue_send(bus->base.rx_msg_queue, &msg, sizeof(msg));\n+  }\n+}\n+\n+\n+rtems_task stm32_tx_task\n+(\n+  rtems_task_argument arg\n+)\n+{\n+  rtems_status_code sc;\n+  can_msg msg;\n+  size_t len;\n+\n+  stm32_can_bus * bus = (stm32_can_bus *) arg;\n+  CAN_HandleTypeDef * hCanHandle = &(bus->wrapper.handle);\n+  while (1) {\n+    //TODO abstract away into\n+    // can_msg_queue_receive\n+    sc = rtems_message_queue_receive( \n+        bus->base.tx_msg_queue, \n+        &msg,\n+        &len,\n+        RTEMS_WAIT,\n+        RTEMS_NO_TIMEOUT\n+      );\n+    _Assert(len == sizeof(msg));\n+\n+    stm32_can_start_tx(hCanHandle, &msg);\n+  }\n+}\n+\n+\n+void stm32_can_gpio_init\n+(\n+  CAN_Instance canInstance\n+)\n+{\n+  GPIO_InitTypeDef GPIO_InitStructure;\n+\n+  // Enable the clock CAN Core //\n+  __HAL_RCC_CAN1_CLK_ENABLE();\n+\n+  if (canInstance == CAN_TWO)\n+  {\n+    __HAL_RCC_CAN2_CLK_ENABLE();\t// CAN2 requires clock for CAN1 enabled too\n+  }\n+\n+  // CAN GPIO Clock Enable//\n+  __GPIOB_CLK_ENABLE();\n+","path":"c/src/lib/libbsp/arm/shared/stm32fxxxx/can/hal-can.c","position":221,"original_position":221,"commit_id":"5e40dce59652e108b87135c3ee2d1c9d882296a0","original_commit_id":"5e40dce59652e108b87135c3ee2d1c9d882296a0","user":{"login":"SudarshanRaj","id":10713663,"avatar_url":"https://avatars.githubusercontent.com/u/10713663?v=3","gravatar_id":"","url":"https://api.github.com/users/SudarshanRaj","html_url":"https://github.com/SudarshanRaj","followers_url":"https://api.github.com/users/SudarshanRaj/followers","following_url":"https://api.github.com/users/SudarshanRaj/following{/other_user}","gists_url":"https://api.github.com/users/SudarshanRaj/gists{/gist_id}","starred_url":"https://api.github.com/users/SudarshanRaj/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/SudarshanRaj/subscriptions","organizations_url":"https://api.github.com/users/SudarshanRaj/orgs","repos_url":"https://api.github.com/users/SudarshanRaj/repos","events_url":"https://api.github.com/users/SudarshanRaj/events{/privacy}","received_events_url":"https://api.github.com/users/SudarshanRaj/received_events","type":"User","site_admin":false},"body":"The GPIO port clock has to be enabled depending on the port and pins used. Also depending on which instance (if different instance uses different GPIO ports) ","created_at":"2015-09-18T19:32:05Z","updated_at":"2015-09-18T19:32:05Z","html_url":"https://github.com/vecnatechnologies/rtems/pull/4#discussion_r39892509","pull_request_url":"https://api.github.com/repos/vecnatechnologies/rtems/pulls/4","_links":{"self":{"href":"https://api.github.com/repos/vecnatechnologies/rtems/pulls/comments/39892509"},"html":{"href":"https://github.com/vecnatechnologies/rtems/pull/4#discussion_r39892509"},"pull_request":{"href":"https://api.github.com/repos/vecnatechnologies/rtems/pulls/4"}}},"pull_request":{"url":"https://api.github.com/repos/vecnatechnologies/rtems/pulls/4","id":45208791,"html_url":"https://github.com/vecnatechnologies/rtems/pull/4","diff_url":"https://github.com/vecnatechnologies/rtems/pull/4.diff","patch_url":"https://github.com/vecnatechnologies/rtems/pull/4.patch","issue_url":"https://api.github.com/repos/vecnatechnologies/rtems/issues/4","number":4,"state":"open","locked":false,"title":"Stm32 bsp rebase fixes","user":{"login":"igutekunst","id":657081,"avatar_url":"https://avatars.githubusercontent.com/u/657081?v=3","gravatar_id":"","url":"https://api.github.com/users/igutekunst","html_url":"https://github.com/igutekunst","followers_url":"https://api.github.com/users/igutekunst/followers","following_url":"https://api.github.com/users/igutekunst/following{/other_user}","gists_url":"https://api.github.com/users/igutekunst/gists{/gist_id}","starred_url":"https://api.github.com/users/igutekunst/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/igutekunst/subscriptions","organizations_url":"https://api.github.com/users/igutekunst/orgs","repos_url":"https://api.github.com/users/igutekunst/repos","events_url":"https://api.github.com/users/igutekunst/events{/privacy}","received_events_url":"https://api.github.com/users/igutekunst/received_events","type":"User","site_admin":false},"body":"This pull request includes the latest changes made by Vecna to master broken up into more reasonable commits for review.\r\n\r\nPlease ignore\r\n* Add STM32F4 HAL Files\r\n* Add STM32F7 HAL Files\r\n\r\nThis [Add STM32 Shared Files](https://github.com/vecnatechnologies/rtems/commit/c32676e4aea62f283eee7c8014a96b5b753c1da2) commit is the core of the BSP. It includes the implementation shared between the F4 and F7.\r\n\r\nThis commit: [Added STM32F7X and STM32F4X BSP ](https://github.com/vecnatechnologies/rtems/commit/da2c09cd582bc7995b3756119b39c1764efc02cd) creates two BSPs using the shared code and HAL code.\r\n\r\nThe Makefile.am files in both stm32f4x and stm32f7x directories list the files that are actually compiled into the BSP (in addition to the RTEMS core).\r\n\r\nThe later commits are addressing code review comments, adding I2C, and fixing additional errors. Code reviews will add new commits to this branch.\r\n\r\n","created_at":"2015-09-16T18:43:53Z","updated_at":"2015-09-18T19:32:05Z","closed_at":null,"merged_at":null,"merge_commit_sha":"8da64a94d03f9fdd950de158fdee7d0334a5e9ec","assignee":{"login":"igutekunst","id":657081,"avatar_url":"https://avatars.githubusercontent.com/u/657081?v=3","gravatar_id":"","url":"https://api.github.com/users/igutekunst","html_url":"https://github.com/igutekunst","followers_url":"https://api.github.com/users/igutekunst/followers","following_url":"https://api.github.com/users/igutekunst/following{/other_user}","gists_url":"https://api.github.com/users/igutekunst/gists{/gist_id}","starred_url":"https://api.github.com/users/igutekunst/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/igutekunst/subscriptions","organizations_url":"https://api.github.com/users/igutekunst/orgs","repos_url":"https://api.github.com/users/igutekunst/repos","events_url":"https://api.github.com/users/igutekunst/events{/privacy}","received_events_url":"https://api.github.com/users/igutekunst/received_events","type":"User","site_admin":false},"milestone":{"url":"https://api.github.com/repos/vecnatechnologies/rtems/milestones/1","html_url":"https://github.com/vecnatechnologies/rtems/milestones/RTEMS%20BSP%20Round%201","labels_url":"https://api.github.com/repos/vecnatechnologies/rtems/milestones/1/labels","id":1309059,"number":1,"title":"RTEMS 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