{"push_id":881288400,"size":17,"distinct_size":17,"ref":"refs/heads/master","head":"27a88a947c78c9af5eaeb6587fb5211057931d8c","before":"72c33f0dd5b8bdf2179d4221b29b375882af5042","commits":[{"sha":"22d2dda03be32d23bc8e9f5823a4f2469737ddbe","author":{"email":"242b79f0804cf52679d58f27ed754158c1323c75@amd.com","name":"Michel Dänzer"},"message":"targets/xvmc: use the non-inline sw helpers\n\nThis was missed in commit 59cfb21d (\"targets: use the non-inline sw\nhelpers\").\n\nFixes build failure:\n\n  CXXLD    libXvMCgallium.la\n../../../../src/gallium/auxiliary/pipe-loader/.libs/libpipe_loader_static.a(libpipe_loader_static_la-pipe_loader_sw.o):(.data.rel.ro+0x0): undefined reference to `sw_screen_create'\ncollect2: error: ld returned 1 exit status\nMakefile:756: recipe for target 'libXvMCgallium.la' failed\nmake[3]: *** [libXvMCgallium.la] Error 1\n\nTrivial.","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/22d2dda03be32d23bc8e9f5823a4f2469737ddbe"},{"sha":"c2e146f4879b806e7178b8145645268c1ce0b4cd","author":{"email":"cdcb67a5e49297de94340ca09f25994bd5e7f762@intel.com","name":"Tapani Pälli"},"message":"mesa: error out in indirect draw when vertex bindings mismatch\n\nPatch adds additional mask for tracking which vertex arrays have\nassociated vertex buffer binding set. This array can be directly\ncompared to which vertex arrays are enabled and should match when\ndrawing.\n\nFixes following CTS tests:\n\n   ES31-CTS.draw_indirect.negative-noVBO-arrays\n   ES31-CTS.draw_indirect.negative-noVBO-elements\n\nv2: update mask in vertex_array_attrib_binding\nv3: rename mask and make it track _BoundArrays which matches what\n    was actually originally wanted (Fredrik Höglund)\nv4: code cleanup, check for GLES 3.1 (Fredrik Höglund)\n\nSigned-off-by: Tapani Pälli <tapani.palli@intel.com>\nReviewed-by: Fredrik Höglund <fredrik@kde.org>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/c2e146f4879b806e7178b8145645268c1ce0b4cd"},{"sha":"63b49e1711382c263acdcbe2d58c28ef64164059","author":{"email":"d284b1e5d144aa8ffd9d3937a966cb84599af26e@intel.com","name":"Marta Lofstedt"},"message":"mesa: remove ARB_geometry_shader4\n\nNo drivers currently implement ARB_geometry_shader4, nor are there\nany plans to implement it.  We only support the version of geometry\nshaders that was incorporated into OpenGL 3.2 / GLSL 1.50.\n\nSigned-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/63b49e1711382c263acdcbe2d58c28ef64164059"},{"sha":"ca976e6900dc8ff457ed9dba661d037c616abc59","author":{"email":"2904e845d63d102574cbb95a4bcdefac0a5d7af0@samsung.com","name":"Julien Isorce"},"message":"st/va: add missing profiles in PipeToProfile's switch.\n\nOtherwise assert is raised from vlVaQueryConfigProfiles's for loop.\n\nSigned-off-by: Julien Isorce <j.isorce@samsung.com>\nReviewed-by: Christian König <christian.koenig@amd.com>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/ca976e6900dc8ff457ed9dba661d037c616abc59"},{"sha":"80a16dece614ef3763e2817d10a45462367af8b2","author":{"email":"0d0be6cf5ad662651be2dc5dfd44aa2b09d4c1cc@amd.com","name":"Nicolai Hähnle"},"message":"radeon: delay the generation of driver query names until first use\n\nThis shaves a bit more time off the startup of programs that don't\nactually use performance counters.\n\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/80a16dece614ef3763e2817d10a45462367af8b2"},{"sha":"f36d9857cd35300d23c6be092feb6cd8c8a0e290","author":{"email":"1d0b47a508f04184301062f109cd46e4b3383bfb@gmail.com","name":"Nicolai Hähnle"},"message":"gallium: add PIPE_DRIVER_QUERY_FLAG_DONT_LIST\n\nThis allows the driver to give a hint to the HUD so that GALLIUM_HUD=help is\nless spammy.\n\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/f36d9857cd35300d23c6be092feb6cd8c8a0e290"},{"sha":"6b5268d202acdc69469bd8c1a2f374ccdf414769","author":{"email":"1d0b47a508f04184301062f109cd46e4b3383bfb@gmail.com","name":"Nicolai Hähnle"},"message":"radeon: use PIPE_DRIVER_QUERY_FLAG_DONT_LIST for perfcounters\n\nSince the query names are not very enlightening, and there are thousands\nof them, GALLIUM_HUD=help should only show the first and last query name\nfor each hardware block.\n\nReviewed-by: Marek Olšák <marek.olsak@amd.com>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/6b5268d202acdc69469bd8c1a2f374ccdf414769"},{"sha":"3e6d0d2ca446cb7b3ad8f32bd0d93275a7ed34bc","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965: Add symbolic defines for some magic dataport surface indices.\n\nReviewed-by: Kristian Høgsberg  <krh@bitplanet.net>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/3e6d0d2ca446cb7b3ad8f32bd0d93275a7ed34bc"},{"sha":"bc8182808aea111aea3cfcba4da3dd861689d890","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/fs: Don't use Gen7-style scratch block reads on Gen9+.\n\nUnfortunately Gen7 scratch block reads and writes seem to be hardwired\nto BTI 255 even on Gen9+ where that index causes the dataport to do an\nIA-coherent read or write.  This change is required for the next patch\nto be correct, since otherwise we would be writing to the scratch\nspace using non-coherent access and then reading it back using\nIA-coherent reads, which wouldn't be guaranteed to return the value\npreviously written to the same location without introducing an\nadditional HDC flush in between.\n\nReviewed-by: Kristian Høgsberg  <krh@bitplanet.net>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/bc8182808aea111aea3cfcba4da3dd861689d890"},{"sha":"55ffa64daf765b1229364518106a4124bd84b9a7","author":{"email":"5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net","name":"Francisco Jerez"},"message":"i965/gen9+: Switch thread scratch space to non-coherent stateless access.\n\nThe thread scratch space is thread-local so using the full IA-coherent\nstateless surface index (255 since Gen8) is unnecessary and\npotentially expensive.  On Gen8 and early steppings of Gen9 this is\nnot a functional change because the kernel already sets bit 4 of\nHDC_CHICKEN0 which overrides all HDC memory access to be non-coherent\nin order to workaround a hardware bug.\n\nThis happens to fix a full system hang when running any spilling code\non a pre-production SKL GT4e machine I have on my desk (forcing all\nHDC access to non-coherent from the kernel up to stepping F0 might be\na good idea though regardless of this patch), and improves performance\nof the OglPSBump2 SynMark benchmark run with INTEL_DEBUG=spill_fs by\n33% (11 runs, 5% significance) on a production SKL GT2 (on which HDC\nIA-coherency is apparently functional so it wouldn't make sense to\ndisable globally).\n\nReviewed-by: Kristian Høgsberg  <krh@bitplanet.net>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/55ffa64daf765b1229364518106a4124bd84b9a7"},{"sha":"b7c958b7b7c44e8f4c6dc0190e4c198722e020e5","author":{"email":"bbac3597f01acc7d927683e64659598a4321d5b2@sigluy.net","name":"Serge Martin"},"message":"clover: fix tgsi compiler crash with invalid src\n\nReviewed-by: Francisco Jerez <currojerez@riseup.net>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/b7c958b7b7c44e8f4c6dc0190e4c198722e020e5"},{"sha":"5adf4a5cdaec98c9195a66485120e8e00c517fc2","author":{"email":"6f78cdb10adbe0a7fbbf4098125a51f401c77a5f@freedesktop.org","name":"Rob Clark"},"message":"freedreno/a3xx: rework vinterp/vpsrepl\n\nMake the interpolation / point-sprite replacement mode setup deal with\nvarying packing.\n\nIn a later commit, we switch to packing just the varying components that\nare actually used by the frag shader, so we won't be able to assume\neverything is vec4's aligned to vec4.  Which would highly confuse the\nprevious vinterp/vpsrepl logic.\n\nSigned-off-by: Rob Clark <robclark@freedesktop.org>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/5adf4a5cdaec98c9195a66485120e8e00c517fc2"},{"sha":"2fbe4e7d2fdb18e12860cd577990ec97b5e18647","author":{"email":"6f78cdb10adbe0a7fbbf4098125a51f401c77a5f@freedesktop.org","name":"Rob Clark"},"message":"freedreno/a4xx: rework vinterp/vpsrepl\n\nSame as previous commit, for a4xx.\n\nSigned-off-by: Rob Clark <robclark@freedesktop.org>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/2fbe4e7d2fdb18e12860cd577990ec97b5e18647"},{"sha":"2181f2cd58f2af1e216618fc6889e23697cec325","author":{"email":"6f78cdb10adbe0a7fbbf4098125a51f401c77a5f@freedesktop.org","name":"Rob Clark"},"message":"freedreno/ir3: use instr flag to mark unused instructions\n\nRather than magic depth value, which won't be available in later stages.\n\nSigned-off-by: Rob Clark <robclark@freedesktop.org>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/2181f2cd58f2af1e216618fc6889e23697cec325"},{"sha":"57fc0dd8d5610a0a25cece53b172b0c992421db0","author":{"email":"6f78cdb10adbe0a7fbbf4098125a51f401c77a5f@freedesktop.org","name":"Rob Clark"},"message":"freedreno/ir3: assign varying locations later\n\nRather than assigning inloc up front, when we don't yet know if it will\nbe unused, assign it last thing before the legalize pass.\n\nAlso, realize when inputs are unused (since for frag shader's we can't\nrely on them being removed from ir->inputs[]).  This doesn't make sense\nif we don't also dynamically assign the inloc's, since we could end up\ntelling the hw the wrong # of varyings (since we currently assume that\nthe # of varyings and max-inloc are related..)\n\nSigned-off-by: Rob Clark <robclark@freedesktop.org>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/57fc0dd8d5610a0a25cece53b172b0c992421db0"},{"sha":"c3ec12ec3c1ddbc72e50df1f5632fe0547a89f7e","author":{"email":"5dd83789ef3714029244367ba1ca09f1d7627408@collabora.com","name":"Timothy Arceri"},"message":"glsl: don't generate extra errors in ValidateProgramPipeline\n\nFrom Section 11.1.3.11 (Validation) of the GLES 3.1 spec:\n\n   \"An INVALID_OPERATION error is generated by any command that trans-\n   fers vertices to the GL or launches compute work if the current set\n   of active program objects cannot be executed, for reasons including:\"\n\nIt then goes on to list the rules we validate in the\n_mesa_validate_program_pipeline() function.\n\nFor ValidateProgramPipeline the only mention of generating an error is:\n\n   \"An INVALID_OPERATION error is generated if pipeline is not a name re-\n   turned from a previous call to GenProgramPipelines or if such a name has\n   since been deleted by DeleteProgramPipelines,\"\n\nWhich we handle separately.\n\nThis fixes:\nES31-CTS.sepshaderobjs.PipelineApi\n\nNo regressions on the eEQP 3.1 tests.\n\nCc: Gregory Hainaut <gregory.hainaut@gmail.com>\nReviewed-by: Tapani Pälli <tapani.palli@intel.com>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/c3ec12ec3c1ddbc72e50df1f5632fe0547a89f7e"},{"sha":"27a88a947c78c9af5eaeb6587fb5211057931d8c","author":{"email":"86e6f0c9eba14994f25948ad50c226b324e9fa92@igalia.com","name":"Eduardo Lima Mitev"},"message":"docs: Update GL3.txt to add ARB_internalformat_query2\n\nAdded to OpenGL 4.3 section, tagged as 'in progress (elima)'. See\nhttps://bugs.freedesktop.org/show_bug.cgi?id=92687.\n\nThanks to Thomas H.P. Andersen for remainding me about this.\n\nv1: - Update the already existing entry in section 4.3\n      instead (Ilia Mirkin).\n    - Added my BZ nickname as contact person (Felix Schwarz).\n\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":true,"url":"https://api.github.com/repos/bminor/mesa-mesa/commits/27a88a947c78c9af5eaeb6587fb5211057931d8c"}]}