{"action":"created","issue":{"url":"https://api.github.com/repos/Qucs/qucs/issues/318","labels_url":"https://api.github.com/repos/Qucs/qucs/issues/318/labels{/name}","comments_url":"https://api.github.com/repos/Qucs/qucs/issues/318/comments","events_url":"https://api.github.com/repos/Qucs/qucs/issues/318/events","html_url":"https://github.com/Qucs/qucs/issues/318","id":95920645,"number":318,"title":"Verilog-A modules builder concept","user":{"login":"ra3xdh","id":4920080,"avatar_url":"https://avatars.githubusercontent.com/u/4920080?v=3","gravatar_id":"","url":"https://api.github.com/users/ra3xdh","html_url":"https://github.com/ra3xdh","followers_url":"https://api.github.com/users/ra3xdh/followers","following_url":"https://api.github.com/users/ra3xdh/following{/other_user}","gists_url":"https://api.github.com/users/ra3xdh/gists{/gist_id}","starred_url":"https://api.github.com/users/ra3xdh/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ra3xdh/subscriptions","organizations_url":"https://api.github.com/users/ra3xdh/orgs","repos_url":"https://api.github.com/users/ra3xdh/repos","events_url":"https://api.github.com/users/ra3xdh/events{/privacy}","received_events_url":"https://api.github.com/users/ra3xdh/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":{"login":"ra3xdh","id":4920080,"avatar_url":"https://avatars.githubusercontent.com/u/4920080?v=3","gravatar_id":"","url":"https://api.github.com/users/ra3xdh","html_url":"https://github.com/ra3xdh","followers_url":"https://api.github.com/users/ra3xdh/followers","following_url":"https://api.github.com/users/ra3xdh/following{/other_user}","gists_url":"https://api.github.com/users/ra3xdh/gists{/gist_id}","starred_url":"https://api.github.com/users/ra3xdh/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ra3xdh/subscriptions","organizations_url":"https://api.github.com/users/ra3xdh/orgs","repos_url":"https://api.github.com/users/ra3xdh/repos","events_url":"https://api.github.com/users/ra3xdh/events{/privacy}","received_events_url":"https://api.github.com/users/ra3xdh/received_events","type":"User","site_admin":false},"milestone":null,"comments":2,"created_at":"2015-07-19T14:35:56Z","updated_at":"2015-07-19T17:11:00Z","closed_at":null,"body":"I would like to present my concept of Verilog-A modules builder. Test branch https://github.com/ra3xdh/qucs/tree/verilog-A contains source code. Verilog-A modules builder allows you to convert a Qucs subciruit (*.sch) to Verilog-A module (*.va). This concept was discussed with @MikeBrinson  about a month ago. At current state only EDDs and resistors are supported. There are no error-checks in schematic. Of course, there may be bugs.\r\n\r\nHow to use:\r\n* Checkout and build branch\r\n* Run Qucs, open subcircuit (*.sch)\r\n* Click main menu *Simulation->Build Verilog-A module from subcircuit*\r\n* Select filename and location to save module\r\n* View module with test editor\r\n\r\nHere is test circuit: https://gist.github.com/ra3xdh/0a579afdb7c24c003a79 . \r\n\r\nIt is tunnel diode model.\r\n![tunn](https://cloud.githubusercontent.com/assets/4920080/8766311/f501a586-2e3b-11e5-9c80-0a33ad228283.png)\r\n\r\nAnd here is auto-generated Verilog-A code for it. \r\n~~~\r\n`include \"disciplines.vams\"\r\n`include \"constants.vams\"\r\nmodule tunnsub(K, A);\r\ninout K, A;\r\nelectrical _net0, K, A;\r\nparameter real Is=1e-12;\r\nparameter real Ip=1e-5;\r\nparameter real Iv=1e-6;\r\nparameter real Vp=0.1;\r\nparameter real Vv=0.4;\r\nparameter real K=5;\r\nparameter real C=0.01p;\r\nparameter real Temp0=300;\r\nreal VT;\r\nanalog begin \r\n@(initial model)\r\nbegin \r\nVT=(`P_K*Temp0)/`P_Q;\r\nend\r\nI(_net0,K) <+ Is*(exp(V(_net0,K)/VT)-1.0);\r\nI(_net0,K) <+ ddt(C*V(_net0,K));\r\nI(_net0,K) <+ Iv*exp(K*(V(_net0,K)-Vv));\r\nI(_net0,K) <+ Ip*(V(_net0,K)/Vp)*exp((Vp-V(_net0,K))/Vp);\r\nV(_net0,A) <+ I(_net0,A)*(1e-3);\r\nend\r\nendmodule\r\n~~~\r\n"},"comment":{"url":"https://api.github.com/repos/Qucs/qucs/issues/comments/122683621","html_url":"https://github.com/Qucs/qucs/issues/318#issuecomment-122683621","issue_url":"https://api.github.com/repos/Qucs/qucs/issues/318","id":122683621,"user":{"login":"guitorri","id":1388949,"avatar_url":"https://avatars.githubusercontent.com/u/1388949?v=3","gravatar_id":"","url":"https://api.github.com/users/guitorri","html_url":"https://github.com/guitorri","followers_url":"https://api.github.com/users/guitorri/followers","following_url":"https://api.github.com/users/guitorri/following{/other_user}","gists_url":"https://api.github.com/users/guitorri/gists{/gist_id}","starred_url":"https://api.github.com/users/guitorri/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/guitorri/subscriptions","organizations_url":"https://api.github.com/users/guitorri/orgs","repos_url":"https://api.github.com/users/guitorri/repos","events_url":"https://api.github.com/users/guitorri/events{/privacy}","received_events_url":"https://api.github.com/users/guitorri/received_events","type":"User","site_admin":false},"created_at":"2015-07-19T17:11:00Z","updated_at":"2015-07-19T17:11:00Z","body":"@ra3xdh does this code has to be after spice4qucs?\r\nI believe the `V() <+` contributions are not currently supported by the ADMS/qucsator interface..."}}