{"action":"created","comment":{"url":"https://api.github.com/repos/maxeler/maxpower/pulls/comments/45874522","id":45874522,"diff_hunk":"@@ -0,0 +1,172 @@\n+package maxpower.kernel.mem;\n+\n+import maxpower.kernel.io.VariableWidthIO;\n+\n+import com.maxeler.maxcompiler.v2.errors.MaxCompilerAPIError;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.Kernel;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.Bitops;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.Mem;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.Mem.RamWriteMode;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.memory.Memory;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.KernelObjectVectorizable;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.KernelType;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFETypeFactory;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEStruct;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEStructType;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEVector;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEVectorType;\n+import com.maxeler.maxcompiler.v2.utils.MathUtils;\n+\n+/**\n+ *   This implements multi-bank FMEM buffer with a scheduled access.\n+ *   Multiple inputs and outputs per cycle are supported. The number of banks\n+ *   in FMEM may exceed the number of inputs/outputs. Each input and output\n+ *   entry is supported by its own scheduling command instructing which FMEM\n+ *   bank to read/write at which address.\n+ *\n+ *\n+ *   @author Pavel Burovskiy\n+ */\n+public class MultiBankBuffer{\n+\n+\tpublic static String bankIdTag = \"bankID\";\n+\tpublic static String bankAddressTag = \"bankIndex\";\n+\tpublic static String readAccessTag = \"readEnable\";\n+\tpublic static String writeAccessTag = \"writeEnable\";\n+\n+\t/***\n+\t *  Create scheduled access buffer for which the number of\n+\t *  inputs and outputs equal AND write access schedule simultaneously\n+\t *  works as read access schedule: data is put into the buffer for the\n+\t *  purpose of the further re-use (in a WRITE_FIRST mode), but the\n+\t *  same data must also\n+\t *  appear at the output same cycle. Read and write access\n+\t *  schedulings are merged into one, with two additional read and write enable\n+\t *  boolean flags per scheduling command\n+\t *  TODO: rewrite this: 'write enable' state implies both read and write access; 'read' state implies only reads from FMEM.\n+\t *  <p>\n+\t *  Inputs and outputs are DFEVectors of same size, also the same size as\n+\t *  DFEVector of scheduling commands. If <i>n</i> scheduling commands says\n+\t *  'write enable' and <i>m</i> commands says 'read', only first <i>n</i>\n+\t *  elements of input vector are put into FMEM (accessed in order of their\n+\t *  reference by 'write' scheduling commands); the last <i>m</i> elements\n+\t *  of input vector are <i>ignored</i>. Please use {@link VariableWidthIO}\n+\t *  to read variable number of necessary items per cycle, to form the\n+\t *  input to this buffer. The output elements come in order of their\n+\t *  reference by both read and write schedule commands.\n+\t *  <p>\n+\t *  Scheduling command is a DFEStruct which must have the following fields:\n+\t *  <ul>\n+\t *     <li> buffID: the FMEM bank to access; </li>\n+\t *     <li> buffIndex: address within the FMEM bank; </li>\n+\t *     <li> readAccessEnable: boolean flag, as above. </li>\n+\t *     <li> writeAccessEnable: boolean flag, as above. </li>\n+\t *  </ul>\n+\t *  It may have other fields (ignored by this buffer). Scheduling must\n+\t *  comply with the following rules:\n+\t *  <p>\n+\t *  <ul>\n+\t *     <li> If several scheduling commands point to the same FMEM bank,\n+\t *          all must have same address, and at most one command is marked 'write enable'.</li>\n+\t *     <li> No two write commands use the same FMEM bank.</li>\n+\t *  </ul>\n+\t *  Non-conforming scheduling implies undefined behaviour.\n+\t *  <p>\n+\t *  @param  numBufs      number of FMEM banks\n+\t *  @param  bufDepth     (maximum) number of entries in each FMEM bank\n+\t *  @param  dataIn       vector of input data\n+\t *  @param  scheduling   vector of scheduling commands\n+\t *  @return DFEVector of data buffered\n+\t *  @throws MaxCompilerAPIError  If number of inputs does not match number of scheduling commands\n+\t *  @throws MaxCompilerAPIError  If number of inputs exceeds the number of FMEM banks\n+\t *  @throws MaxCompilerAPIError  If number of inputs is zero\n+\t *  @throws MaxCompilerAPIError  If scheduling command does not have necessary fields\n+\t */\n+\tpublic static <T extends KernelObjectVectorizable<T,?>> DFEVector<T> create(int numBanks, int bankDepth,\n+\t\t\tDFEVector<T> dataIn, DFEVector<DFEStruct> scheduling) {\n+\t\treturn create(numBanks, bankDepth, dataIn, scheduling, RamWriteMode.WRITE_FIRST);\n+\t}\n+\n+    // Hm, it does not only create the buffer, it also returns stuff. Any suggestions?\n+\tpublic static <T extends KernelObjectVectorizable<T,?>> DFEVector<T> create(int numBanks, int bankDepth,\n+\t\t\tDFEVector<T> dataIn, DFEVector<DFEStruct> scheduling, Mem.RamWriteMode bufferWriteMode) {\n+\n+\t\tKernel owner = dataIn.getKernel();\n+\t\tKernelType<T> dataType = dataIn.getType().getContainedType();\n+\n+\t\tint numInputs = scheduling.getSize();\n+\t\tif (numInputs > numBanks )\n+\t\t\tthrow new MaxCompilerAPIError(\"Number of FMEM banks must be greater or equal the number of scheduling commands\");\n+\t\tif (numInputs < 1)\n+\t\t\tthrow new MaxCompilerAPIError(\"Number of input data items must be greater than 0\");\n+\t\tif (dataIn.getSize() != numInputs)\n+\t\t\tthrow new MaxCompilerAPIError(\"Number of input data items must equal the number of scheduling commands\");\n+\t\tif (!scheduling[0].getType().equals(getAccessCommandType(numBanks,bankDepth)))\n+\t\t\tthrow new MaxCompilerAPIError(\"Access commands must have the following fields: [\"\n+\t\t\t             + bankIdTag +\",\"+ bankAddressTag +\",\"+ readAccessTag +\",\"+ writeAccessTag +\"]\");\n+\n+\t\tDFEVectorType<DFEVar> selectorType = new DFEVectorType<DFEVar>(DFETypeFactory.dfeBool(), numInputs);\n+\n+\t\tDFEVector<T> dataFromBanks = new DFEVectorType<T>(dataType, numBanks).newInstance(owner);\n+\t\tfor (int i = 0; i < numBanks; i++) {\n+\t\t\tMemory<T> bank = owner.mem.alloc(dataType, bankDepth);\n+\t\t\t/*\n+\t\t\t *  Num inputs does not match num banks =>\n+\t\t\t *  do match bank ids with the list of available banks:\n+\t\t\t *  preparing for accessing the row of FMEM banks\n+\t\t\t */\n+\t\t\tDFEVector<DFEVar> readSelector = selectorType.newInstance(owner);\n+\t\t\tDFEVector<DFEVar> writeSelector = selectorType.newInstance(owner);\n+\t\t\tfor (int j = 0; j < numInputs; j++) {\n+\t\t\t\tDFEVar bankIdMatch = ((DFEVar)scheduling[j][bankIdTag]) === i;\n+\t\t\t\t// Assuming CPU scheduling does not allow 2 mem commands to write to the same bank\n+\t\t\t\twriteSelector[j] <== bankIdMatch & (((DFEVar)scheduling[j][writeAccessTag]) === 1);\n+\t\t\t\treadSelector[j] <== bankIdMatch & (((DFEVar)scheduling[j][readAccessTag]) === 1);\n+\t\t\t}\n+\n+\t\t\t// TODO: possible optimisation: shift vector elements so that required element has index 0\n+\t\t\tDFEVar writeSelect = writeSelector.pack();\n+\t\t\tDFEStruct writeMemCommandPerBank = owner.control.oneHotMux(writeSelect, scheduling.getElementsAsList());\n+\t\t\t// If neither mem cmd references this bank, make sure we don't write to it\n+\t\t\tDFEVar writeEnable = writeSelect.neq(0) & (((DFEVar)writeMemCommandPerBank[writeAccessTag]) === 1);\n+\t\t\tT dataToWrite = owner.control.oneHotMux(writeSelect, dataIn.getElementsAsList());\n+\n+\t\t\t// If more than one mem cmd request to access this (i-th) bank, choose one;\n+\t\t\t// for the sake of convention, choose memcmd with largest id number\n+\t\t\tDFEVar readSelectorPacked = readSelector.pack();\n+\t\t\tDFEVar oneHotReadSelect = DFETypeFactory.dfeUInt(numInputs).unpack(readSelectorPacked);\n+\t\t\tDFEVar readSelect = Bitops.leading1Detect(oneHotReadSelect);\n+\t\t\tDFEStruct readMemCommandPerBank = owner.control.oneHotMux(readSelect, scheduling.getElementsAsList());\n+\n+\t\t\t// Working around corner case:\n+\t\t\t//  - read and write addresses may not coincide\n+\t\t\t//  - we're forced to use one address for both read and write\n+\t\t\t//  - cannot simply use write address: there may be no write commands in a cycle\n+\t\t\t// => using write address if there's write or read address otherwise\n+\t\t\tDFEVar address = writeEnable? (DFEVar) writeMemCommandPerBank[bankAddressTag]\n+\t\t\t                            : (DFEVar) readMemCommandPerBank[bankAddressTag];\n+\t\t\tdataFromBanks[i] <== bank.port(address, dataToWrite, writeEnable, bufferWriteMode);\n+\t\t}\n+\n+\t\tint numOutputs = scheduling.getSize();\n+\t\tDFEVector<T> output = new DFEVectorType<T>(dataType, numOutputs).newInstance(owner);\n+\t\tfor (int j = 0; j < numOutputs; j++) {\n+\t\t\tDFEVar bankId = (DFEVar)scheduling[j][bankIdTag];\n+\t\t\toutput[j] <== owner.control.mux(bankId, dataFromBanks.getElementsAsList());\n+\t\t}\n+\t\treturn output;\n+\t}\n+\n+    /***\n+     *  Return the type of access commands expected as input to MultiBankBuffer.\n+     */\n+\tpublic static DFEStructType getAccessCommandType(int numBanks, int bankDepth) {\n+\t\t\tDFEStructType.StructFieldType bankID    = DFEStructType.sft(bankIdTag, DFETypeFactory.dfeUInt(MathUtils.bitsToAddress(numBanks)));\n+\t\t\tDFEStructType.StructFieldType bankIndex = DFEStructType.sft(bankAddressTag, DFETypeFactory.dfeUInt(MathUtils.bitsToAddress(bankDepth)));\n+\t\t\tDFEStructType.StructFieldType bankRead  = DFEStructType.sft(readAccessTag, DFETypeFactory.dfeBool());\n+\t\t\tDFEStructType.StructFieldType bankWrite = DFEStructType.sft(writeAccessTag, DFETypeFactory.dfeBool());\n+\t\t\treturn new DFEStructType(bankID, bankIndex, bankRead, bankWrite);\n+\t}","path":"src/maxpower/kernel/mem/MultiBankBuffer.maxj","position":170,"original_position":170,"commit_id":"b6345cd704876702bb4e21122113b80300773a11","original_commit_id":"b6345cd704876702bb4e21122113b80300773a11","user":{"login":"simontilbury","id":13101368,"avatar_url":"https://avatars.githubusercontent.com/u/13101368?v=3","gravatar_id":"","url":"https://api.github.com/users/simontilbury","html_url":"https://github.com/simontilbury","followers_url":"https://api.github.com/users/simontilbury/followers","following_url":"https://api.github.com/users/simontilbury/following{/other_user}","gists_url":"https://api.github.com/users/simontilbury/gists{/gist_id}","starred_url":"https://api.github.com/users/simontilbury/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/simontilbury/subscriptions","organizations_url":"https://api.github.com/users/simontilbury/orgs","repos_url":"https://api.github.com/users/simontilbury/repos","events_url":"https://api.github.com/users/simontilbury/events{/privacy}","received_events_url":"https://api.github.com/users/simontilbury/received_events","type":"User","site_admin":false},"body":"This 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