{"push_id":718936712,"size":40,"distinct_size":40,"ref":"refs/heads/EZ-arcHS-upstream","head":"d37a97118df7c4f45fb5aee49e02c62372a47830","before":"fefb3feef0a6ebebd053a9792246226ee3de6b0d","commits":[{"sha":"e4a20f7fdc5ffe517e1b09efa0c8cc4bfd332849","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"NET: nps_enet: reduce processing latency.\n\nTX handler is minimalistic and there is no need to schedule\na NAPI job. We processs tx done during hardware interrupt context.\n\nAlso when interrupt is recieved we read directly from control\nregister for RX/TX instead of reading cause register\nsince this register fails to indicate TX done.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/e4a20f7fdc5ffe517e1b09efa0c8cc4bfd332849"},{"sha":"5d90fc383b2a8c02e90e2af4c6be9024dc51a443","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"Documentation: Add EZchip vendor to binding list\n\nAdd EZchip to vendor prefixes list\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/5d90fc383b2a8c02e90e2af4c6be9024dc51a443"},{"sha":"bd3e9b1a9e1b71c6b4370e447a12a0bdd4e3d831","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"scripts: [modpost] add new sections to white list\n\nAdding cmem, cmem_shared, and fmt_slot* to list\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/bd3e9b1a9e1b71c6b4370e447a12a0bdd4e3d831"},{"sha":"c25d68aaace4c83ccae2d9111cafbe855a487aba","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"!!!!!!!!!!!!!! ARC specific commits !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/c25d68aaace4c83ccae2d9111cafbe855a487aba"},{"sha":"f98ee8cbe7a950c3b21c90998ec83e2e826b5f6c","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: Set alignment for symbol first_lines_of_secondary\n\nNow platform can set secondary CPU alignment for the first PC where\nfrom instruction is executed. By default alignment is 4.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/f98ee8cbe7a950c3b21c90998ec83e2e826b5f6c"},{"sha":"3da386d99e23d4ac83eb906a6a4075030008ef72","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: Adjust cpuinfo to work on sparsed mask\n\nWe need to scan online CPUs without assuming\nthat they are consecutive.\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/3da386d99e23d4ac83eb906a6a4075030008ef72"},{"sha":"eae052d9dcfa10f6818ffc4fa42b733e7fcf7c3f","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: Set vmalloc size from configuration\n\nUser space got lower 2G however kernel steal 512M of this space.\nThis stolen space is used partially for vmalloc and the rest\nis serve as gutter between kernel and user space.\nThe vmalloc size is depend on NR_CPUS since per cpu use vmalloc\nto allocate chunks for its use.\n\nHistorically vmalloc size was 256M however it is not enough for\n4K CPUs. An extra 192M is needed to support 4K CPUs.\nWe are setting default vmalloc size to be 256M, and any extra\nspace will be taken from the gutter between kernel and user.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/eae052d9dcfa10f6818ffc4fa42b733e7fcf7c3f"},{"sha":"34adfce77bee967eca758ffd900649497b0e5919","author":{"email":"68bcf2e31c6d30ede2ee225536656df5156ec4c4@ezchip.com","name":"Gil Fruchter"},"message":"ARC: return to exception context before EXCEPTION_EPILOGUE\n\nNeeded when faking rtie and another exception may occur\nduring EXCEPTION_EPILOGUE at the end of this faked situation.\n\nOne can see a scenario where a program would do:\nUser program does a store to un-cached DDR with no write back.\nTrap (for system call, TLB miss, whatever)\n...\n\nIf the latency to DDR is long enough, and an ECC error occurs,\nyou can get \"back\" a memory exception in the short window of EXCEPTION_EPILOGUE.\n\nWith the original code, this would result in an endless loop.\nWith the existing code, it would result by user program terminated with a SIGBUS.\n\nAnother scenarion may be in case that Perf counter overflow cause\nexception (NOT interrupt) during EXCEPTION_EPILOGUE specifically after restoring eret.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/34adfce77bee967eca758ffd900649497b0e5919"},{"sha":"93cea22b337e3bc1e224afe7e3a811b5defc630b","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: disable interrupts before read/write spinlock\n\nIf we hold rw->lock_mutex and interrupt occures we may\nend up spinning on it for ever during softirq.\n\nBelow you may see an example for interrupt we accept while\nnl_table_lock is holding its rw->lock_mutex and we spinned\non it for good.\n\nThe concept for the fix was taken from SPARC.\n\n[2015-05-12 19:16:10] ethdriver version 0.1 (11.Feb.2012)\n[2015-05-12 19:16:10] TCP: cubic registered\n[2015-05-12 19:16:10] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.17.0.EZchip_2.2 #17\n[2015-05-12 19:16:12]\n[2015-05-12 19:16:12] Stack Trace:\n[2015-05-12 19:16:12]   arc_unwind_core+0xb8/0x11c\n[2015-05-12 19:16:12]   dump_stack+0x68/0xac\n[2015-05-12 19:16:12]   _raw_read_lock+0xa8/0xac\n[2015-05-12 19:16:12]   netlink_broadcast_filtered+0x56/0x35c\n[2015-05-12 19:16:12]   nlmsg_notify+0x42/0xa4\n[2015-05-12 19:16:13]   neigh_update+0x1fe/0x44c\n[2015-05-12 19:16:13]   neigh_event_ns+0x40/0xa4\n[2015-05-12 19:16:13]   arp_process+0x46e/0x5a8\n[2015-05-12 19:16:13]   __netif_receive_skb_core+0x358/0x500\n[2015-05-12 19:16:13]   process_backlog+0x92/0x154\n[2015-05-12 19:16:13]   net_rx_action+0xb8/0x188\n[2015-05-12 19:16:13]   __do_softirq+0xda/0x1d8\n[2015-05-12 19:16:14]   irq_exit+0x8a/0x8c\n[2015-05-12 19:16:14]   arch_do_IRQ+0x6c/0xa8\n[2015-05-12 19:16:14]   handle_interrupt_level1+0xe4/0xf0\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/93cea22b337e3bc1e224afe7e3a811b5defc630b"},{"sha":"2971a62d5266eeac9c943f9723a1d2d058b84d13","author":{"email":"9eb5903f3e94f804514a44d30418315f7a8c2f7d@ezchip.com","name":"Tal Zilcer"},"message":"ARC: arch_spinlock use cpu_relax() for optimization\n\nIn SMT machine with multiple HW threads if one HW thread is\ncontending on spinlock we wish to switch to another thread\nthat may hold this spinlock.\n\nThis may achieved by using cpu_relax() that is should be defined\nproperly for such platform with SMT.\n\nRunning hackbench on NPS400 we got more than 10% improvement in time.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/2971a62d5266eeac9c943f9723a1d2d058b84d13"},{"sha":"b81ef773a57c3fa64a41e6a75bb8fa546dcd4b86","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: [SMP] init cpus maps according to given maps.\n\nplatform can set its own set of possible/present cpus at run time.\n\nNOTE: map must include cpu 0.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/b81ef773a57c3fa64a41e6a75bb8fa546dcd4b86"},{"sha":"cf632a71ab125d5b00f966d102bba8fad2659cb5","author":{"email":"68bcf2e31c6d30ede2ee225536656df5156ec4c4@ezchip.com","name":"Gil Fruchter"},"message":"ARC: [actionpoints] Add kernel actionpoints support\n\nAdd support for CONFIG_HAVE_HW_BREAKPOINT.\nSupport both watchpoints and breakpoints.\nSupport big and little endians.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/cf632a71ab125d5b00f966d102bba8fad2659cb5"},{"sha":"f7e3ff8dfd5dde72e38472abe26d72ae4f47f985","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: Support arch_irq_work_raise() via self IPIs\n\nThis will allow the scheduler tick to be restarted.\nWe shall use this if we're if CONFIG_NO_HZ_FULL.\n\nSigned-off-by: Gil Fruchter <gilf@ezchip.com>\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/f7e3ff8dfd5dde72e38472abe26d72ae4f47f985"},{"sha":"702a73d394594e9fafa5d235e2c89737c4f2a890","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: Check TIF_SYSCALL_TRACE before calling tracehook report routine\n\nWe need to see the reason we got to syscall trace.\nOnly if TIF_SYSCALL_TRACE is set we will call\ntracehook_report_syscall_entry() / tracehook_report_syscall_exit().\n\nLater we will add TIF_NOHZ as reason to call syscall trace\nbut not to call tracehook report methods.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>\nSigned-off-by: Gil Fruchter <gilf@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/702a73d394594e9fafa5d235e2c89737c4f2a890"},{"sha":"7d4e321105d11826b11df2e9329a702fbf0d8b98","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: Schedule hooks for context tracking subsystem\n\nInform context tracking subsystem that we exiting usermode.\nIf !CONFIG_CONTEXT_TRACKING just call schedule\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>\nSigned-off-by: Gil Fruchter <gilf@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/7d4e321105d11826b11df2e9329a702fbf0d8b98"},{"sha":"cf4a7d89eccd4cbb9a9cd0e5426843553eb6f762","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: TIF_NOHZ for context tracking subsystem\n\nThis is the syscall slow path hooks for context tracking subsystem.\nThis bit (in addition to TIF_SYSCALL_TRACE) is used to jump to\ntracesys/tracesys_exit.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>\nSigned-off-by: Gil Fruchter <gilf@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/cf4a7d89eccd4cbb9a9cd0e5426843553eb6f762"},{"sha":"9bab634391aeca1246ebd750cfb96031c9aff05e","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: Exception hooks for context tracking subsystem\n\nWe basically inform the context tracking that the CPU is going to\nenter/exit userspace mode.\nThis information will be used by scheduler to decide if tick can be\nswitched off in dynamic tick mode.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>\nSigned-off-by: Gil Fruchter <gilf@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/9bab634391aeca1246ebd750cfb96031c9aff05e"},{"sha":"8b358417bba2bf90dbf2049b332e614a3c49dd6c","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: add cmpxchg64 for CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN\n\nThis is to ovecome build failure due to commit:\nsched, time: Fix build error with 64 bit cputime_t on 32 bit systems\n347abad981c1ef815ea5ba861adba6a8c6aa1580\n\nThis commit introduce the use of cmpxchg_cputime().\nWhich in our case defined in asm-generic/cputime_nsecs.h to be:\n\nHowever ARC as 32 bit system lake to have cmpxchg64.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/8b358417bba2bf90dbf2049b332e614a3c49dd6c"},{"sha":"9457e952fcc306b765d396b743141c120d7b86a4","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"ARC: call machine hook smp_init before CPU turns online\n\nWe need to make sure that CPU completed all preparations\nbefore next CPU will be waken by cpu_up().\n\nThis is true for SMT system where few CPUs share AUX registers used\nduring CPUs wakening.\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/9457e952fcc306b765d396b743141c120d7b86a4"},{"sha":"583e93db93063db696b737e1895d32051ea3a472","author":{"email":"5aa4b9705348d1692ae3b503c5c840c9fdcd7054@ezchip.com","name":"Noam Camus"},"message":"!!!!!!!!!!!!!! Platform specific commits !!!!!!!!!!!!!!!!!!!!!!!!!\n\nSigned-off-by: Noam Camus <noamc@ezchip.com>","distinct":true,"url":"https://api.github.com/repos/EZchip/linux/commits/583e93db93063db696b737e1895d32051ea3a472"}]}