{"push_id":572459920,"size":1,"distinct_size":1,"ref":"refs/heads/svn/branches/UDK2014.SP1","head":"25b015368fd803e91d213e2f48ddb4d08809a2a3","before":"852128733c3a3ab9044e9b35c87f9f0cadeb3888","commits":[{"sha":"25b015368fd803e91d213e2f48ddb4d08809a2a3","author":{"email":"364a90bfebd1f362ebb7b48e4bf8ec010adef203@intel.com","name":"Yao, Jiewen"},"message":"Fsp1.1 update.\n\nUpdate ApiEntry.asm to use MACRO instead of direct XMM access.\nAdd sanity parameter check for FSP API.\nAdd sanity return code check for internal API.\nCall LoadUcode before CarInit to meet silicon requirement.\nRemove unnecessary VpdBase for PatchTable.\nAdd ASSERT for NULL check FSP1.1 entrypoint.\n\n(Sync patch r16834 from main trunk.)\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: \"Yao, Jiewen\" <jiewen.yao@intel.com>\nReviewed-by: \"Rangarajan, Ravi P\" <ravi.p.rangarajan@intel.com>\nReviewed-by: \"Ma, Maurice\" <maurice.ma@intel.com>\nReviewed-by: \"Mudusuru, Giri P\" <giri.p.mudusuru@intel.com>\n\ngit-svn-id: svn://svn.code.sf.net/p/edk2/code/branches/UDK2014.SP1/IntelFspWrapperPkg@16836 6f19259b-4bc3-4df7-8a09-765794883524","distinct":true,"url":"https://api.github.com/repos/tianocore/edk2-IntelFspWrapperPkg/commits/25b015368fd803e91d213e2f48ddb4d08809a2a3"}]}