{"push_id":822832020,"size":13,"distinct_size":1,"ref":"refs/heads/caf/3.10/LNX.LA.3.7.2_rb1","head":"42e96264d76f911ff546fdc19b2cd423ce1b68ba","before":"56c0c93d046b587d9761c19d09b383f5f3f0cc11","commits":[{"sha":"0dbf8c87e50804bfc64dc64477ca38abce8aeebc","author":{"email":"2a4b97e7c2c7c25502647546b38417ff8ce09c9d@codeaurora.org","name":"Ankit Gupta"},"message":"i2c-msm-v2: reset the qup state in case of error\n\nsoftware workaround to clear any bogus interrupt\nthat generated because of hardware bug that fails\nto clear the interrupt bit mask. Reseting the qup\nstate ward off any pending interrupts.\n\nChange-Id: Iec93d045ea7ef7dd15740b9eeb491462f8b9495d\nSigned-off-by: Ankit Gupta <ankgupta@codeaurora.org>\nSigned-off-by: Sandya Chikka <sandyachikka@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/0dbf8c87e50804bfc64dc64477ca38abce8aeebc"},{"sha":"d382b9110e68f9893319c65c19fd4fa924576c1a","author":{"email":"2a4b97e7c2c7c25502647546b38417ff8ce09c9d@codeaurora.org","name":"Ankit Gupta"},"message":"i2c-msm-v2: Avoid writing core registers when HW is not ready\n\nSW reset of the qup core can take a few clock-cycles before\ngetting into valid state. Another register write during that time may\nlead to NoC error due to core-master not being reachable by AHB, or\ncore may return not-ready status if clocks are gated by HW if HW\ngated the clocks before SW read the register.\nOnce core status is valid, make sure core doesn't keep spinning by\nsleeping intermittently until timeout, or valid state is reached.\n\nChange-Id: I6bd002bf91ba2221bf8398b92c0e8206d86fe050\nSigned-off-by: Ankit Gupta <ankgupta@codeaurora.org>\nSigned-off-by: Sagar Dharia <sdharia@codeaurora.org>\nSigned-off-by: Sandya Chikka <sandyachikka@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/d382b9110e68f9893319c65c19fd4fa924576c1a"},{"sha":"5a85c92d33c04327e0b2374a8d290d35cef5869d","author":{"email":"2a4b97e7c2c7c25502647546b38417ff8ce09c9d@codeaurora.org","name":"Ankit Gupta"},"message":"i2c-msm-v2: fix potential spinning forever in ISR\n\nIRQ is disabled before doing reset state in\npost transfer on timeout to avoid entering ISR that can cause\nthis issue. If ISR is entered due to transfer error,\nwaiting for the qup core to get in a valid state may cause watch\ndog bite if HW generates NoC error while reading status.\nAvoid that by not polling in ISR.\n\nChange-Id: I2e92e43cb37d501a378a717c996b9e98f6cf9fe8\nSigned-off-by: Ankit Gupta <ankgupta@codeaurora.org>\nSigned-off-by: Kiran Gunda <kgunda@codeaurora.org>\nSigned-off-by: Sandya Chikka <sandyachikka@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/5a85c92d33c04327e0b2374a8d290d35cef5869d"},{"sha":"8ea26a06106f6cd8c23ef2658b3a4d08285c8465","author":{"email":"bf1b3d55c9688c44c47080bb956e0b5fa97ddc18@codeaurora.org","name":"Srinivasarao P"},"message":"power: reset: Add support for the new scm_call2 API\n\nThe SCM library now provides a new API that implements\na secure world syscall interface that is more aligned\nwith the ARMv8 SMC calling convention. Add support for\nthis new API.\n\nChange-Id: Ia76309de556e97e43c1e8ab782f89c4115d5fac6\nSigned-off-by: Vikram Mulukutla <markivx@codeaurora.org>\nSigned-off-by: Srinivasarao P <spathi@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/8ea26a06106f6cd8c23ef2658b3a4d08285c8465"},{"sha":"413392b985ab7da6856c1eba3157507e584341ca","author":{"email":"577f74ec3f2c8a155237d5ad42a70103d17f8313@codeaurora.org","name":"Vikram Mulukutla"},"message":"qcom: scm: Implement a retry mechanism\n\nThere are times when the secure world may be processing\nrequests that require one particular client on the HLOS\nto invoke an scm_call. While waiting for this particular\nscm_call, no other scm requests can be processed and the\nsecure world will return an error code indicating this\nsituation.\n\nWhen this error code is encountered, release the scm_call\nmutex, wait for a specified amount of time and retry the\nscm_call. As much as possible, avoid overhead in the first\nscm_call attempt.\n\nChange-Id: I6edce93bb70620fdffcb3ef3fb639cf5b928845b\nSigned-off-by: Vikram Mulukutla <markivx@codeaurora.org>\nSigned-off-by: Srinivasarao P <spathi@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/413392b985ab7da6856c1eba3157507e584341ca"},{"sha":"dd084749bc44bb0f7677d6ffd33eec3075a4d939","author":{"email":"bf1b3d55c9688c44c47080bb956e0b5fa97ddc18@codeaurora.org","name":"Srinivasarao P"},"message":"drivers: soc: qcom: Support the new SCM interface\n\nThe secure world implementation now supports a new SMC\ninterface that is more aligned with the ARMV8 SMC standard.\nSupport this new interface.\n\nChange-Id: I717b92fe626536fb01b3cbc21ccb8a00f7251be6\nSigned-off-by: Vikram Mulukutla <markivx@codeaurora.org>\nSigned-off-by: Srinivasarao P <spathi@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/dd084749bc44bb0f7677d6ffd33eec3075a4d939"},{"sha":"f60fc4343fe0e58798ed74a43a7ca4a51cc59a48","author":{"email":"bf1b3d55c9688c44c47080bb956e0b5fa97ddc18@codeaurora.org","name":"Srinivasarao P"},"message":"qcom: scm: Provide an API that restores security configuration\n\nDrivers require an API to be able to inform the secure world\nthat their devices have resumed from power collapse and security\nsettings need to be re-relaxed.\n\nTransition existing users to the new API.\n\nChange-Id: Ia5b49176c797ec9d6d35350ea98964203d622516\nSigned-off-by: Vikram Mulukutla <markivx@codeaurora.org>\nSigned-off-by: Srinivasarao P <spathi@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/f60fc4343fe0e58798ed74a43a7ca4a51cc59a48"},{"sha":"59f1ef266391a6c365114dc362df2f3839453381","author":{"email":"577f74ec3f2c8a155237d5ad42a70103d17f8313@codeaurora.org","name":"Vikram Mulukutla"},"message":"soc: qcom: scm: Add APIs to allow register access via the secure world\n\nAdd an API to allow certain registers to be accessed\nvia secure world syscalls. Switch existing users to\nthis new API.\n\nChange-Id: I1c2a67f728ddf486e93751e77853cc50e1b9db21\nSigned-off-by: Vikram Mulukutla <markivx@codeaurora.org>\nSigned-off-by: Srinivasarao P <spathi@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/59f1ef266391a6c365114dc362df2f3839453381"},{"sha":"921d731888048684869f6d052ccd27699e84012b","author":{"email":"4b3f23b045e38e54cffd83d34440316666b35af9@codeaurora.org","name":"Stepan Moskovchenko"},"message":"power: reset: msm: Deassert PS_HOLD via SCM if possible\n\nSupport a new SCM call which disables the PMIC arbiter and\ndeasserts PS_HOLD in a single operation. Fall back on the\nlegacy behavior of disabling the PMIC abriter and directly\ndeasserting PS_HOLD if this call is not available.\n\nThis is necessary comply with atomicity requirements of the\nsecure environment.\n\nChange-Id: Ia3b13d469932edf94d3249fa3e7234a1c12eee1b\nSigned-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/921d731888048684869f6d052ccd27699e84012b"},{"sha":"2cace031296eccc0e152dc6379f82d00d369f493","author":{"email":"4b3f23b045e38e54cffd83d34440316666b35af9@codeaurora.org","name":"Stepan Moskovchenko"},"message":"power: reset: msm: Allow configuring reset type via secure I/O\n\nSome targets require that the Download Mode / EDL\nconfiguration be performed by means of a Secure I/O write\nto the TCSR_BOOT_MISC_DETECT register rather than through a\ngeneric SCM operation. Provide a mechanism for specifying\nthe address of this register in the device tree, to use as\na fallback method if the generic SCM call to set the\ndownload mode configuration is unavailable.\n\nThis is necessary to comply with atomicity requirements of the\nsecure environment.\n\nChange-Id: I5d3fcb48b0b47815d4839a3b722b0462a1bca087\nSigned-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>\nSigned-off-by: Srinivasarao P <spathi@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/2cace031296eccc0e152dc6379f82d00d369f493"},{"sha":"be4aa45c3ce82556677d504819b54d8acdca835b","author":{"email":"4b3f23b045e38e54cffd83d34440316666b35af9@codeaurora.org","name":"Stepan Moskovchenko"},"message":"ARM: dts: msm: Support download mode through secure I/O on 8916/8939\n\nAdd the TCSR_BOOT_MISC_DETECT register address to the\nqcom,pshold device on 8916 / 8936 / 8939, to allow\nconfiguring Download Mode / EDL by means of a Secure IO\ncall rather than a direct SCM call.\n\nChange-Id: Ie2eb9decfdfb855c72bcb784ed29f7d0e8c07beb\nSigned-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>\nSigned-off-by: Srinivasarao P <spathi@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/be4aa45c3ce82556677d504819b54d8acdca835b"},{"sha":"c4956d6173c95536506a097dd88ff5f078e14b6d","author":{"email":"4b3f23b045e38e54cffd83d34440316666b35af9@codeaurora.org","name":"Stepan Moskovchenko"},"message":"power: reset: msm: Defer set_dload_mode to end of probe\n\nThe set_dload_mode() call in msm_restart_probe() may depend\non the TCSR base address, which is initialized later in the\nprobe function. Move this call to the end of\nmsm_restart_probe() to avoid potentially trying to use an\nuninitialized resource.\n\nChange-Id: I65c408f065cc7c68a929ec43d50b0a493942a189\nSigned-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>\nSigned-off-by: Srinivasarao P <spathi@codeaurora.org>","distinct":false,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/c4956d6173c95536506a097dd88ff5f078e14b6d"},{"sha":"42e96264d76f911ff546fdc19b2cd423ce1b68ba","author":{"email":"d3c7bae90ce2477533ec852edf38b65198016249@localhost","name":"Linux Build Service Account"},"message":"Merge c4956d6173c95536506a097dd88ff5f078e14b6d on remote branch\n\nChange-Id: I0eb2e22f66a78653a579b999e4de08cc2ba539ad","distinct":true,"url":"https://api.github.com/repos/Rashed97/caf-kernel-msm-3.18/commits/42e96264d76f911ff546fdc19b2cd423ce1b68ba"}]}