{"action":"created","issue":{"url":"https://api.github.com/repos/OP-TEE/optee_os/issues/522","labels_url":"https://api.github.com/repos/OP-TEE/optee_os/issues/522/labels{/name}","comments_url":"https://api.github.com/repos/OP-TEE/optee_os/issues/522/comments","events_url":"https://api.github.com/repos/OP-TEE/optee_os/issues/522/events","html_url":"https://github.com/OP-TEE/optee_os/issues/522","id":113606037,"number":522,"title":"plat-zynq: SCU","user":{"login":"b-bub","id":15342971,"avatar_url":"https://avatars.githubusercontent.com/u/15342971?v=3","gravatar_id":"","url":"https://api.github.com/users/b-bub","html_url":"https://github.com/b-bub","followers_url":"https://api.github.com/users/b-bub/followers","following_url":"https://api.github.com/users/b-bub/following{/other_user}","gists_url":"https://api.github.com/users/b-bub/gists{/gist_id}","starred_url":"https://api.github.com/users/b-bub/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/b-bub/subscriptions","organizations_url":"https://api.github.com/users/b-bub/orgs","repos_url":"https://api.github.com/users/b-bub/repos","events_url":"https://api.github.com/users/b-bub/events{/privacy}","received_events_url":"https://api.github.com/users/b-bub/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":1,"created_at":"2015-10-27T15:06:21Z","updated_at":"2015-10-27T15:24:52Z","closed_at":null,"body":"Hello,\r\n\r\ni try to port optee_os to a Zynq platform.\r\nSo, i cloned plat-stm because it's a Cortex-A9, too.\r\nI only edited platform_config.h, so far.\r\n\r\nUnfortunately, my system crashes when setting up SCU addresses in tz_a9init.S : _boot_late_primary_cpu.\r\nMy guess is, that the SCU start & end addresses are wrong.\r\n\r\nLooking at plat-stm/platform_config.h the SCU addresses (CPU_PORT_FILT_START, CPU_PORT_FILT_END) are set to the DRAM0 address range, aye?\r\nSo, i try the same with my DRAM0 address range, but fail.\r\n\r\nRight after setting the SCU addresses i access the UART register with the following code, to get some debug output.\r\nThe CPU crashes then with the STR instruction.\r\n> mov r0, #'D'            // Load character\r\n> movw r1, #0x1000\r\n> movt r1, #0xE000\r\n> orr r1, r1, #0x30       // TX FIFO register\r\n> str r0, [r1]            // Write character to UART\r\n\r\n\r\nI also checked the Zynq TRM (ug585, v1.10) Chapter 29 'OCM' which gives example settings for SCU. But, i fail with these too.\r\n\r\nI guess i just don't really understand SCU address settings. The examples in Zynq TRM do not follow the logic as in plat-stm.\r\n\r\n\r\nCan anybody throw light on this topic for me, please?\r\nWhat's the purpose of SCU?\r\nIs setting the SCU addresses really that easy as in plat-stm?\r\nIf so, why the hell shouldn't this work on Zynq?\r\n\r\n\r\nThanks"},"comment":{"url":"https://api.github.com/repos/OP-TEE/optee_os/issues/comments/151539528","html_url":"https://github.com/OP-TEE/optee_os/issues/522#issuecomment-151539528","issue_url":"https://api.github.com/repos/OP-TEE/optee_os/issues/522","id":151539528,"user":{"login":"jenswi-linaro","id":6150306,"avatar_url":"https://avatars.githubusercontent.com/u/6150306?v=3","gravatar_id":"","url":"https://api.github.com/users/jenswi-linaro","html_url":"https://github.com/jenswi-linaro","followers_url":"https://api.github.com/users/jenswi-linaro/followers","following_url":"https://api.github.com/users/jenswi-linaro/following{/other_user}","gists_url":"https://api.github.com/users/jenswi-linaro/gists{/gist_id}","starred_url":"https://api.github.com/users/jenswi-linaro/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jenswi-linaro/subscriptions","organizations_url":"https://api.github.com/users/jenswi-linaro/orgs","repos_url":"https://api.github.com/users/jenswi-linaro/repos","events_url":"https://api.github.com/users/jenswi-linaro/events{/privacy}","received_events_url":"https://api.github.com/users/jenswi-linaro/received_events","type":"User","site_admin":false},"created_at":"2015-10-27T15:24:52Z","updated_at":"2015-10-27T15:24:52Z","body":"Hi,\r\n\r\nYou can read about the SCU in Cortex™-A9 MPCore® Technical Reference Manual (http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407i/index.html). There also seems to be some information about it in the TRM you reference.\r\n\r\nRegards,\r\nJens\r\n\r\n"}}