{"action":"created","comment":{"url":"https://api.github.com/repos/maxeler/maxpower/pulls/comments/45861286","id":45861286,"diff_hunk":"@@ -0,0 +1,172 @@\n+package maxpower.kernel.mem;\n+\n+import maxpower.kernel.io.VariableWidthIO;\n+\n+import com.maxeler.maxcompiler.v2.errors.MaxCompilerAPIError;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.Kernel;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.Bitops;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.Mem;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.Mem.RamWriteMode;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.memory.Memory;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.KernelObjectVectorizable;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.KernelType;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFETypeFactory;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEStruct;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEStructType;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEVector;\n+import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEVectorType;\n+import com.maxeler.maxcompiler.v2.utils.MathUtils;\n+\n+/**\n+ *   This implements multi-bank FMEM buffer with a scheduled access.\n+ *   Multiple inputs and outputs per cycle are supported. The number of banks\n+ *   in FMEM may exceed the number of inputs/outputs. Each input and output\n+ *   entry is supported by its own scheduling command instructing which FMEM\n+ *   bank to read/write at which address.\n+ *\n+ *\n+ *   @author Pavel Burovskiy\n+ */\n+public class MultiBankBuffer{\n+\n+\tpublic static String bankIdTag = \"bankID\";\n+\tpublic static String bankAddressTag = \"bankIndex\";\n+\tpublic static String readAccessTag = \"readEnable\";\n+\tpublic static String writeAccessTag = \"writeEnable\";\n+\n+\t/***\n+\t *  Create scheduled access buffer for which the number of\n+\t *  inputs and outputs equal AND write access schedule simultaneously\n+\t *  works as read access schedule: data is put into the buffer for the\n+\t *  purpose of the further re-use (in a WRITE_FIRST mode), but the\n+\t *  same data must also\n+\t *  appear at the output same cycle. Read and write access\n+\t *  schedulings are merged into one, with two additional read and write enable\n+\t *  boolean flags per scheduling command\n+\t *  TODO: rewrite this: 'write enable' state implies both read and write access; 'read' state implies only reads from FMEM.\n+\t *  <p>\n+\t *  Inputs and outputs are DFEVectors of same size, also the same size as\n+\t *  DFEVector of scheduling commands. If <i>n</i> scheduling commands says\n+\t *  'write enable' and <i>m</i> commands says 'read', only first <i>n</i>\n+\t *  elements of input vector are put into FMEM (accessed in order of their\n+\t *  reference by 'write' scheduling commands); the last <i>m</i> elements\n+\t *  of input vector are <i>ignored</i>. Please use {@link VariableWidthIO}\n+\t *  to read variable number of necessary items per cycle, to form the\n+\t *  input to this buffer. The output elements come in order of their\n+\t *  reference by both read and write schedule commands.\n+\t *  <p>\n+\t *  Scheduling command is a DFEStruct which must have the following fields:\n+\t *  <ul>\n+\t *     <li> buffID: the FMEM bank to access; </li>\n+\t *     <li> buffIndex: address within the FMEM bank; </li>\n+\t *     <li> readAccessEnable: boolean flag, as above. </li>\n+\t *     <li> writeAccessEnable: boolean flag, as above. </li>\n+\t *  </ul>\n+\t *  It may have other fields (ignored by this buffer). Scheduling must\n+\t *  comply with the following rules:\n+\t *  <p>\n+\t *  <ul>\n+\t *     <li> If several scheduling commands point to the same FMEM bank,\n+\t *          all must have same address, and at most one command is marked 'write enable'.</li>\n+\t *     <li> No two write commands use the same FMEM bank.</li>\n+\t *  </ul>\n+\t *  Non-conforming scheduling implies undefined behaviour.\n+\t *  <p>\n+\t *  @param  numBufs      number of FMEM banks\n+\t *  @param  bufDepth     (maximum) number of entries in each FMEM bank\n+\t *  @param  dataIn       vector of input data\n+\t *  @param  scheduling   vector of scheduling commands\n+\t *  @return DFEVector of data buffered\n+\t *  @throws MaxCompilerAPIError  If number of inputs does not match number of scheduling commands\n+\t *  @throws MaxCompilerAPIError  If number of inputs exceeds the number of FMEM banks\n+\t *  @throws MaxCompilerAPIError  If number of inputs is zero\n+\t *  @throws MaxCompilerAPIError  If scheduling command does not have necessary fields\n+\t */\n+\tpublic static <T extends KernelObjectVectorizable<T,?>> DFEVector<T> create(int numBanks, int bankDepth,\n+\t\t\tDFEVector<T> dataIn, DFEVector<DFEStruct> scheduling) {\n+\t\treturn create(numBanks, bankDepth, dataIn, scheduling, RamWriteMode.WRITE_FIRST);\n+\t}\n+\n+    // Hm, it does not only create the buffer, it also returns stuff. Any suggestions?","path":"src/maxpower/kernel/mem/MultiBankBuffer.maxj","position":91,"original_position":91,"commit_id":"b6345cd704876702bb4e21122113b80300773a11","original_commit_id":"b6345cd704876702bb4e21122113b80300773a11","user":{"login":"burchanie","id":7000687,"avatar_url":"https://avatars.githubusercontent.com/u/7000687?v=3","gravatar_id":"","url":"https://api.github.com/users/burchanie","html_url":"https://github.com/burchanie","followers_url":"https://api.github.com/users/burchanie/followers","following_url":"https://api.github.com/users/burchanie/following{/other_user}","gists_url":"https://api.github.com/users/burchanie/gists{/gist_id}","starred_url":"https://api.github.com/users/burchanie/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/burchanie/subscriptions","organizations_url":"https://api.github.com/users/burchanie/orgs","repos_url":"https://api.github.com/users/burchanie/repos","events_url":"https://api.github.com/users/burchanie/events{/privacy}","received_events_url":"https://api.github.com/users/burchanie/received_events","type":"User","site_admin":false},"body":"It also fits the future plan of supporting separate access commands for reads and writes: both read() and write() method take the 'scheduling' as argument, similar to address arg of mem.read()","created_at":"2015-11-25T12:33:43Z","updated_at":"2015-11-25T12:33:43Z","html_url":"https://github.com/maxeler/maxpower/pull/43#discussion_r45861286","pull_request_url":"https://api.github.com/repos/maxeler/maxpower/pulls/43","_links":{"self":{"href":"https://api.github.com/repos/maxeler/maxpower/pulls/comments/45861286"},"html":{"href":"https://github.com/maxeler/maxpower/pull/43#discussion_r45861286"},"pull_request":{"href":"https://api.github.com/repos/maxeler/maxpower/pulls/43"}}},"pull_request":{"url":"https://api.github.com/repos/maxeler/maxpower/pulls/43","id":51294505,"html_url":"https://github.com/maxeler/maxpower/pull/43","diff_url":"https://github.com/maxeler/maxpower/pull/43.diff","patch_url":"https://github.com/maxeler/maxpower/pull/43.patch","issue_url":"https://api.github.com/repos/maxeler/maxpower/issues/43","number":43,"state":"open","locked":false,"title":"Adding a scheduled access multi-bank FMEM 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