{"push_id":538628264,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"016345ab9420a332d3a81c0ea284fd305e16e0c3","before":"3c0c8b691e6b5baedc048a1beeeb764fd91dd703","commits":[{"sha":"016345ab9420a332d3a81c0ea284fd305e16e0c3","author":{"email":"cdca4787270da064010d22babbd4b763d61bcde5@gmail.com","name":"Ahmed Bougacha"},"message":"[AArch64] Improve codegen of store lane 0 instructions by directly storing the subregister.\n\nFor 0-lane stores, we used to generate code similar to:\n\n  fmov w8, s0\n  str w8, [x0, x1, lsl #2]\n\ninstead of:\n\n  str s0, [x0, x1, lsl #2]\n\nTo correct that: for store lane 0 patterns, directly match to STR <subreg>0.\n\nByte-sized instructions don't have the special case for a 0 index,\nbecause FPR8s are defined to have untyped content.\n\nrdar://16372710\nDifferential Revision: http://reviews.llvm.org/D6772","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project/commits/016345ab9420a332d3a81c0ea284fd305e16e0c3"}]}