recording now. All right thank you. I assume the antitrust policy notice is on display. Hello everyone this is Arnaud. I'm on the phone today so I can't see but I assume the antitrust policy notice is being displayed. This meeting is open to everyone. You're welcome to attend and participate however we need you to be aware of the antitrust policy notice as well as the cutoff conduct which basically requests that you behave. So with that further ado I would like to get started. We have a pretty packed agenda. There are things that I think are important that we get to discuss. So Dave you actually have and I apologize we didn't have a chance to sync up on exactly the intent was. I saw as I said on the chat you had inserted an announcement on the community calendar Reorg stuff but it wasn't published and when I made a change it pushed the publication of your change and I don't know if you actually intended this to be an agenda or not as a result. Dave? And you might be on mute. Is Dave double muted or something? He's got two different accounts open so we can't hear you right now Dave whichever one you're happening to be using. Do you want me to unmute you? I'll unmute him there. Dave are you there? I think he has to join for our deal. But both of them have the mics showing for Dave. He's got two different logins and both have the mic unslashed. Well let's not hopefully is going to figure it out but let's go to the quarterly reports we can get back to that next if Dave manages to to get heard. They were three quarterly reports filed. Thank you all for doing your homework. The first one is the performance and security working group which basically states that nothing much is happening but we have actually some discussion going on as to what the working group should become anyway. I mean working groups in general which would impact the performance and scalability working group. I don't know that there is much else to say. Mark are you on? Do you want to say anything? No I am on. I wasn't you know we've looked at doing defining metrics for Providence use cases for supply chain but we haven't been able to get a lot of people interested in doing that and so we've sort of been meandering about trying to get that done but it's hard we only have two or three people working on it so anxious to hear you know we've had lots of more people contributing when we have like the fast fabric people come talk to us or something like that so definitely interested in figuring out you know what this reboot would look like and how we can get people interested in performance and scalability again. Right and quite frankly I mean I'll repeat what I've said before is that there is nothing wrong in declaring victory and say okay there doesn't seem to be any impetus behind this now we just close it and tell somebody else says hey I want to do this is there enough people interested so we can start a new effort I think we could just close it. Well I think there's interest in still being able to review papers and things like that I know there's another fabric paper out that I want that I'm reviewing and want to figure out how we can share publicly on the website so okay the idea of a you know SIG whether it be technical SIG or we go under the other under the other. Okay so then we just leave it alone for now. Yeah if there's no deliverables it's easier to man. All right thank you any questions for Mark? So on and I guess this is all again it comes back to the whole okay so now we have SIGs or T-SIGs or whatever we call them and we aren't yet settled on whether they produce anything but I think it's a different story comes when somebody comes in with a paper that they would like to be published somehow or other through Hyperledger now whether that's no is it more than a blog is it you know is it I guess that that then becomes a question for well how does something like that get processed is that something we should be channeling through marketing although again I guess it's it's not really marketing it's a technical paper or that's you know the kind of thing that I'm thinking about and so then the question becomes do they send it to the to the TSC and the TSC decides? Yeah that's an interesting question Chris yes I agree I think you know I don't want to get into this now we are just going over the quality reports but I do agree with you that this is an interesting question is that's really the intent that some I mean some people have that intent to publish papers we should definitely have an open issue and discuss what what the process is yeah all right let's move forward then Hyperledger transact so there was a report find I added the review section that was missing many people have checked their boxes there was one question from Mark yeah this is Mark Ford I'm actually on the call if people have questions I may not be able to answer them all but I did put the report up yesterday and I apologize for the lateness of doing that so I'm glad to see so many people still managed to have a chance to glance through it you typically like to get these things done a little bit more on time yeah but thank you for for doing it anyway and there was a question from Mark Wagner I don't know if you had a chance to see that he put that as a comment yeah so I see it asking if anybody was tracking CVE issues that's something I I don't know I haven't seen any any specific tickets in Jira that fit that description but I will check and let the team here and that be something that could be responded to on the transact channel on rocket show where most of our conversations occur okay so Mark Wagner you do you want more than that I mean I don't know that there's any outstanding CVE's right now but I know some of the earlier Linux CVE's were due to the hardware sure they're using your product console or this project I'll throw that past some of the usual suspects here and see if we can get a response on that transaction that helps okay thank you any other questions we're running transact if none let's move sorry I know just a very quick one but because there's a there's a link this is Angelo I am but is there any example available on how to use transact if it's usable already because there's a link that on the website on the git repo that points to the examples but it's empty so will it be filled at some point or what's the plan there you mean the example on the crates release but no also in the github repo so if you go to the github repo or transact at some point in the rate read me there's written out this is the link to the examples but then you go to the example it goes to another github github repo but it's empty there let me go off to take a look at that yeah oh so there are already examples available are there examples of working transact yes he's referring to the transact contrary though that we currently don't have anything in but where things will get put into eventually yeah I think that really is that eventually we would put some things in there is that a day or do you put the ready planning on that or by the end of the year next quarter first quarter and next year I'll have to follow up on that I don't have an update I know I mean under private health we talk about a couple items that are starting to make use of it like the lives up to the library is starting to make use of it so that'd be an example even though it's just simply using the rust crate yeah library for that and then the new open-source splinter is leveraging some pieces there but far as something that would actually fit in the definition of that example I'll have to follow up on that associated with the link that was just okay so that's the correct so there are other projects using pieces of it to not to the entire transact yeah the idea is really to grow with that component and that grant would grow in alignment with those other efforts but yeah as far as like a standalone transact example that's something we'll have to follow up on got it thanks much okay yeah one reason we recently contributed repo in a project was that we were ending up with two different kinds of examples one is a background noise but when the when the core maintainer team creates examples then those were typically in a regular repo that maintained along the project but then often there would be contributions of things maybe a debris removed by teams separate from from the core project team and so those might not track as closely so that's one of the background behind having a contrib repo as opposed to just having an integrated examples directory in the main all right I guess not so that's good thank you thank you so the last report was for the cello project since I could all people reviewed it and there is no issue raised by the project and no question asked by any of the TSC members so I assume we are good anybody else wants to bring up any issue related shallow now so I guess maybe I do as I was just scrolling through this again I noticed version 1.0 release is that a planned release is that already been released because obviously I don't remember approving the 1.0 for cello yeah that's a good question I read that as something that was planned but maybe it has happened because it says we are redesigning the architecture and finishing the features for v10 so I read that as this is there working towards this but okay so we probably we know do we have anybody from cello here or with somebody who is in the know so I mean I think it's worth reminding everyone that you know projects should not have a major release with that coordinating and going to especially for the first one for the first major release whether it's 1.0 or something else because you have the past that makes you start somewhere else the first hyperledger major release ought to be going through some approval process with the TSC we have an approval process for that we've done this for the in the past there is quite a bit I mean normally there's a lot of you know resources are located to this event because there is press releases security audit all sorts of things happening at that time and so we don't do that too lightly and unfortunately some projects don't seem to be aware and we have already had one case of 1.0 release happening without any you know any process any approval and there was no intent is just not knowing but it's unfortunate so we you know I'm taking this as an opportunity and I agree with you Tracy it's important to raise here for cello we they should be made aware and it's probably worth a comment on the leader under on the yeah I just dropped a comment in there so that people are aware thank you all right let's move on then is Dave back on with a voice yes I am can you hear me I am yes I can hear you now yeah I just wanted to give everybody an update on the they community calendar switch over so I've gone through all of our lists and groups out I have granted moderation status to anybody who followed my instructions last week and said hey would you please make me a moderator of this group what we have left right now that list there are community groups that do not have a volunteer to be moderator and then there's another small group there are community ones where we do have moderators but the moderators are hyperlitric staff so they're like Salona or Rye or me that we would like to have a community volunteer so again I ask everybody on the call take a look at that list if you're a member of any of those groups and you want to volunteer to be moderator being a moderator doesn't really do anything other than give you the ability to edit the calendar and potentially mute people who are being unruly that's about it so we should follow those steps that are crossed out yeah please email me with your your email address with a subject line saying please mod me and I will do that this as soon as we can get everybody here all these groups of moderators will move on to the next step actually those with moderators I'm gonna start moving on to the next step having them move the community events over and hopefully today or tomorrow I will get a quote-unquote new calendar new community calendar up on Google calendar that you can subscribe to so that we have the old one and the new one side-by-side and we can start seeing you know what the status is everything that's it I need to thank you very much all right thank you Dave hey Dave Dan I was just looking for a clarification do you want potentially multiple maintainers to volunteer you just want them to coordinate a single point in contact oh it doesn't matter we can have 10 we can have one it doesn't matter I'm leaving it up to the group to decide what makes sense okay great anything else on the real calendar real risk nope nope that's it for now I just don't want to confuse things let's just focus on one step at a time all right thank you Dave all right let's move forward then so you may have noticed I made a late change to the agenda I was purely structural in response to a comment from Gary who just informed me by the way that he's been he's been hijacked in a customer meeting and he is frustrated that he cannot join this call but he said it's not clear from the agenda what is expected to be voted on so I have actually changed the structure slightly in highlighting the items that I expect us to have a vote on and things that are more up for discussions I do want to highlight that at the harrier river this is not meant to you know prohibit discussions on on the decisions item or vice versa decision on discussion items if the case might be if somebody you know sometimes we have discussion we say hey we are ready to make the decision let's just do it I wanted to be clear for everybody that it's still a possibility we're not precluding any possible ways forward so with that being said there was one thing that we left out last week related to you know the the different proposal that came out of the working group task force there were two related the proposals one was basically to stop you know to drop the notion of working groups as they have been existing and then to transition them to a new type of working group which would not have these requirement of having deliverable to produce deliverables and in the discussion you know the point was made well this quite expensive to change the name of these groups and just like from a website point of view all the information we have the category of groups called working groups it would be better off keeping that name so I have actually put together counter proposal which went through some you know refinement over time over the last couple of days but so which basically says we're keeping the working groups as they are we are merely changing the purpose of the working group making it clear that those working groups are you know they are meant to be about information exchange and not production of deliverables and so my proposal today is to basically you know say no to the first A&B proposals and to say yes to the counter proposal which you know there is one item that is might be worth discussing that came about in the discussion so in the discussion last week I think it was Chris but you know I might have been other people there was this question about whether working group could still produce deliverable or not and I think Chris I apologize if I get that wrong but I think somebody at least said well it'd be clear if we just didn't have that at all because then you don't know what's the what really the difference between task force and working group if we say task force are set to produce deliverables within a time frame the you know maybe it's better to say working groups do not do this and that would mean working groups basically are not expected to produce deliverables and if they want to do that they simply have to basically launch a task force which for which we have defined a process now so it wasn't that's that was you right thanks and and so my proposal states that in the description there is there is this implication is actually highlighted some people's you know I think it was hot and Mark Wagner said well how are we going to enforce this and what not I don't know that we need to go crazy on you know defining a very strict model for this but I think it's worth having that expectation so any questions or comments I don't see a need to prevent the working groups from creating deliverables and it seems unnecessary to create additional bureaucratic steps that they would have to launch a task force so I would be fine with just dropping that that last line from the proposal yeah I mean Chris since you're the one who bought it up how do you feel about not having that in yeah yeah I hear you go ahead yeah so look we keep going around around in circles and what we're saying is that working groups aren't working I you know they're not for working for the for information exchange now I get I don't care what we call them but let's not confuse things by saying oh but you can create something and there's no policing involved if you want to produce a deliverable create a task force there's nothing stopping a working group or any collection of people on the planet from creating a task force none and and so I don't know why we're going through hoops to sort of say yeah but working groups can still produce something true create a task force have it be a hundred percent inclusion of all the people in the working group I don't it doesn't matter but it's a different thing it's the thing that we're looking at as producing artifacts not working groups and again when we think about this you also have to think about are we going to be monitoring working group you know status and composition and all those things I don't know that that really matters anymore other than you know maybe once in a while they're going to need to have somebody else lead the thing and they'll come to the TSC but it should be the thing that we're tracking is stuff that's getting done and how well it's tracking to that so we track task force is not working groups since working groups aren't producing anything they're just all right thank you Chris you made that clear then did you does that convince you or let me give you a counter example so in the DCI working group we have a few deliverables that we're working on one of them is this community survey so it'd be kind of weird when that's one of our main things that we spend our time on to separately spin out a task force that is essentially the exact same thing as the constituency of the DCI working group and then spin out another task force when we have our next deliverable because this is an example you're going set but you're making my point for me I mean so what what how is that going to be at all in invasion or in intrusion into your into into the work you're doing just submit us a request saying hey we'd like to create this task force of stuff that we're already doing and the TSC goes how many and you're done why would I bother doing that we've already we already chartered that work like okay so here's the thing then let's just cancel this whole thing all together because it's stupid to have an argument about whether or not we're producing anything in working groups and then say yeah but you can still produce stuff I think the point of having some sort of governance is that we avoid situations where there's poorly reviewed work so if we had a group that wanted to issue some sort of artifact that was okay and then let's call them special working groups or task okay guys I can see both sides of this I mean you know in Dan's opinion it's like in that case he's describing going through the process of creating a task force just seems to be a stupid administrative burden and why do we need this and I you know I will say I think we're clearly setting an expectation with the task force it doesn't really hurt to say well you know not to say anything about the fact that working groups in some cases might decide to produce something but we might need then to have something to say well how do we control what comes out of it somebody monitoring their baby monitor or something there it's going on there's a pumping I hear the pumping too I think one of the issues here is we're proposing that the work groups would not have quarterly reports and governance you know the current governance by the TSC they'd still be under the TSC but they wouldn't be required to do quarterly reports and things therefore if they want to do a deliverable then you need you know there's no way to report on that right so I think you know and that's what the task force would be so we're saying working groups wouldn't have quarterly reports and things like that where a task force would be required to give ongoing reporting so this is Troy I think I'm still in the same thought as last week that there should be clear separation so I kind of agree with what Chris is saying and I'm not so convinced that if there's going to be deliverables that there wouldn't be governance so I think it's pick one like have governance and deliverables or don't have either okay let's hear from other people anyone else feeling strongly one way another from this is like that from the perspective of the DCI working group I I was actually thinking that this task force would help some of the deliverables because I felt like having some more outside governance could get some of the work done for example our survey has kind of been lagging for the last like month and having a task force and having I feel like would maybe kind of enforce some deadlines or some kind of urgency to get things done at a certain time and having a working group I mean the DCI working group is a little different maybe because it's constantly going to be picking new deliverables each quarter and maybe how we define a task force is slightly different in that situation but I feel like there's some value to having a governing kind of thing on the deliverable rather than the group all right so yes yes I have to interrupt for a second I'm getting a thing from zoom that I'm trying to fix but for some reason it's saying that I don't have a paid account but when I go to validate I do have a paid account but it's claiming it might end the meeting in five minutes so if that happens I will try to reopen the meeting but check the TSC chat list if that happens because that's where we'll have to roll things over to if I can't get the zoom back up so sorry but zoom's been behaving weirdly as of yesterday and I don't know what's going on okay thanks for letting us know that is right I'm trying to fix it but it's you know just I don't want everybody to suddenly get cut off and you know four and a half minutes and go what the hell but I'm trying to fix it so okay somebody didn't like that discussion so if we get dropped would please hang hang around for another five minutes or so and then check on the TSC channel yes hi can you guys hear me now sorry we can thank you for Tracy so yeah so thanks Silona for letting us know hopefully we can keep going please do check the TSC channel in case we get dropped we'll try to resume within five minutes and if it doesn't work then we resume next week wherever we stop so let's get back to this working group proposal so we've heard a few people anybody else feeling strongly one way another I mean the burden I say you know I'll be biased but my proposal actually pretty much says that you know I don't know you're on mute again what does the proposal say sorry it's my phone is playing tricks on the so I was saying so the bias is towards the current proposal where working groups do not produce deliverables and if they want to do that they have to create a task force we heard from Dan that it's unlike that anybody else doesn't like that yes I do not like that because of the following reason currently even the quarterly reports do not get read I saw that identity working group quarterly report was put out one two weeks in advance and all I saw what three people from the TSC are reading it now you're proposing a governance structure in which you will examine the outputs from task forces which are probably going to be more than what is in the working group and you propose that you will handle it I somehow doubt it because of the performance of the people who are in the TSC don't get me wrong I respect you but you guys also have full-time jobs and you probably take a look at these things just before the meeting and hold on hold on Chris so my point is if you want to put this kind of governance on the task forces like hard stress make it very lightweight otherwise for trouble I have to admit I don't understand the report on the identity working group I don't know if we missed it it's you know it's an oversight you should have brought it up no no no you didn't miss it you you were one of the people who kicked off on it but several people hadn't I'm not blaming any one of them I'm just saying that look your workload is tremendous but what does that do with the task force and the working group because because the task force is going to produce outputs that you probably cannot check very in a very detailed manner that's what you're advocating that we don't do anything at all no no no I'm not advocating that but I think we're missing the fundamental point here and make I know you're on and I know you felt pretty strongly about this in the previous discussion the whole impetus for this discussion was to have the working groups be more relevant to what's going on in the projects and that you know having short-term focused task force you know working collaboratively on something that is ideally relevant to more than one project was the thing that we would use as a vehicle to encourage more and that working groups well they were being very effective at bringing people together and having conversations and discussions yeah we have just lost that whole half hour recording yeah I understand I'll sit there and see if I can find it somewhere on my hard drive but it didn't ask me to do the normal save-off that it normally asks people more is back on the hard drive when the meeting ends no matter how it ends I said a bunch of stuff and I probably was speaking to my no but we heard and you called on me to to chime in and that's where we left and then I said I spoke for about five minutes and so I got dropped even before that but again I mean the point here was to find a vehicle to encourage more collaboration on specific deliverables not on so you know again I think we're back at now square one because now you're saying well we still want to have working yeah I agree with that I mean it's a bit unsettling that you know we seem to have gone into a circle here so I hear you then that you know it feels like in some cases might just be an arbitrary burden and purely administrative but you know if we keep it simple enough within the TSE to get those things process it's pretty minor and might be worth the cost well what what is it that you get out of approval well for one thing I mean we have this notion of having a timeline that is set with an expectation of an outcome and a checkpoint that is set by that which we don't have with working groups and if we say working groups are in general just exchanging from you know information exchanger groups then there really is no way for us to say oh but now they are producing something we need to be aware of for you know so if I can just chime in here for just a second please number one the existing from the discussions we've had with the working group chairs have been doing this the most success that we've had in engaging people is when we focus on information exchanges on that in parallel the most success we've had in actually delivering things that have made appreciable impact on hyperledger has been through what we have been formally been calling task forces and all the proposals are doing is ratifying that what we've been doing in reality is the thing that we should be which is focus the working groups on the information exchange for the purpose of engaging projects more directly focus the task force on specifically on time limited deliverables where there's a beginning and an end and you can be held accountable for completing the task in the time that's it countable how it's the task forces that we have right now are all accountable to the TSC this is the way we've been doing it you have one of two choices you can either come back and extend and explain why you need an extension you know why are you not completing it and if lack of interest is the reason then okay we know what to do kill it right if it's not if it is if it's not done and there's no good reason then the task force should end and we have not been doing a job of that with work here so focus on a task limited time if it's not done in that limited time it's done just move on and then and the recharging this is really important because it does provide a sense of urgency for those who need to see the work done in the standards groups we worked on this trick helps tremendously at getting people off off the dime and getting them to provide the feedback they might know otherwise all right so given the time now I would like to move and either we're ready to to make a decision according to the current proposal or we have to postpone to next week and hope that in between people can beat each other up into into agreeing one way or another every decision does not have to be unanimous that's correct so I propose we we vote on the proposed on the proposal as set forward which which proposal there were three of them so no I said I'm asking for I think they cannot be combined because that's not where the issue is anyway the working we say no to A and B and yes to C I second that all right saying thank you mark so anybody in favor say hi anybody objecting okay then is what it does opposed anybody abstaining in none okay so it's here by approved thank you okay so we only have 15 minutes left I have two more discussion items there was the TSC election voter selection I don't want to get into this now what do what I do want to say so what I what what it says on the agenda is the short version of how things have been done for the last election according to Rai I basically prompted him after the call last week and I say so can we document what we've done so far and he said okay this is the short version we have give come commit crawler from Tracy we have nomination from the six and working groups and then people can sell self-nominated I I think then I actually commented and and try to separate the two main issues there is the there is an issue of you know who actually gets eligible to participate in the whole process and then there is the question of how we get contact information which I appreciate I think it's indeed a good separation I my take on this is this is the current process and the default resolution is the current process and I I would say anybody who wants to change this the status quo as the burden to to make a motion basically to say no I think this is how we should do it instead can we agree to this to this process to move forward on this issue so people can comment on the wiki as to how did rather do it what they don't like in this current way of doing it we already agreed by the way that the nomination would not be done by Google form anymore we said we would do that through the mailing list you've have to post to the mailing list say hey I self-dominate for the TSE election it doesn't talk about I think I know the self-nomination is self-nomination if you think you had a commit that wasn't counted rather than self-nomination to the TSE election thank you for the clarification yeah and we we had a form for this that people use I think in the past we did have a form this time yep okay okay so that's the process so again I just want to you know agree on the approach rather than you know I think we're confusing things I think the issue this time this last election was we had a form not the self-nomination where previous years everyone would send mail to the TSE list self-nominating no no but again we're we're Tracy clarified the self-nomination by Google form that this is about is about you know if you want to be added to the list of voters which you know not not to the list of candidates for the TSE which is a separate form okay all right I don't need anybody yes I was going to say I think we have some people on from Bezu do we want to cover that yes that's why I wanted to not go deeper than that on this issue now so we have had this request filed a few weeks ago now from the Bezu team on on their desire to move their project from incubation into active status there was a fairly extensive well put together I have to say you know request put on the on the wiki and it generated a lot of comments and questions some of which have been answered some of which seems to be pending and you know as I've yet to be answered so I thought we could use some time and we only have 10 minutes left but let's please use those 10 minutes to try to see if we can move forward I do have to say and I put an extensive comment along those lines that you know I was a bit surprised this came that early although the Bezu team mentioned that intention early on when they made their initial proposal for the project I had already pointed out there would be a challenge to do that quickly and and you know as far as I'm concerned the challenge remains and it's been commented by several people that you know there is a problem with the regard to the diversity in terms of control of the project all the maintainers are basically from Pegasus and this you know there's this question we have used before you know and said well essentially if one company if the project would not survive a single organization walking away that's a bad sign right and active status has nothing to do with we had extensive discussions on that in the past has nothing to do with the the maturation the maturity of the product they are developing but really the maturity of the community the project and so how it's organized how is everything set up and whether there is actually diversity in the community and it's a fully fledged community that's functioning and it's often been the challenge for many projects you know to achieve to meet that criteria because we often have project that gets started from one company or a couple and then it's hard to grow from there even with all the good intentions so I think you know this is a point that needs to be addressed from that point of view I don't think it's fair to to to put it up for a vote I don't honestly don't think that the Bezu project really qualifies for this the point has been made by civil TSC members we could have a vote down just for the sake of it but I don't think that serves any purpose I'd rather have a discussion and I think Grace actually commented saying well you know could you please tell us exactly what we need to do to to be able to qualify if we don't which I think is a fair question although there is a set of executia that we have defined and of course you know they have they there is always room for interpretation right because if you read the request they think they qualify and they are you know an answer to all the questions but there was another point I wanted to make which was I don't know but now so I'll leave it alone anything else anything else anybody Gary sounded like he had wanted to say something at the beginning rejoinder Gary definitely wanted to say and I'm sure that's why he's frustrated not to be able to be on the call but we usually have other opinionated people so I'm happy to hear from anyone or from anyone from the Bezu team who might be on the call and wants to speak up Hey Erno this is Grace and I'll get you to see just wanted to I guess point out that we're on the call and thank you first for everyone being very thoughtful and asking really great questions to the proposal um just wanted to call out so we have kind of three different organizations from Bezu on the call right now um so just to help kind of run up the discussion that way so myself um Daniel Heyman and Dan O'Farran from Pegasus, Antony from Danier from Web3Labs and then Bob Summerwell from ATC Cooperative uh so just wanted to I guess uh you know we kind of have these two organizations kind of I think there were a couple of outstanding points that you kind of hinted at with um you know our request and what we're looking for to kind of help us uh make the progression to active status so uh I think the couple of outstanding points as of a few weeks ago was the Jira board migration which is uh the Jira tickets have all been moved to the Hyperledger Jira board uh as of last week we currently have the um Pegasus one just staying open until the next week or so to make sure the transition is as smooth as possible and and nothing gets missed but everything was moved as at this point and then the other one so diversity around the project so just wanted to say that we have um now as of yesterday conveniently enough uh EGC and Bob was providing some context on uh their work and kind of their kind of becoming the third organization there so I think yeah just kind of what I was saying happy to answer any questions you'll have but um the only strict requirement uh that I could see around diversity was the three organizations which we now have um so if there's a way to help us kind of there's a percentage if there's a way to help us kind of meet that requirement in a different way that's not listed in the uh in the exit criteria that would be really helpful so that's I think that's what we're looking for this morning but anyway I'll open the floor for questions okay thank you I remember the the second point I wanted to bring up which also is related to the governance aspects of the project which is key to this active status as I was saying and I had noticed that in going through the Gita brief of the the project that there was this governance document that basically stated you had the you had the dictatorship model and um can I speak on that? a benevolent dictator and I don't know what happened because I raised that and nobody answered can I speak on it to that point yes please so that was from the previous iteration when we moved over we forgot to clean that document up when you pointed it out we deleted it immediately okay so that's good to know um anyone else any questions so Chris I know sorry go ahead Tracy no no worries uh so can can you comment on like when Orion is uh something that you guys are planning to bring over type or ledger if you are planning to meet over maybe you're not planning on it and I think that was a question that I saw that I don't know a lot of conversation around it first off Orion is the piece that provides confidentiality basu does not need Orion operate in an enterprise context to get the permission list and the permission ledgers all I need to do is change the consensus algorithms and basu has right now three main consensus algorithms the proof of work the click which is a proof of authority which uh enterprises use and the ibf tv2 which enterprises use so we provide all the same functionality described in the architecture white paper that's needed for a permission network got whitelisting a lot of the other things what Orion brings in is the um off ledger storage um with confidentiality by way of only sharing with a few select parties and that's not a requirement for an enterprise level um enterprise level uh blockchain so basically it's complete right now as we're bringing Orion over um it's something that we've talked about we haven't committed to it yet but the one thing we did decide we wanted to go through was we wanted to get the basic code base in we want to see what the bumps were what the process was before we try to bring too much in because if we tried to it's like you know how to get an elephant through a door you get it in one leg at a time so we need to make sure that we get everything in first um before we start bringing the other pieces and you know there were some pretty big bumps just getting the basic code base in a lot of things like like JIRA and Circle CI integrations so a lot of that's driving why we didn't just bring everything in at once we wanted to get small pieces in the words completely yeah and if I can just jump in and add to that Orion is just one mechanism by which you can achieve confidentiality on Beisu there are zero knowledge proof based approaches that are compatible there are conversations about integrating third party private transaction managers and off-chain privacy approaches into Beisu so it feels a little like one one of the reasons for caution is it feels a little strange to focus on integrating Orion and putting it in a different class from these other privacy approaches all right thank you so I actually I was going to ask about this I know Chris I'd ask about this so thanks Tracy this is the question yeah I I think the other question obviously is around diversity of maintainers I think uh you know originally we had one maintainer who was not from Pegasus and all the other ones were from Pegasus and so I mean to me that still implies that this project is dependent on Pegasus remaining viable if you will right because one maintainer cannot take on everything that exists especially when they're only focused on kind of the privacy aspects of things so uh I know you guys mentioned Bob is he becoming a maintainer is that like a second out of the you know 25 or so folks who are going to be non Pegasus maintainers or is Bob just starting to contribute short to go you know I don't know if you want to speak to our maintainer process but so yeah I think Bob would chime in talking about ETC cooperative I don't want to speak for ETC co-op I was hello I can I can certainly speak um yeah I mean to be fair we only have one minute left but you can start and I'm happy to you know to bring it up next week we can continue the discussion obviously it was disrupted today so but go ahead if you want to say something it looks like Bob dropped off well there he is hello I'm black can you hear me yes um so yeah I'll be very quick um chain safe have been uh doing the work for ETC support it's pretty much pretty much finished just finishing on the upstreaming the plan moving forward is ETC co-op is committed to this code base forever uh whatever Pegasus does um you know in the majority we would be uh you know having contractors doing the work as opposed to doing it ourselves because there's just two of us we are both engineers but we don't have time um you know uh capacity may be built up within the co-op or we may just give grants to other people to do work as needed um but irrespective of the way it works um you know that that's something that will be a long-term commitment forever all right thank you I apologize I've really a hard stop and so I have to close the call on this but obviously this discussion will carry on thank you all today for joining talk to you next week and bye


In this case study, we're going to be looking primarily at a type of portraiture called faeum portraits. These were mummy portraits that were painted during the late Egyptian period and the reason that we call them faeum portraits is that most of them were found in an area of Egypt close to the faeum oasis. They're sort of a depression to the west of the Nile Delta to the west and a little south and there's a series of lakes there and communities and many of these late period Roman mummies were found there. And I'm showing you here a selection of these faeum portraits. As you can see they are painted on wood panel. Most of them are painted either, well they tend to be painted either in in caustic, which is the technique we're going to pay attention to in this particular case study. Some are painted in tempera. So within caustic what you're doing is you're suspending your pigment in melted beeswax. Sometimes that beeswax is mixed with other substances. It can be mixed with oil to form something that dries and hardens more slowly and can be worked for a longer period or it can be mixed with types of varnish and other things. With tempera on the other hand you are mixing your paint with some sort of a binder like egg yolk or egg white or whole egg and painting with it that way. The more expensive portraits tended to be done with in caustic. Here we're looking at the portrait that was on the right in our image earlier and taking a closer look we're looking at her from sort of a raking angle so that you can see some of the texture of the in caustic paint and then just a close-up of this young woman's face. And one of the advantages of working in the in caustic medium is that of course beeswax is translucent and depending on how saturated it is with pigment you can actually build up sort of semi-transparent layers of this paint and get sort of a luminous quality that is a very good imitation of human skin and the way that light plays on human skin. And I think you can see that particularly in the close-up image on the right where we see all of the different shades in this young woman's face. You can also see a variety of different textures, little swirly patterns or little quick dabs or slashes made with the brush. When you work with in caustic you have to work very quickly because it hardens right on the brush almost the moment you take your brush out of the hot wax and so you have to have a pretty good idea of what you're doing before you even grab your brush or the tool that you're working with. You can heat the surface that you're painting on to some degree and by warming it up extend the amount of time that you can paint but you have to work very quickly and you tend to build up sort of solid layers that end up having a bit of a sculptural effect because of just that buildup of the wax. So it's a really interesting way to work. Now we have a view and a detail of a male portrait, another one of these Faya Mummy portraits, and I want to point out a couple of things. First, take a look at the relative state of disrepair on this particular work and because of the flaking paint on the surface you can get a sense for how thickly the layers build up on the wood surface. You can also get a sense of how this would have been placed into the wrappings of the mummy.  The rest of this would be covered up in mummy wrappings and so this is just standing in for the face of the deceased. There's a real emphasis on the eyes of these. In the ancient world there were widespread beliefs that eyes were the windows to the soul and of course in the Egyptian tradition they believed that the soul lived on in the afterlife and needed a home to go back to in the form of the mummified body of the deceased and also other statues that would be provided and so perhaps these eyes are allowing particular access for the Ka. Recently works like these Faya portraits have received a lot of scholarly and particularly scientific attention and there have been a number of groups worldwide that have been analyzing these Faya mummy portraits. There was a huge project in Germany that well it was started in Germany that spread also into Italy and into parts of Egypt to Mount Sinai for example that was a look at painting techniques for the representation of human flesh between about the year 250 and 1200 and they they did these really in-depth analyses including pigment analysis and one of the things that I'm showing you here is this is on the right sort of an ultraviolet light look at the painting that you see on the left and when you expose certain pigments to UV light they fluoresce and so here what they're doing is identifying the presence of Egyptian blue which is a synthetic cobalt based glass pigment and it's does tend to fluoresce under those light conditions. A slightly more destructive way to study a painting but one that gives a great deal of information is to take a cross section of a layer of paint. This is usually done in an area very close to the edge of a painting or in an area that's already been damaged and here you're seeing sort of a microscopic view of a cross section of paint and you can see that there are at least three distinct layers and again you're looking you're seeing it analyzed under various types of light including I think x-ray in the image on the bottom. When you zoom way into one of these encaustic portraits one of these Faya mummy portraits you can see a lot of the individual colors that were laid next to each other and on top of each other in order to create effects and so here we're looking at a woman's portrait and at a close-up of the way that her eye was painted and in a moment we'll see a short clip that reproduces that technique. What we'll do now is look at the way that an eye very much like the one we saw on the last slide was painted and this is something that was achieved through analysis of paint sections and also just really close microscopic analysis of the painting and so what I want you to notice is that almost all of the colors in this painting are ochre-derived or ochre-based colors so here even in the background we have sort of a pinkish tone that could be red ochre with a lot of white in it now we have this sort of buff tone that's yellow ochre with a lot of white now we have like a dye an orange ochre that's been lightened and then we're getting closer into sort of a red ochre like a burnt sienna but all of these are earth pigments they're incredibly stable and light fast they hold up over time very well and now finally as we start getting darker you'll see that eventually the artist will bring in full black here and then for that final pop the white. This is our final slide in this case study and I want you to notice the photo of the little steel tool at the lower left this is a reproduction of an encaustic wax working tool that is based on the marks that were found on the painting that you see here and as you can see on then the top two images you see it sort of straight on and then examined with raking light so that you get really high contrast imagery that gives you a sense of sort of the topography of the painting and then there's this wonderful magnified view at the lower right in which you can see the diamond shapes that were created by the tool being pressed in to manipulate the wax metal tools like this could be heated up and used to move around the wax on the surface of one of these paintings and to to further mix and move the paint for different effects. You're going to be watching another video about works like this in which Maurice Boboda who is a conservator at the Getty Villa in California will discuss a little bit more about ochre and the way that works like this were made


Hello and welcome to this session. In this session we will discuss a question which says that find the solution of the given system of equations. And the equations are y is equal to log x plus 1 to the base 2 and y is equal to 5 minus log x minus 3 to the base 2. Now let us start with the solution of the given question. Now we have given this system of equations. Now let this be equation number 1 and this be equation number 2. Now this is of the form y is equal to f of x and y is equal to g of x. Now the solution of this system of equations will be given by the equation f of x is equal to g of x. Now this is f of x and this is g of x. So this is the solution of the system of equations is given by f of x is equal to g of x. So we have log x plus 1 to the base 2 is equal to 5 minus log x minus 3 to the base 2. Now we need log terms together. This implies log x plus 1 to the base 2 plus log x minus 3 to the base 2 is equal to 5. Now by using the property of log ribbons we know that log n to the base b plus log n to the base b is equal to log nn to the base b. So using this property we have log 1 the whole into x minus 3 the whole and this complete whole to the base 2 is equal to 5. Now by definition of log we have y is equal to log x to the base b. If the log is x is equal to b raise to power y x plus 1 the whole into x minus 3 the whole is equal to 2 raise to power 5. And this implies x square plus x minus 3 x minus 3 is equal to 2 raise to power 5. Now this implies x square plus x minus 3 x is minus 2 x minus 3 is equal to 2 raise to power 5 is 32 which further implies x square minus 2 x minus 3 minus 32 is equal to 0. And this gives x square minus 2 x minus 35 is equal to 0. Now this is the analytic equation in x so we will solve this by definition. Now by definition of log n term this implies x square minus 7 x plus 5 x minus 35 is equal to 0. Now this implies now from these 2 terms taking x common it will be x into x minus 7 the whole and from these 2 terms taking 5 common it will be plus 5 into x minus 7 the whole is equal to 0. This implies x y is 7 the whole into x plus 5 the whole is equal to 0 which implies x is equal to 7 and x is equal to minus 5. Now for x is equal to minus 5 the values of y in both the functions is not defined because log of negative numbers does not exist so we will start x is equal to minus 5. Now we are left with only x is equal to 7. Now let us find corresponding values of y for x is equal to 7. First of all let us put x is equal to 7 in equation 1. So we have y is equal to log 7 plus 1 to the base this implies y is equal to log 8 to the base 2. Now again by using definition of log we have 2 raise to power y is equal to 8 this implies 2 raise to power y is equal to now 8 can be written as 2 raise to power 3. So this implies y is equal to 3 because this is same so we can equal the parts therefore for x is equal to 7 we get y is equal to 3 the solution of the given system of equations is order pair 3 7 and this completes our session hope you all have enjoyed the session. .


So there's obviously nothing to say and there's obviously no one to say it to and yet words happen spontaneously Without a doer without a controller without a center Like leaves rustling in the wind and it's free It's totally free It's impossible to go somewhere because it's always it Every move every word is always it. It's always already empty without an entity without a path Although it can appear as a path It's free to do so the freedom of No longer being attached to saying it Because it's not possible to say at every word is it and so there's so much just joy joy of being Normal Ordinary just whatever is appearing water drinking Video streaming simple ordinary love Just nothing with nothing joyfully playfully abundantly Where would the sky go? To be itself Where would the wind go to be itself? Where could the ocean go to get wet so free already It's always been this way Apparently born as nothing and then it apparently is nothing and then it apparently passes or dies as nothing And nothing really happened and nothing really changed and nothing was ever Contracted and nothing was ever expanded They may have appeared so but that's all just a story There's no need for a conceptual Conversation or to communicate ideas Although every idea or concept that said is still it And yet this body continues to be excited about dows and About basic needs and freedom But no matter what function is Apparently happening in the body as the body. It's freedom high in the live chats beautiful comment about crying because being taught to play the the game and Wasting apparently 60 years trying to win and it doesn't even exist Better to just stop playing the game Because it's already nothing and Every move is checkmate Every move is freedom Every single move is nothing happening There's no winning when it's already the prize You've never left the prize And there's never been an entity. There's never been a location There's only been that sky that wind hmm Although there can be an appearance of there being a lack of of it of not being it and then some sort of a Path or pointing to it. That's also all it. That's also all freedom. It's already nothing everywhere It's already that freedom everywhere Everything that said every movement that's made is already nothing moving It's already freedom Talking freedom listening. There's no way to leave freedom There's no way to leave freedom There's no way to leave Freedom the freedom of there not being a way to leave freedom There's no knowing it. There's no understanding or comprehending it Because it's already Yeah, interesting comment about never being able to play the game correctly With neurodivergence and all blessing in disguise Yeah, in a way, it's it's really beautiful to To not fall for the idea that I lack and I need and I can find it in society's attainments Very big big blessing. Yeah, it just simply is as it is And it's all freedom Already, it's all love already. It's all emptiness already Empty ising already And all these words fall short and yet all of them are it Because it cannot be said The freedom of it not being able to be said and yet every word is it Yes, we are so free free to pretend we are bound Yes Free to pretend every single idea imaginable, it's impossible to not be free It's impossible to not be nothing And there's so much beauty and freedom in just being nothing which was always the case Because there's nowhere to go nothing to attain there can just be a raw beauty and awe and Wow to just what is Without ever trying to control it or manipulate it in order to fulfill Some lack. Yeah, there's no control and there's no problem that whole thing of bouncing around between Problems endless problems Goes away, you know, you can beautifully just hear the wind right now Here in Austin, Texas you can hear it It's just so palpable like it's not a single entity in that wind There's not a single idea in that wind. It's just pure innocence pure freedom pure spontaneity and these little Very light rain too. So there's little raindrops sliding down the window just perfection Nothing ever had to be done for this to be perfect and yet there's an appearance of lots of salesmen's of maps and paths and Techniques and the appearance of lots of spiritual seekers That want to try to use those to find this What's impossible to be missing the freedom that it's already freedom The freedom that every move is freedom The freedom that every thought is freedom the freedom that every appearance is freedom the freedom that Bondage is freedom. It's not possible to leave freedom It's not possible to leave the perfection The empty unspeakable perfection that are these words and that is this listening That is this watching that is rubbing This facial hair and cheek what's looking out all eyes is empty free infinite Perfect without entities or locations or names or time. It's just so pristine It's incorruptible Uncorruptible the uncorruptible freedom that is already hearing this voice Watching this video Speaking these words it doesn't require reading any ancient scriptures Doesn't require any Meditation it doesn't require anything because that would be a condition And what is being said is unconditioned appearing as what may be Trying to find by reading a book or by meditating. It's just unspeakably perfect Ordinary Wow There's nothing extra ordinary about it. There's nothing special about it. There's no attainment about it There's no knowing About it.  It's already that purity and spontaneity.   So free. Oh, I've left it. No, you haven't. Never can. It's the ordinariness of what's appearing. How can one leave the ordinariness of what's appearing? How can one leave what's appearing? Impossible to leave what's appearing. I'm so grateful for the fam in the live chat. As long as there's looking for something to attain, there's the appearance of mutually assured destruction. It was a question in the chat about if there are dreams and what are they like? Yeah, there are dreams and there are just dreams. That was good to say.  And I finally found wholeness in those dreams.  That was her on the mic a moment ago.  Gotta get in that booty hole of papa, too. Gotta take papa's dick, too. It's pretty big.  Yes, they need the dick, too.    Imagine those kinds of inquiries to the presidents of nation states. So what's the what's the girth down there, president? How's the how's the wife's pussy? How is how's it going?  How is it? Pretty good. Have any threesomes recently? What if what if I took a took a stab at your husband's back door? Would that be okay? And what if I was to try to fulfill the wife? Or what if the presidents of the nation states were banging it out? What if we had these the presidents of nation states just ramming each other online, just watching them ram each other, just give each other the D. All of a sudden, so much relaxation for those tight okay, so free it can appear like whatever. Thanks for tuning in. all ready ya freelance freedom, freedom, freedom, freedom, freedom, freedom, always already freedom, freedom, freedom, mobile freelance


Hi, this is Sabiru. I work in Depot Units for PAS1 here and I have been a system admin for the past 3 years. Now my topic is about why running puppet in a standard one mode or why configuration management is important for 0 plus systems. Puppet is generally used as a client server architecture. It is used in a client server architecture, but there are several problems that you will face when you are using it in a client server architecture like certificates and there is a problem of scaling up. You can scale up using passenger or mongrel or any other stack server, but there is always a cost to it like the complexity and the cost of running the stack itself. So I propose an alternative solution or like many people are doing it and we are also doing it. It is like using puppet in a standard one mode. There is an inbuilt compiler and let's see how do we use it in that. So there are several problems in doing that and there are several advantages also. There are several challenges also. So let's have an open discussion and then let's all share our views about this. I will share whatever I have done in the past 1 year in running it in a standard one mode.


Hello, and welcome to this presentation of the STM32 MP1 Reset and Clock Controller, or RCC. The RCC is a complex block closely working with the power controller block. So, before going through this slide set, please have a look at the power control module. The RCC offers several clock sources, three internal RC oscillators, two oscillators using an external crystal or resonator, and four PLLs or phase locked loops. The clock distribution block uses all those clock sources to provide a flexible set of clocks for peripherals, bus interconnects, and processors. The clock gating control block is in charge of the gating of the clocks in order to optimize the power consumption. Many peripherals have their own clock, independent from the bus interface clock, allowing the user to dynamically change the bus interface clock without affecting the peripheral interface rate. The STM32 MP1 RCC provides high flexibility in the choice of clock sources, which allows the application to meet both power consumption and accuracy requirements. In addition, the RCC also embeds a reset control block, generating the reset for the complete system. Finally, the RCC register interface, trust zone capable, allows the application to properly control each function of the RCC. The RCC can be fully controlled via registers. The RCC offers trust zone capabilities and can handle three kinds of secure attributes. The always secure registers. Those registers can be modified only by performing right secure accesses. The secureable registers. Those registers can be switched to secure or non-secure mode via two bits, TZEN and MCK PROT, located in an always secure register. TZEN and MCK PROT bits enable the application to control the security perimeter. This is detailed in the next slide. And the non-secure register. Those registers can be modified by secure and non-secure right accesses. On top of trust zone, some registers of the RCC can only be written by the MPU. This is the case for the registers offering services dedicated to the MPU. Those registers are also sensitive to trust zone, so it is possible to have registers allowing only secure right accesses performed by the MPU. The following access rules apply for the RCC. All registers can be read without restrictions. The MCU is also allowed to read registers dedicated to the MPU. A secure register can only be modified by a secure writing. A non-secure writing into a secure register generates a hard fault. Non-secure registers can be modified by secure or non-secure right accesses. And the MCU cannot write into a register designated MPU only. At the RCC level, the trust zone feature prevents a non-secure application from performing a reset or disabling a peripheral used by a secure application. The figure gives a simplified view of the trust zone perimeter. The RCC can be in three different protection modes. The first mode is the non-secure mode, TZEN equals zero. In this case, all registers can be accessed in a non-secure way. Some registers are still protected against master accesses other than the MPU ones. The second mode is the secure mode with TZEN equals one and MCKPROT equals zero. In this case, peripherals located in the APB-5 and AHB-5 domains can only be used in secure mode. The DDR and MDMA are also protected, as well as all the required interconnect buses and clock generators. In this configuration, the secure peripheral shall use clocks provided by secure elements. And the third mode is the secure mode with TZEN equals one and MCKPROT equals one. This mode is similar to the previous one, but the perimeter is increased in order to also secure the MCU subsystem. Now let's focus on the reset part of the RCC. The RCC offers a rich set of safe and flexible reset management without any need for external components to reduce the application costs. The RCC manages several types of resets, the power-on reset, the system reset, the local resets, and the backup domain reset. Thanks to the voltage monitoring included in the PWR block, the filters embedded into the NRST pad and the RCC reset control, the amount of external components is significantly reduced. The first type of reset is the application reset, which resets most of the registers except the ones located in the backup domain. Many sources can generate an application reset, an invalid voltage on the VDD supply, see the PWR block for details, an invalid voltage on VDD due to a brownout function. The brownout function allows the user to choose their own threshold levels for the VDD supply, see the PWR block for details. A low level on the NRST pad, a timeout from one of the independent watchdogs, IWDG 2 and 1. Software reset request initiated by the Cortex-M4, the MCU, if the option bytes allow it. Software reset request initiated by the Cortex-A7, the MPU, the RCC registers, or a failure on the HSC oscillator. Note that the application reset asserts the pad NRST, allowing the reset of external components. A system reset is generated when the application reset is asserted, or when an invalid VDD core is detected, V-core RST. This situation appears after a power-on sequence, or when the chip exits from standby mode. The option bytes configuration and the memory repair sequences are triggered every time an invalid VDD core voltage is detected, or when an application reset occurs. The block named RPC-TL, or reset pulse control, allows the application to define the minimum activation time of the NRST pad. The block named RD-CTL, or reset delay control, allows the application to delay the activation of the system reset until the DDR is in self-refresh mode. Those two blocks will be explained later. The backup domain reset occurs when the VSWRST bit is set to 1 by the application. As shown in the figure, this bit is located in the RCC-BDCR register. When the VDD and VBAT are both powered on, if both supplies were previously off. The MPU reset is performed when the MPU resets one of its processors via MPU-PXRST bits. One processor can be reset without disturbing the other. The snoop control unit is not reset. When a system reset occurs, or when the system exits from C standby mode if allowed by the PWR management. The MCU reset is performed when the MPU asserts the MPU-RST bit, when a system reset occurs, when the window watchdog is not reloaded at the right moment, or when the MCU requests a system reset. The reset of the system can be blocked by an option byte, but the reset of the MPU is performed. The peripherals are reset either by their respective reset bit on RCC registers or by a system reset. The debug parts are reset when the bit DBGRST is asserted on request of the DAP or when the VDD core is invalid. The table is a simplified view of the parts reset by the most important reset sources. The power on reset or PORRST is the reset having the largest coverage. It resets all the logic located in the VDD domain and most of the logic of VDD core. The logic located in the backup domain powered by VBAT and the logic located in the VSW domain are not reset. Note that the power on reset also triggers the system reset and APPRST, and the NRST pad is asserted during the power on reset. The application reset or APPRST resets most of the logic located in the VDD core domain except some resources located in the RCC and the PWR. The backup and VSW domains are not affected by this reset. The system reset or NRESET resets most of the logic located in the VDD core domain except some resources located in the RCC, the PWR. Debug components, IWDG2 to 1 and the backup and VSW domains are not affected by this reset. The V-CORE reset or V-CORE RST resets most of the logic located in the VDD core domain except some resources located in the RCC, the PWR. The IWDG2 to 1 and the backup and VSW domains are not affected by this reset. The backup domain reset or NRESET VSW resets all the components located in the backup and VSW domains which contain the RTC and the external low speed oscillator, the backup RAM and the retention RAM. The reset pulse control block allows the application to control the minimum activation time of the NRST pad. This feature is particularly helpful because some external devices may request a minimum reset duration for the activation of the NRST. The reset pulse duration can be adjusted from 1 to 31 milliseconds with the accuracy of the LSI oscillator. If the LSI is switched off when a reset occurs, the LSI is switched on as long as it is needed by the RPC-TL control register. The reset delay control block allows the application to set the external DDR device into self-refresh mode before generating a system reset or NRESET to the circuit. When an application reset occurs, C1, the RDC-TL maintains this reset active and prevents the propagation of the system reset, C2. Then the RDC-TL requests the DDR-PHY to switch the DDR into self-refresh, C3. Once it is done, the RDC-TL asks the PWR to switch DDR pads to retention, C4. Finally, the system reset is propagated, C5, and the application reset is no longer maintained, C6. If the DDR-PHY does not answer to the self-refresh request, the system reset is propagated to the circuit after a timeout delay programmable by the user. The RDC-TL block can also be bypassed if needed. The RCC stores the reset root cause into two registers, RCC-MCRSTS and RCC-BRRSTS. The boot ROM can check and acknowledge the reset root cause via the RCC-BRRSTCLRR register. In addition, the boot ROM updates the physical register RCC-MCRSTS via the RCC-MCRSTSETR register. The MPU can check and acknowledge the reset root cause via RCC-MCRSTCLRR register. The MCU can check and acknowledge the reset root cause via the RCC-MCRSTCLRR register. The hold boot function allows the MPU to maintain the MCU in a frozen state every time the MCU is reset. After a system reset, the hold boot function is enabled and the MCU is frozen. The MPU can then load the application code into the MCU SRAM and allows the MCU to run by setting the bit boot MCU to 1. When the circuit is running, the MPU can decide the behavior of the MCU after an MCU reset. The MCU can simply reboot after an MCU reset if boot MCU equals 1. Or the MCU can remain frozen after an MCU reset if boot MCU equals 0. The MPU can decide which processor is allowed to restart its application after a standby mode. This feature is controlled via two bits, MPU-BEN and MCU-BEN. For example, when the system is in standby mode, if an event wakes up the system, the boot ROM checks if the MCU must be activated or not via the MCU-BEN bit. If the MCU needs to be activated, the content of the RETS SRAM is checked or not by the boot ROM code before giving the control to the MCU. The MPU application boots or not according to bit MPU-BEN. If the MCU needs to wake up the MPU, it can generate an SEV event. Focusing on the clocking part, the RCC offers a large choice of clock sources which can be selected depending on low power, accuracy and performance requirements. The STM32MP1 microprocessor embeds three internal RC oscillators. A high-speed internal RC oscillator or HSI which can work at 64, 32, 16 or 8 MHz. A low-power internal oscillator or CSI working at 4 MHz. And a low-speed internal 32 kHz RC oscillator, LSI. It also embeds two oscillators working with external crystals or resonators. A high-speed external 8-48 MHz oscillator or HSE with a clock security system. And a low-speed external 32.768 kHz oscillator or LSE also with a clock security system. Four PLLs are also available, each with three independent outputs for clocking different peripherals at different frequencies. Note that the USB and DSI have their own dedicated PI. The high-speed internal oscillator is a 64 MHz RC oscillator with an accuracy of 1% and a fast wake-up time. The HSI clock is trimmed during production testing and can also be user-trimmed. A dedicated divider allows the generation of a 64, 32, 16 or 8 MHz clock. The HSI clock is selected as system clock for the MCU when the system wakes up from system stop mode. The HSI clock remains powered when the system goes to stop mode in order to speed up the wake-up time. Some peripherals such as the I2C's and UART's can request the activation of the HSI clock in system stop mode for their own processing. If the HSI is disabled, the RCC automatically enables the HSI and provides this clock to the peripheral which requested it. The low-power internal oscillator is a 4 MHz RC oscillator with an accuracy of 5% and a fast wake-up time. The HSI clock is trimmed during production testing and can also be user-trimmed. The HSI clock can remain enabled when the system goes to stop mode in order to speed up the wake-up time. Some peripherals such as the I2C's and UART's can request the activation of the HSI clock in system stop mode for their own processing. If the HSI clock is disabled, the RCC automatically enables it and provides this clock to the peripheral which requested it. A crystal or ceramic resonator working in the range of 8 to 48 MHz can be connected to the HSI clock. The HSI can also be set in digital bypass mode and receives a digital clock on the OSC-IN input. In analog bypass mode, a clock with a reduced amplitude down to 200 mV peak-to-peak can be used. A clock security system allows an automatic detection of any HSI failure. In this case, an application reset is generated and a failure event is provided to the temp block, allowing the protection of backup registers and the backup RAM. Some peripherals can request the activation of the HSI clock in system stop mode for their own processing. If the HSI clock is disabled, the RCC automatically enables it and provides this clock to the peripheral which requested it. The boot ROM must use the HSI oscillator when a boot is requested via the USB port. For that purpose, the boot ROM needs to know how the HSI clock is used in the product and configures it properly. The OSC-OUT must be connected to ground via a resistor in order to inform the boot ROM that an external digital clock is provided as HSI clock. The OSC-OUT must be connected to VDD via a resistor in order to inform the boot ROM that an external analog clock is provided as HSI clock. If pull-up or pull-down are not detected, then the boot ROM configures the HSI in oscillator mode. The STM32MP1 microprocessor embeds an ultra-low-power 32 kHz RC oscillator which is available in all modes except in VBAT mode. The HSI clock can be used to clock the RTC, LPU arts, some RCC blocks, low-power timers, and the independent watchdogs. The 32.768 kHz low-speed external oscillator can be used with external crystal or resonator or with an external clock source in bypass mode. The oscillator driving capability is selectable in order to adapt the oscillator characteristics to the external crystal device. A clock security system monitors the failures of the LSC oscillator. In case of failure, the application can switch the RTC clock to the LSI clock. The clock security system is functional in all modes except VBAT mode. The LSC clock can be used to clock the RTC, the USARTS, or low-power UART peripherals and the low-power timers. The PLLs embedded in the device provide a flexible way to generate the wanted frequency for the system or peripheral clocks. The STM32MP1 microprocessor integrates two PLL 1600s. The input frequency must be between 8 and 16 MHz. The VCO frequency must be in the frequency range of 800 to 1600 MHz. The PLLs also provide three different outputs, which are all derived from the VCO frequency divided by two via post dividers, DIVP, DIVQ, and DIVR. In addition, it is possible to change the values of the post divider without disabling the PLLs. The application just needs to disable the corresponding post divider, change the division ratio, and re-enable the post divider. In order to get a duty cycle close to 50%, the application has to program the post dividers to even values. The PLLs can be switched in fractional mode, allowing a high precision in the VCO frequency. The 13-bit fractional divider can be changed without disabling the PLLs.  Finally, the PLLs integrate a spread spectromechanism in order to reduce the amount of EMI, more especially for the DDR interface. The STM32 MP1 microprocessor also provides two PLL 800s. The architecture is very similar to the previous ones. Those PLLs are more dedicated for the generation of the medium speed clocks. The input frequency must be between 4 and 16 MHz. The VCO frequency must be in the frequency range of 400 to 800 MHz. Other functionalities are similar to the PLL 1600. The slide shows the relation between the input and the output frequency of the PLL for integer and fractional modes. The application shall take care to respect the frequency range for the VCO and for the clock frequency of the signal provided to the PLLs. The spread spectrum clock generator, or SSCG, performs a triangular frequency modulation of the VCO frequency using a 16-bit fractional divider. The application can adjust the modulation period via a mod per field, the modulation depth via a mod ink field, and the modulation mode via the SSCG mode field. This option allows the SSCG to generate a modulation either centered on the VCO frequency or lower than the VCO frequency. The SSCG is mainly used for the DDR interface as it is an important contributor to EMI interferences. This is due to the amount of IOs toggling at high frequency with steep edges. The SSCG does not significantly affect the jitter because the modulation frequency is very low compared to the speed of the DDR interface. The modulation frequency is generally in the range of 20 to 50 kHz, and the modulation depth is around 1%. The small plot shows an example of the effect of the clock spreading. Spreading the frequency over a limited frequency band spreads the power of the signal over this band, reducing the peak of power. The red signal is the VCO output without SSCG, and the black signal is the VCO output with SSCG. The oscillators don't deliver a clock if they are not ready. The ready flag is based on a temporization. This temporization is bypassed for the LSE clock when the LSE is in bypass mode. The control of the oscillators can be switched in secure mode when the TZN bit is set to 1. The HSE, HSI, and CSI oscillators provide a kernel clock dedicated to peripherals and a system clock. Those clocks are identical except the gating logic. The PLL1 and PLL2 can use either HSE or HSI as reference clock. The PLL3 can use either HSE or HSI or CSI as a reference clock. And the PLL4 can use either HSE or HSI or CSI or I2S CKIN as reference clock. The PLL1 is dedicated to the MPU. The DIVP shall be bypassed or use even division ratios in order to ensure a duty cycle of 50%. The PLL2 is dedicated to the AXI subsystem to the GPU and to the DDR. The PLL3 is dedicated to the MCU subsystem and to peripherals kernel clocks. Finally, the PLL4 is dedicated to peripherals kernel clocks. Each PLL has a dedicated pre-divider in order to adjust the reference clock for each PLL. Note that the PLLs clock source must not be changed if one of the PLLs is enabled. In addition, the generation of the MPU, AXI, GPU, and DDR clocks can be switched to secure mode. If desired, the generation of the MCU clocks can also be switched to secure mode. There are three main subsystems in the STM32-MP1 microprocessor, the MPU subsystem, the AXI subsystem, and the MCU subsystem. The clock provided to the MPU can be changed dynamically via the switch MPU-SRC or by changing MPU-DIV. The clock provided to the AXI subsystem can also be changed dynamically via the switch AXIS-SRC or by changing AXI-DIV. In addition, the frequency of APB-4 and APB-5 can be changed dynamically. The clock provided to the MCU subsystem can also be changed dynamically via the switch MCU-SRC or by changing MCU-DIV. In addition, the frequency of APB-1, 2, and 3 can be changed dynamically. The MPU can be clocked up to 650 MHz. The MCU and the multi-layer AHB can be clocked up to 209 MHz. The AXI clock shall not exceed 266 MHz. Other limitations are shown in the figure. After power-on reset, a system reset, an application, or an exit from standby mode, the MPU, the AXI subsystem, and the MCU subsystem are clocked with the HSI clock. The clock for the RTC-AWU can be selected among LSE, LSI, or HSE clock divided. Note that when the divided HSE clock is used as kernel clock for the RTC-AWU, the frequency shall not exceed 4 MHz. The RTC-SRC switch can be modified only once after a reset of the backup domain or after an LSE failure. Note as well that if the LSI clock is used as kernel clock for the RTC-AWU, the RTC-AWU will no longer be clocked in VBAT mode. If the divided HSE clock is used as kernel clock for the RTC-AWU, the RTC-AWU will no longer be clocked in standby or VBAT mode. It can be clocked in stop mode if HSE-KERON is set to 1. The LSE clock remains enabled in all low power modes, including VBAT mode. The RCC also provides two clock output signals, MC01 and MC02. A pre-scaler allows the application to adapt the frequency to the pad's capability. This feature allows the circuit to distribute its internal clocks to external devices. The RCC offers the possibility to estimate the frequency of CSI and HSI clocks with respect to HSE clock with an accuracy better than 0.3%. Timers 12 and 15 receive the calibration clock signal for that purpose. The timers count the amount of timer clock periods within a period of the calibration clock signal. The capture registers of the timers keep the last completed calibration value. Interrupt services are also available. Many peripherals in the STM32MP1 microprocessor have different clocks for the data and control flows via the processor bus interface and for the peripheral specific interface. Generally, the clocks for the data and control flows via the processor bus interface are named bus clocks and the clocks for the peripheral specific interface are named kernel clocks. The peripheral clocks represent the clocks received by the peripheral, bus clocks and kernel clocks. Having a separate bus clock and kernel clock allows the application to change the interconnect and processor working frequency without affecting the peripheral. For some peripherals, it is also possible to disable the bus clock as long as the peripheral does not need to transfer data to the system. So it gives good flexibility on the frequency selection for the bus processor and memories and for the real need of the peripheral interface. For example, the UARTs have a kernel clock which is used, among other things, by the Baud rate generator for the serial interface communication and an APB clock for the register interface. In addition, some peripherals are able to request the kernel clock when they detected specific events. The distribution of the kernel clocks is not detailed in this presentation. Please refer to the reference manual for specific details. Most of the peripherals using a kernel clock have a dynamic clock switch to select the optimal clock source. The proposed clock sources generally come from one of the PLL outputs from internal or external oscillators. This is mandatory for peripherals requiring a kernel clock when the system is in stop mode. From pads, for example, on peripherals using an external PHY, but also for audio as well in order to use a clock reference from an external device or from other internal peripherals for synchronization between blocks. The dynamic switching eases the transition between one source and another. RCC registers allow the configuration of the kernel clocks for all peripherals. Peripherals generally receive one or several bus clocks, one or several kernel clocks. Each processor can control the clock gating of the peripheral clocks via dedicated registers located in the RCC. The gating of the peripheral clocks depends on several parameters, the clock-enabled bits. Each processor has a dedicated enable bit named M-P-P-E-R-X-E-N and M-C-P-E-R-X-E-N. The low power clock enable bits, and the processor states C-Run, C-Sleep or C-Stop. Setting the bit M-P-P-E-R-X-E-N to 1 indicates that the peripheral P-E-R-X is enabled for the M-P-U. This operation is named allocating a peripheral. The next slides give additional information on the clock gating conditions. It is important to notice that the RCC offers two register sets, allowing each processor to enable or allocate peripherals to their own use. The peripheral allocation in the RCC offers two registers sets, allowing each processor to enable or allocate peripherals to their own use. The peripheral allocation informs the RCC that the M-P-U or M-C-U enabled a peripheral. This information is used by the RCC for the clock control in low power modes. So, before using a peripheral, the processors have to allocate it to their own use. The same peripheral can be allocated by both processors. It is up to the application to avoid resource conflicts. Some peripherals are implicitly allocated to a processor. The CISRAM, DDRC, DDRPHYC, and IWDG1 are implicitly allocated to M-P-U. The M-C-U can also allocate the CISRAM, but by default it is not allocated to the M-P-U. If the CISRAM is allocated to the M-C-U, the CISRAM is still available when the M-P-U goes to C-Stop mode. Otherwise, the CISRAM is being clock-gated. Some other peripherals are allocated to both processors. This is the case for the RCC, PWR, SRAM1, 2, 3, and RETRAM. When a processor has been allocated a peripheral, this peripheral's status depends on the processor state for the low power modes. The processor plus the peripherals allocated by this processor and the associated interconnect are considered by the RCC as a processor domain. To give a simple example of the use of the peripheral allocation by the RCC, a rule can state that the RCC will not allow a domain to be clock-gated if one of the peripherals of this domain is used by the processor of the other domain, which is in C-Run or C-Sleep mode. The following table is a simplified view of the system states versus processor states. The system is in Run mode when one of the two processors is at least in C-Run or C-Sleep mode. The system is in Stop mode when both processors are in C-Stop mode and one of them does not allow the entry in Standby mode. The system is in Standby mode when both processors are in C-Stop mode and both of them allow the entry in Standby mode. In System Standby mode, the VDD core is switched off. For more details on system states, please refer to the PWR training slides. When it is requested to go to Stop mode, the RCC performs the following operations. The RCC waits that the DDRC enters into self-refresh. Then the RCC stops all clocks. More precisely, the PLLs are disabled and the oscillators are disabled except if they are requested to remain active. And finally, the RCC informs the PWR that all clocks are gated. Then the PWR block can either reduce the VDD core voltage or keep the current VDD core voltage according to the way it is configured. When the system is in Stop mode, most of the clocks are disabled except LSE and LSI can still be running if enabled. HSE, HSI or CSI oscillators can remain activated in Stop mode if they have their Karen bit set to 1. This feature allows a very fast reaction of peripherals in Stop mode and also a faster exit from Stop mode. And HSE, HSI and CSI oscillators can also be activated on peripheral requests. The system leaves Stop modes thanks to events generated by peripherals able to work in Stop mode. Before entering Stop mode, the application shall program the EXTI in order to define which event shall exit the system from Stop mode. When a peripheral generates the expected wake-up event, then the EXTI informs the PWR that a wake-up event requests the exit from Stop mode. Step 2 in the drawing. The PWR block restores the PMIC state if needed and waits for a valid VDD core. Step 3 Once the VDD core reaches its nominal voltage, the PWR informs the RCC that exit from Stop mode can be performed. Step 4 The RCC enables the HSI clock if it is not yet available and provides the clock HCLK4 for the EXTI and PWR. Step 5 The PWR and EXTI can then define if the wake-up event shall wake up the MCU or the MPU. Step 6 and 7 Finally, the RCC restores the clocks to the corresponding processor and generates the corresponding wake-up interrupt. Step 8 When the system exits from Stop mode, the RCC provides to the MPU and the EXTI subsystem the same clock setting as before going to Stop mode. This means that PLL1 and PLL2 are re-enabled automatically if they were used before going to Stop mode. The RCC provides the HSI clock to the MCU for fast restart. If the wake-up event was for the MPU, then the RCC generated a wake-up interrupt for the MPU. If the wake-up event was for the MCU, then the RCC generated a wake-up interrupt for the MCU. Note that a programmable delay named PWR-LP-TEMPO can be configured in order to delay the activation of the PLL1 and PLL2. The restart of the MCU can also be delayed or not by PWR-LP-TEMPO according to the MCT-MPSKP bit. This feature can be helpful to adapt the circuit according to the capabilities of the external power devices. Some peripherals such as the U-Arts and I2Cs are able to asynchronously detect events requesting a kernel clock for processing. The RCC can provide on-demand a kernel clock to those peripherals when the CPU allocating the peripheral is in C-Stop mode or if the system is in Stop mode. The kernel clock request only works if the selected kernel clock source is an oscillator, HSE, HSI, or CSI. In order to speed up the activation time when a peripheral requests a kernel clock, the HSE, HSI, or CSI oscillators can be maintained activated during the system stop mode. In system stop mode, if enabled, the LSI and LSE clocks are always available for peripherals. A kernel clock is provided to the peripherals if one of the following conditions is met. One, when the CPU to which the peripheral is allocated is in C-Run mode. Two, when the CPU to which the peripheral is allocated is in C-Sleep mode and if it's LP-Enabled bit is set to 1. Three, when the CPU to which the peripheral is allocated is in C-Stop mode and if it's LP-Enabled bit is set to 1 and the peripheral is generating a kernel clock request and the kernel clock source is HSE, HSI, CSI, LSE, or LSI. Or four, when the CPU to which the peripheral is allocated is in C stop mode, and if its LP-enabled bit is set to one, and the kernel clock source of the peripheral is LSE or LSI. The bus interface clock is provided to the peripherals only when conditions one or two are met. The RCC integrates specific modes in order to control the low power transitions of the DDR controller, or DDR-C, and DDR-PHY. The software self-refresh mode, or SSR. The automatic self-refresh mode, or ASR. Or the hardware self-refresh mode, or HSR. In software self-refresh mode, the application has to directly program the DDR-C in order to switch the external DDR device immediately into self-refresh mode. The RCC just performs the gating of the DDR-C and DDR-PHY-C clocks, as it is performed for other peripherals. The automatic self-refresh mode must be used if the application programmed the DDR-C in order to switch the DDR in self-refresh mode if the DDR-C did not receive any transaction for an amount of time configured by the application. In this mode, the DDR goes to self-refresh mode when it is not used for a defined amount of time. When the DDR-C receives a new transaction, the DDR-C requests the DDR to exit from self-refresh mode. The counterpart is some microseconds more to exit from the self-refresh mode. In this mode, the RCC has two levels of clock gating. The RCC dynamically controls the gating of the DDR-C clock according to the DDR-State and independently of the processor state. The RCC dynamically controls the gating of the DDR-C and DDR-PHY-C clocks according to the DDR-State and independently of the processor state. This mode can only be used when the DDLs of the DDR-PHY-C are bypassed. For example, it can be used for an LP DDR2 working in the range of 125 MHz. The hardware self-refresh mode is using the AXI low power interface in order to control the DDR-C and DDR-PHY-C clock gating. In hardware self-refresh mode, the DDR automatically goes into self-refresh mode when the interface is disabled via DDR-C XEN bits, when the MPU transitions from C-run to C-sleep mode, or when the MPU transitions from C-run to C-stop mode. The DDR automatically exits from self-refresh mode when the interface is enabled via DDR-C XEN bits, when the MPU exits from C-sleep or C-stop mode, or when the DDR-C requests to exit from self-refresh mode. This could happen if another master is accessing one of the AXI ports. This mode tends to set the DDR in self-refresh mode when the MPU is in low power mode, but other masters such as DMA can exit the DDR from self-refresh mode if needed. In this mode, the RCC also has two levels of clock gating. The RCC dynamically controls the gating of the DDR-C clock. The RCC dynamically controls the gating of DDR-C and DDR-PHYC clocks. This mode can only be used when the DLLs of the DDR-PHYC are bypassed. For example, it can be used for an LP DDR2 working in the range of 125 MHz. The RCC provides two interrupt interfaces, one for the MPU and one for the MCU. The MPU interrupt interface can be switched in secure mode via T-Zen bit if needed. For each processor, the RCC provides a general-purpose interrupt and a wake-up interrupt. There are mainly three kinds of event. Clock failure events, oscillators and PLLs ready events and wake-up events. In addition to this training, you may find the power control and interrupt controller trainings useful. Thanks a lot for your attention.