So, welcome to this lecture of digital system design with PLDs and FPGA. Last 8 lectures we had a look at the advanced digital design. We started with an overview of the field or revision of the field and I gave a brief overview of the current state of the art the basic what is happening in the field. Then we started with a synchronous sequential circuit, we have started with a synchronous counter its structure how to design a timing analysis. Then we got on to the design itself we have seen the hierarchical design of a CPU, we have seen what is data path, what is a controller, how to hierarchically design the data path and using CPU as an example we have seen the behavior of the controller of finite state machine. What is the structure of it, then we have seen timing analysis of it and how to design a control algorithm and finite state machine using state diagram. And we have wound up the whole process with a case study somewhat realistic real life case study of a data acquisition system, we started with the spec and went through all the way like the partition data path design, controller design, how to implement the you know the state diagram, the next state logic, output logic and all the way down. And what is the part of the kind of the designer main part and what are the tools plus designer and so on. But now we have some portion left in the advanced digital design but before proceeding I thought it is better we look at this hardware description language. So that when now onwards when we go with the digital design or anything PLDs or FPGA wherever it is appropriate we can put the connected VHDL or the hardware description language that is a basic idea that is why we go. So now for quite a few lectures we will have the VHDL lectures where my plan is to at least complete the combinational circuit description models and sequential circuit test pages and some demonstration using the tools available, free tools available you know how to write the code, how to synthesize, how to simulate and so on. So let us turn to the slide of this VHDL okay. So let us look at the slide now the VHDL the full form of the VHDL is VHSIC hardware description language that means the very high speed integrated circuit hardware description language. It has started in 1970s and 80s by department of defense USA for maybe I will give a brief on the conduct so that sometime the conducts make things clear you do not grumble or complain why certain things are like that and it is an IEEE standard IEEE 1076.3 there are various years you know 93, 97, 2012, 2002 and all that I do not exactly remember but then these are the various versions of the VHDL. Essentially it started with some kind of limitation of the earlier design methodology which was using something called schematic capture okay. So I do not know whether you are familiar with the schematic capture but I will show a slide which is taken from the internet of some kind of hardware, mainly digital hardware but then you see this is kind of some flip flops are there, some muxes are there, inverters are there and all that. A schematic would always involve some symbol of the IC you are using or the gate or the flip flop many a times in terms of the ICs you are using suppose this is a flip flop which is written IC3B so and there are pin numbers and it shows how it is interconnected okay that was the earlier days that was starting point of a design. You put like you want an inverter you put the inverter symbol which you mark which is a part of the IC maybe this there are 4 inverters in an IC so or 6 inverters then it will be IC1A1B1C1D1E like that the numbering goes and the pin numbers you can see that this is the output is 15 pin number 14 pin number and all that and people would put symbols and interconnect with the wires okay so that was basically the schematic capture and when one design a printer circuit board there will be an associated package with it okay if it is in the standard library the package will be part of the library if the user creates he has to create what is the package maybe old times it was many a times dual inline package so this was to be precisely created so that the PCB when one make PCB it is precise and the chip goes into the pin holes and the tracks are aligned and so on but basically essentially a schematic would tell how is the interconnection or the it is called a net list okay just shows a symbol and the interconnection between the IC and it does not give you what is the function of the circuit many a times you have to refer to the data sheet of each IC try to understand the internal in simple case gates and all it will be simple but if there is a processor one has to read the data sheet of all the complete processor to understand memory processor gauge flip flops everything need to be understood and sometime a design description need to be written saying that this is a particular IC this is a function of that IC and so on. So that was one big problem that it just does not convey anything other than kind of connectivity information that was the first problem with the schematic capture and the second problem was that there were lot of schematic capture or the CAD tools and everybody had many times a proprietary format that means the CAD tool if you are using a CAD tool from a vendor A the file stored in that format may not be openable you cannot you know edit using some other tool okay that was big problem a proprietary standards were followed and many a times this kind of tool did not support something called a black box design say go back to our hierarchical design of the CPU and initially at the level 0 we put a black box and said the clock and reset and read bar write bar were the inputs outputs and so on. Then we have partitioned it into a level one kind of partition still it was black box you know that is ALU registers program counters ultimately when we broke down into known pieces it has come to some kind of gates and flip flops or some known blocks. So this was one difficulty with the schematic a hierarchical design was not possible or top down approach was not possible in this thing. So this that if you had to design a finite state machine now when we describe the finite state machine we said you could kind of describe that in hardware description language and the tool will make the next side logic and output logic this was not possible with schematic capture you need to you know draw the state diagram you need to make the truth table minimize it and then implement those minimize equations using the gates and flip flops and so on. So this was kind of external you work externally and bring the design into the schematic capture. And they also supported some kind of simulation because there is a flip flop if the model of the flip flop was available then you could simulate the old circuit I mean model of all the chips used are available then using some kind of simulator the behavior of this could be kind of simulated. But again these were proprietary like the vendor I will give some models but that was not compatible with the other tools and so on there were not that it is completely proprietary there were standards for you know the CAD file exchanges you know the schematic exchanges and the simulation models and so on. But not everyone was following and there were problems issues with it and there was the huge problem was that these were binary files if there is one bit goes wrong everything is corrupted and there were such were the problems with the schematic capture. Now the department of defence had lot of vendors making big systems I mean they have huge rack of cards comprising a system maybe each subsystem was designed by a separate vendor and they all use different tools and to put it together and to understand to kind of coordinate the whole activity was a big problem that is why this particular standard came up and they thought of basically documenting the schematic you know that started with documenting so basically to describe in human readable language English language the description of the circuit that was a basic idea. So that it is portable like all the vendors use the same language to describe the circuit so that one can read and understand that was a basic idea. So it started with documentation you know document it well you know describe it unambiguously so that the human can understand and there is it was an open standard it is human readable it is portable and so on. Then later on people thought anyway we are describing the behaviour of subsystems or small circuits using some language why not use that description to simulate the behaviour of the circuit. Still the design was largely done on schematic capture but then the simulation came second ultimately when everybody started using simulation people started thinking why not generate the circuit itself from the description okay. So these are the three uses of the VHDL language documentation simulation synthesis which is I mean which happened at different points in time. So you will see all these features in the language okay. So there are documentation features you know when you look at the VHDL people will see that the entity is or architecture a name is of and all that and people often complain saying that what this if and off and why the computer algorithm need this human readable thing. But you know you should remember that this was meant for documentation and anyway you can use standard templates you can make your own templates or copy paste the old templates and so on. So do not complain that much about it is a little bit verbose language. So do not complain about that part of it and similarly there are when you come back there are you know the syntax for simulation there are some constructs in the language which is only used for simulation there is no point in using it for synthesis okay. So this should be kept in mind it is not that all like anything you write can be synthesized you know there are different there are some things meant for synthesis something meant for simulation some part of the language is merely meant for documentation. So do not complain too much and the language support hierarchical design you can do the top down design with a black box absolutely no issue you can do bottom up or whatever much to the convenience there are higher level constructs you know you can describe the behaviour not just Boolean equations but you can use higher level constructs like if then case when loops. So it kind of give a power to describe the language at many levels at a very detail level abstract level and as we go along we will see what is a how we can efficiently use this construct to describe and what are the best scenarios to use certain constructs and so on and it supports library based design that means that you can put suppose you have designed a counter a generic counter you can put that in a library and later on you do not have to redesign that. So anything which is modular generic can be put in the library similarly various operators various functions procedures everything can be put in the library so that that can be reused. So it is a great help you are in an organisation in a particular business and you are making designs over the years. So you can have a good library of the various modules subsystems components you are using and so that when a new design need to be made you can quickly make it using already well designed components interconnect them or modify them quickly and put it together. So that is a big advantage and one lacunae or you know or a feature of the VHDL is that it is strict type checking that means that data type is strict you know you suppose you declare something called bit ok bit is something takes one and zero and there is a another kind of data type called standard logic ok we will see that but that also support one and zero and many more things. But in VHDL suppose there is a signal which is of data type bit this cannot be assigned to the something of data type standard logic ok. This is looks like a restriction but it is a very good thing because if you do not know what you are doing because you are interconnecting various signals and if you are not careful like you declared something as an integer of some range and there is some kind of bus which is 8 bit and you try to connect this integer to that kind of bus 8 bit bus maybe that your range of integers is more than 8 bit and then there is a confusion like you end up with 12 bits and how to connect this 12 bits to 8 bits and if the tool decide that least significant bits will be connected then you are in trouble. So that is why the strict type checking is enforced it is a good thing because we are making hardware not to make mistake the VHDL enforces strict type checking and there are like is not that you cannot assign a bit to a standard logic you have to forcefully convert the data type then you are aware of it and then you will take caution that is why it is provided. So let us move on to the slide and let us look at the main design unit of the VHDL. So the VHDL design or any block has two parts when you describe it has two part any component as an entity which is nothing but the interface specification and the architecture which is functionality okay this and we will take an example of orbit comparator this part is taken basically from the reference book Kevin's Cahill at least this starting part is taken from there. So say you look at an equality comparator so you have A and B which are 4 bit and there is a single bit signal called equal when the numerical value of A is exactly equal to B that means if it is say 1010 and B is 1010 this will be 1 that is the meaning of it. So entity means a name for the block some name what are its input port okay so you say input port is A and B which is 4 bit and what is the data type is it bit or standard logic vector and so on okay. So and similarly what is the output how many bits are there is it a single bit or multi bit and what is the data type so that comprises the entity. So give a name for the block what are the inputs what are the outputs. So you have to clearly say what is the name whether it is input output and so on and what is the data type. Now comes architecture having define the entity you define what is inside the architecture is nothing but functionality. So you have to define what is the function of the circuit in terms of the input and output that means you somehow you say that equals will be 1 if A is equal to B you know in some there are many ways of describing it. And that is the functionality so you describe the functionality of this block equality comparator in terms of the input and output okay. So you say output how the output is assigned from the input that is the basic crux of the VHDL entity and architecture entity means the name input output the basic the data types and the architecture means function in terms of the input output. And you know the circuit you know when you come to the basic implementation we need to have each bit you know suppose if you have a A3, A2, A1, A0, B3, B2, B1, B0 you can see that for these number to be equal A3 should be equal to B3, A2 should be equal to B2 and so on. So we use an exclusive NOR gate because exclusive OR gate has 0, 1 and 1, 0 as 1. But here you have 0, 0 and 1, 1 as 1 so unless all these are equal these won't be 1 and if all these bits are 1 then we have this AND gate is making it 1. So you know the circuit for exclusive OR gate and sorry exclusive NOR gate and 1 AND gate is a function. So that is the VHDL way of describe main kind of component kind of sub description entity and architecture. So let us look at this equality combinator VHDL codes straight away and try to kind of see how to write a VHDL code and what are the basic components and so on. So say when you like I have written here 2 dashes and 4 bit equality combinator that means this is a command ok if you start a dash anywhere you could you know I could put 2 dash here and write something. So anything after the dash is a command and you know that there is no way to kind of make it you know nest multiple lines not a big problem earlier when people used to use the keyboard that was a big problem. Now suppose you have 10 lines to command it if you have to put everywhere it is a big problem nowadays with GUI it is very easy you select everything and click an icon then everything become commanded. So this is a command character only for a line it does you cannot nest it ok. The next thing is interesting it say ok now the I have shown the code in 2 colors basically in green and the blue and whatever is written in the green color is a VHDL keyword and rusts is what we are writing ok so that is to make out. So like library is a keyword of the VHDL use is a keyword of the VHDL and so on ok so here we are saying we are going to use library IEEE that there are IEEE standard libraries. So we are saying that we are going to for this entity and architecture we are going to use library IEEE so when you declare that this IEEE libraries are visible only to this entity and this architecture. Because in the same file you write another entity and architecture you have to and you need to use a library then you have to write again library before the entity and architecture. And just writing the library it makes a library visible to the code but not the packages library has lot of packages within it. So it is a hierarchy of library so you have library you have packages and within the packages you have components, functions, procedure, data type and so on ok. So that is a hierarchy and we are going to say that we are going to use a particular package within this library called standard logic, standard underscore logic underscore 1164.all ok. So we are going to use this particular package for this entity and architecture that is the meaning of this and now onwards we are going to use the standard logic library. The reason is that if you look at the VHDL inbuilt data type is bit ok as far as the logic is concerned and it supports only two values you know 0 and 1 and this is a great limitation and for digital design we just cannot do with only 0 and 1 we need many other things at least you know that we have tri-state gate which we use and we want to use at least and z describe saying that some output need to be tri-stated. So that and that is described in a standard underscore logic and that is a kind of data type which is used which is available in this particular library and package. So that is why we use this. So it supports you know the data types like 0, 1 values like 0, 1, z and you know there is many times in minimization we use don't care to support don't care and all that many more we will see what are the values in this standard logic data type. But for the time being understand that it will at least support a z which is represent the tri-state which is very much required for the design. So now onwards all the code we will not get into bit we will use the data type standard logic that is what it shows now this comes the entity description. So the key word is entity give some name it does not matter and this is what I said is is a kind of for documentation and you say end this particular name eqcomp ok. So that is a body of the entity so you start with the keyword entity a name is and end that name then that is kind of that is the body of the entity and within that we have to describe the inputs and outputs and the keyword used for that is port you open the port with the parenthesis left and right and semicolon you can see that all the kind of syntax is terminated by semicolon. So if you describe something a complete entity then you put a semicolon complete port then you put a semicolon everything every statement every kind of the body is terminated by a semicolon. Now you see this is the input specification and this is the output specification. So we have two types of inputs two inputs a,b so if it is of the same size same data type which use it in the same line say here a,b then you put a colon this is the name. Now we say what is the direction of the port it is an in means it is an input and standard underscore logic underscore vector 3 down to 0 that means that a is a 4 bit vector which is a of 3 a bracket you know 3 like we have seen here a of 3, a of 2, a of 1, a of 0. Similarly b of 3, b of 2, b of 1, b of 0 ok that is the meaning of it the moment you say standard logic vector 3 down to 0 that means it is a of 3, a of 2, a of 1, a of 0 there is another syntax you can say instead of 3 down to 0 you can say 0, 2, 3 it is possible to write like that and there is a difference we will soon say what is the difference and let us come to this equals which is a name and the mode of the or the direction is out and the data type is standard logic ok. So when you describe a port you have to give a name you have to tell the direction you have to tell the data type and now when you say there has to be clarity with this kind of direction of the port. So when you say in it means that it is an input ok it cannot be treated as an output that means that when you write some assignment like here we are writing the assignment equals get 1 when a equal to b. So a and b are the inputs in any assignment the input can come only at the right hand side of the assignment ok that should be kept in mind when you have something declared as a direction in it can come only on the right hand side of the assignment and there is similarly there is out and out means it is an output port something drives you know there is some kind of gate of flip flop its output is driving a signal which is outside and when you declare something is out like equals that can that should come on the left hand side only. You cannot write you know something like z gets 1 when equals equal to something now you cannot write on the right hand side ok but that could be a restriction and you look at this kind of thing like we have some many times an output a tap is taken from the output and used as an input to some circuit inside this is quite common you know you have something coming like some gate is driving an output but that output is going to the output pin also it is used as an input to the further circuit you know within this block ok but by definition if you use out such a thing cannot happen with the VHDL. So there is a roundabout there is a kind of way out that is declare this output as buffer like you say equals buffer you know standard logic but this as a problem because as a stand alone it is ok but when you have multiple components buffer it cannot be connected together you know there is an issue with the buffer. So I do not think that you should or we will not be using this particular direction of the output signal at all and what we are going to do is that there are internal signal you know you can use signal. So what we are going to do is that we will normally in our codes we will declare a signal here which can you know which can definitely connect to the some output and can connect to some input and ultimately this signal we can assign it to some pin you know that is what we are going to do in our code. So literally forget about this particular direction of the port buffer and now there is one other direction specification which is nothing but in out or an IEO. So now that is not a same as buffer in the case of buffer it is still an output the pin is an output but there is a tapping which is used internally ok. But when you say something is in out it literally means sometime there is a definitely a tri-state gate and when the enable is one this circuit will drive the circuit which is outside ok. And when it is cut off when it is not disabled this part is inactive there is nothing you know it is tri-stated and this can be used as an input pin that means literally something can drive the pin ok. So there is a difference between this structure and this and you should not use in out for out or buffer ok and I have seen sometime people you know use out and something goes wrong and they somehow find that if you write in out that can be circumvented because of some kind of simulator difficulties maybe at the appropriate time I will tell people tend to use in out where in out is not meant to be used ok. So that should not happen you should not use in out in place of buffer that in out is used only when a pin is used as both as output and input and necessarily there has to be a tri-state gate without which there is no way to use an IEO pin. Now that is the kind of various direction in out buffer and in out and as I said forget about buffer we will use the wires I will show at the appropriate time and standard logic vector is a repetition of the standard logic like you know this is a 4 bit standard logic is a standard logic vector and as I said you could write 3 down to 0 or 0 to 3 ok. There is a difference when you write 3 down to 0 the most significant bit is 3 and least significant bit is 0. When you write 0 to 3 the most significant bit is the 0 that means whichever comes on the left hand side and the least significant bit is the 3 which is on the right hand side. So the rule is simple whatever you write on the left hand side is the most significant bit and whatever you write on the right hand side is the least significant bit. Now you might ask what is the big deal you know what does it matter ok. It matters if you have studied a kind of the processors from the indel actually this has some history you know behind the indel processors used to treat suppose you have a data bus which is going from 16 like 16 bit data bus the D15 was treated say the data 15 was treated as the most significant bit and D0 was treated as the least significant bit and this was called little engine. That means the small number will end the end the you know is it at the end part and then the motor law which was a kind of a competitor to indel when they came out with this processor subsequently that has become free scale but when they came out the numbering was kind of opposite the say D15 was LSB and D0 was MSB ok. Now you can imagine so this is something to do with this 3 down to 0 or 0 to 3 has something to do with the kind of the bit order and the byte order and so on. So if you are using little engine then you should use terminology like 15 down to 0 if you are using big engine then you should use 0 to 3. So you may even end up with you are designing a chip on one side you are connecting to some other chip from another vendor which has a bus in little engine order and the second side has a bus which is in the big engine order. Then you should appropriately kind of define this properly otherwise things can go wrong.  So that is all about the entity so we have looked in detail what is the entity what is the port what are the directions little engine big engine in the case of multi bit and so on. Now comes the functionality which is defined as architecture so you say architecture which is a keyword give some name arc underscore eqcom that is my style of doing it of this particular entity say whatever the entity name is written here. So this is the kind of link between the entity and architecture you say architecture and name of which name you have to say is okay. Now you say begin that is where you describe the functionality okay. So before that before the begin you could declare many things you know you could declare components you can define functions procedure and so on okay. So we will see what could be done before that and when you write say the statement we will see what are the statements and so on. Say this is an output signal and this is an assignment operator which is similar to which is exactly similar to less than or equal to the VHDL also use same for the less than or equal to. So depending on the context I know the meaning of that is derived so one you know one is written with the quotes left quote and right quote because in the library in the standard logic library the values are defined with the quotes like one with the left quote and right quote when A equal to B else it is 0 okay. So equals get one when A equal to B else it gets 0 okay very simple the description is over and you say end this architecture whatever is the name so that architecture is over. So that is the code in a nutshell you have a comment you have a library you have a used package kind of construct you have an entity with port mainly within the entity is a port direction the data type the multi bit declaration then the architecture before the begin there is a declaration in the statement region you write various statement then the description is over okay. So that is in a nutshell a kind of the basic VHDL code. So and you can use various keywords various names and let us move on to the slide summarise whatever I have said. So I have said commence start with anywhere on the line and library as a hierarchy library packages and it contains components functions procedures various data objects data types and things like that then you have different mode or direction you have in out in out and buffer we said this has very limited usage and in out and out is different or buffer is different then we have down to and to so you have to worry about little engine big engine bit order byte order and things like that. And when you define some name you can use alphabets you can use numbers you can use underscore and it is not case sensitive first character should be an alphabet the last character should not be underscore and you should not have two underscore in succession and I do not remember the exact number of characters you can use for the maybe 32 characters you can use you can check with the standard because the standards keep changing. But for practical purposes your normal names you can give quite a long names there should not be problem but better to check with your with the VHDL later standard and tool compatibility what the tool support maybe you refer to the VHDL later standard but the tool support the earlier standard then you will be in trouble then you should be careful with that. So that is in summary about the code so let us move on the architecture body so we have said that in an architecture before the begin you can declare many things you know there is lot of things you can declare that is what is shown here the architecture has two parts before the begin you can declare something after the begin you can write the statements you can describe the function. So what all you can declare is that you can declare components components are you know like equality comparator gates or flip flops or multiplexers encoders all that is the components the type data type like standard logic bit Boolean and things like that and constant like you have a bus width you can decide you know define as a constant like size of width signal we have described like you want to interconnect kind of two ports or output of some block with an input of another block then you can use signals. You can also use functions and procedures for the time being we will keep it aside but then you can literally define functions and procedure not declare you can literally define in the architecture declaration region which is visible only to the architecture statement region okay. So after architecture statement region is where you put all the description in terms of various constructs. So let us turn to the logical operators. So you have all the logical operators you have AND, NAND or NOR, XOR, XNOR and NOT. But the trouble with the VHDL is that the basic operators within VHDL support only the bit and Boolean okay. But as we described in the first slide we are not going to use the bit because it is restricted by 1 and 0. We are going to use the data type called standard std underscore logic we call it standard logic. So std underscore logic is called standard logic and this is but you do not have to worry about the logical operators for this data type because in this particular package IEEE standard logic 1164 package which we have used in our code the first example code this logical operators are overloaded. Overloaded means whatever was written for the bit is rewritten for the standard logic data type. So the moment you declare you know like here the moment you declare use IEEE dot standard underscore logic underscore 1164 dot all means we could use all that AND and NAND all that here in the statement region and the all means everything in it like that means the entity and architecture following this use construct can use whatever there is within this particular package that is the meaning of all. So that is the logical operators then you have arithmetic operators you have the plus you can add minus multiplication integer division exponentiation because many times we work with the power of 2 then you suppose you have a data bus which is 8 bit then you know that it can go take values from 0 to 2 raise to 8 minus 1 ok. So where these kind of exponentiation operators are useful then you have a modulo division kind of modulo reminder then the absolute value there is a little confusion with this terminology like mode is different from the computer science mode the mode definition is say A mode B is A minus B into N like suppose you say 13 put 3 that means you know that it is 13 minus 3 into 4 so which is tall the highest number you can put before it crosses over then you get 1 ok. So if you know that when you do a mod N the result has to be 0 to N minus 1 but there is an issue with this kind of expression because it does not work well with the negative values because you know that the mod N has to map any number to 0 to N minus 1. So that is why this RUM operator is given which is actually this is equivalent to the computer science definition of the mode A RUM B is nothing but A minus the floor of A by B into B ok. For positive numbers it makes no difference because if you say again 13 mod 3 it is 13 minus 13 by 3 integer division is sorry the kind of the real division will yield you 13 by 3 will give you some you know 4 point something which is the floor of that is the decimal part is thrown off the fraction part is thrown off. So you will get 3 and 3 into 4 is 12 and 13 minus 12 is 1 you know you get it correctly but if you say minus 13 then you will end up with there is a confusion but with this formula but with this formula there is no issue because minus 13 by 3 you will get minus 3 point something the floor of it is the lesser number so which is minus 4 into 3 is minus 16 and you have minus 3 minus minus 16 you get plus 3 ok. You do not get a 1 but because your sorry it is 13 like minus 13 by 4 is 3.4 4 into 3 12 so this is minus 12 so minus minus 12 plus 12 and you will get you will end up with a positive number that is the crux of it. You can work out with an appropriate example but very important thing to note is that all these operators are defined internally for the data type integer and real integer is the integer as you know the real is the real numbers or the kind of floating point data type. These internal operators cannot be will not work for the standard logic data type but if you use standard logic unsigned package in the use case like you say library IEEE and you say use IEEE dot standard logic unsigned dot all then you can use plus minus multiplication division and all that mind you if you write a code with this with the standard logic it might work for simulation it may not synthesize and generate a proper circuit for you have to keep that in mind everything does not work sometime you have to write your own low level design for some of these to work or it will give some rudimentary circuit which is not that we want and things like that. So you have to keep that in mind and let us come to the relational operators. So relational operators are equal to greater than less than or equal to greater than or equal to and not equal to okay these are the relational operators you say when a equal to b or if a less than b and so on and you see that less than or equal to operator is same as the assignment operator. So depending on the kind of context you use the tools will infer what is the kind of operator appropriate operator and will find it you do not have to worry. Once again internally these are defined for integer and real for standard logic data type this is overloaded these operators are overloaded for standard logic function in the package called IEEE.standard logic arith okay. So in principle like if you use three packages like IEEE standard logic 1164 IEEE standard logic unsigned and IEEE standard logic arith you can do many things with the standard operators at least you can work with the standard logic data type. So keep that in mind and when it comes to shift operators you have logical shift arithmetic shift and rotate. So you have shift left logical SLL so that is just symbol left shift shift right logic is symbol right shift and shift left arithmetic and shift right arithmetic works with the tools complement numbers. So in tools complement number you know that the most significant bit represent the MSP or the most significant bit and that is the sign bit. So for negative numbers it will be 1 and when you extend suppose you have an 8 bit number with the sign bit as 1 when you convert this into 16 bit then all the numbers starting from the 9th sorry number 8 bit to 15 bit has to be 1. So when you do a shift left arithmetic this sign extension will be automatically taken care that is the meaning of left shift left arithmetic and shift right arithmetic. So if you do some arithmetic using the shift operators like you know that shifting left is like multiplying by 2 shifting right is like dividing by 2 and if you are working with unsigned integer then the shift SLL, SRL like logical shift works but if you use arithmetic like if you use kind of signed integers then you have to essentially do the shift left arithmetic and shift right arithmetic to preserve the sign otherwise things will go wrong and you can work out you know you take a 4 bit number work out the negative numbers you work out you know if you extend it in up to 8 bit make sure that you get the same value with the sign extension that should convince you and that gives you little clear understanding of the 2 scombie numbers you can you know work with even the decimal numbers and how this old game works you can you must have studied but then that brings clarity. And once again the shift left arithmetic and shift left logical and arithmetic all these are defined for the bit and the Boolean data type for the standard logic data type this is overloaded in the standard logic Arith package. So that is what I said you use these 3 packages most things will work you know standard logic 1164 unsigned and Arith and you have an operator called aggregate operator essentially it is shown here suppose you have a signal like standard logic signal with ABC these are single bit signal ok now I am using bit do not confuse bit I mean the real bit of the digital system not the bit data type of the VHDL ok. So here we are trying to make it combine ABC into a 3 bit kind of bus so you have a signal there is a keyword this is a name which is of type standard logic vector 2 down to 0 that means there is temp2, temp1, temp0 now we say temp is nothing but assigned in the brackets you say a,b,c that means temp2 is a, temp1 is b, temp0 is c. So this is called aggregate operator so you can aggregate individual signals which can be single bit, multi bit to a bus but the restriction is that these elements individual elements should be of the same data type and should be same size it is not that a can be 3 bit, b can be 2 bit and this is single bit it has to be either single bit, 2 bit, 3 bit together but even better flexible operator is a kind of concatenation operator which will work for the same data type for different size say you can see here we are declaring a data type new data type which is a keyword is type byte is array, array is a keyword it is an array of single bits that is the meaning of it 7 down to 0 of bit ok bit is the byte is nothing but an array of 8 bit array of bit is the meaning of it and we say signal count is a byte and we say now the byte is an 8 bit kind of signal which account gets 0,1,0 and 0,0,1,0. So this is a 3 bit kind of signal and this is a 5 bit signal which is combined it. So this and is much more flexible concatenation operator the type has to be same but you can join things together very useful in digital design you have some kind of some parts of the bus come from different places which is combined together to make a bigger bus and things like that. So that is very useful these operators and there is a precedence of the operators. So you have the highest precedence is 6 as you go down 6,5,4,3,2,1,1 as the lowest precedence. So you have miscellaneous operators are highest precedence and multiplying addition shift relational and logical operators and not operator as precedence 6. And when you write the same precedence operator from left to right it is evaluated left to right. But it is very difficult to remember all these I suggest you remember the kind of use the brackets possible it is good for you know understanding when if you write you write the code somebody read it is very easy to understand. So maybe we will stop here today's lecture so we started with the VHDL how did it kind of evolve what was the basic context the department of defense has trouble with the schematic. So it started with documenting then use for simulation synthesis it is human readable it works with the computer language support hierarchy, support to higher level construct, library based design and so on it is an open I2P standard. So whichever tool does not matter you know the different tool vendors everybody uses the same language. And we have seen basically an entity and architecture entity is interface architecture is a function. Then we have seen an example code we have looked at the entity pod the direction the mode the data types bit order byte order then architecture declaration region statement region a statement and various operators we have seen the logical operators. And the particular data type called standard logic and which are the libraries which is used for the standard logic then we have looked at the arithmetic operators we have made found what is the difference between mode and RAM then you have we have looked at the relational operators as two special operators called aggregate and concatenation operator. So now in the next class we will see little bit how to what is the design tool flow you know various kind of different models of description and so on ok. So I suggest you look simple to start with so please go back brush up understand it thorough you can refer to some good books to get a grip on this particular VHDL there are lot of good books as I said earlier maybe you use some book with synthesis as the emphasis. So that is it I wind up this lecture I wish you all the best and thank you.


When I go to watch a film, I sometimes wonder if this is the result of a collaborative creation or the sensibility of a single author. And if this is true, is this the director, the producer or an actor? What do you think, Sasha? Well, I think lots of things. This is why we compose this course about creativity and authorship on examples from Spanish cinematography. So we are going to talk about many theories that were born during the development of cinema that aboard this problem of who is creative, why is this person creative, how to divide creativity, how to organize a creative effort on the set. Okay, so students will be able to learn about that, but also they will be able to learn about Spanish cinematography from silent cinema until today. Simple attention will be placed, of course, since this is cinema on the notion of the author. You know how the director is always the author, so he is a creative subject. So we are going to explain why, how and which theories are against the author's theory. Also we will explain some things about politics, relationship between creativity and politics on examples from Franco, dictatorship and Spanish transition. And Paul also will say something about some more interesting topics. I'm sure they are, and this is because we will have some seminars to approach the concepts of authorship, originality and creativity in cinema and in the arts.


Hey everyone, welcome back for more XOZeroes content, today's video we're going to discuss the top PvP teams and heroes as of February 21 2021. But before that, if you want updated XOZeroes content, please hit the subscribe button down below. Hey guys, so we're going to start with the top tier heroes in PvP. So what happened last February 2021. So this is actually the rankings in terms of the top 10. So if you can see here, the number has actually come around and actually dominated the what they call the top five at least. And once when you once when you have seen this week's top heroes in PvP as of February 21. So take note guys, this is just for the Asian server for for the top 50 teams. So basically right now, you can see there hasn't been a change that much in the top four or top three. So basically again, this just says that the best dominated PvP, especially with the with the addition of FCZ on and also Tantaloh has climbed as well in the top five. So for top one, you have their Iris of 50%. Take note that Iris's usage rate has dropped. So it used to be higher than 50%. So she's now at 50%. And a close second and third would be April and Rachel with 48%. So teams have been have begun to do away with Iris in terms of PvP and replaced her more with more firepower as well. So for your fourth, you have FCZ on with 32%. So he gains a plus plus three in the standings for your fifth, you have their Tantaloh at 30%. So he also gains a plus three, both wasted red Garf and FC Redley went down. So Garf went down a spot at 28% usage for number six. FC Redley also went down at 26%. He went down by one spot now at seventh. Bathory also took took a hit with a minus four. She lands now at number eight. And if you notice Herrera is actually not again in the top 10. So she's been absent as well. So for your nine, 10, 11, I could not leave one out because the three of them have the same percentage of 24%. But Annie actually gained one spot from number 10 before to ninth right now at 24%. Shell and Genai actually is actually climbing up the what they call this climbing up the top 10 because they're at 10 and 11. Sorry, it's a top 11 now because both of them are at 24% usage as of February 21. Okay, so this picture says it all. So the dominance of the number four now is actually visible here. And the other teams are just catching up. So FC Iris's dominance actually as the top hero is actually slipping down because teams are realizing that they can actually do without FC Iris in PVP. Okay, so let's move to these are the top tier teams in PVP. This is as of February 7 again 2021. So basically, these were the teams that are top. But if you can see in our next next screen that the difference is FC Iris Dorca and FC Shufraken Valentina, FC Bathory team actually was around they ranked fifth before. Okay, in the previous month, they were fifth with in terms of usage. Now they are first with six teams using them. So take note that this team actually although they don't have that much top heroes, they are solid and they have been used that much. So Linombe is a story with Linombe all over the place with different mix and matches with other teams. But if you base it on team only, you have here the top team which is North One Frosty with a splash of Bathory and Dorca. Dorca is here as well. So for your second top team, which is FC Iris, FC April, Rachel, Baraka, and Xeon, they were fourth last month. Now they're in number two with five usage. And in terms of the third, so you have Iris, FC Rachel, FC April, FC Boris, FC Xeon. So the only hero here that was swapped out from Baraka to Morris. So this team, this one, the third one actually with four usage was top last month. So it topped the standings in terms of top teams in PVP. Again, these teams or these rankings based on the Asian server, the top 50 teams as of February 21. So if you want to see the other eight teams that I mentioned here, especially here at three usage and at two usage, I will post them down in the comments section below for you to look at. So let's proceed to just a summary of my final thoughts for this top tier teams and heroes. So basically, the usage of Talia also drops. I forgot to mention that earlier. You didn't see Talia in the top 10 heroes. So basically, players have, you know, have learned on how to deal with Talia already with FC Ramji. And you know, try to try to time on how to kill Talia has been actually, I think, very key in her dropping in usage. But I think it's more or less on the usage as well for Ramji. So out of the top 10 heroes, out of the top 10 heroes as well is who was that one. Dorca is out of the top 10, but her team actually shines with North One Frosty. So number two is Lanombe is king right now. So there are a lot of, there have been a lot of team comps that use Lanombe, not necessarily the full Lanombe team, but usually some of the teams would splash in April and FC Rachel together with their other team comps. So top teams are usually going for mostly for Lanombe build or Lanombe heroes. Okay. So North One Frosty again remains solid. So it's proof that last week's rise in North One Frosty usage was not a fluke because I also thought it was a fluke, but fortunately it's not. They're here to stay and they have really proved their worth since they started dominating PvP back when the day was still starting. Okay. So it remains solid, limited team composition. So basically the only team comp that you see with North One Frosty is the standard Shufraken, Valentina, Iris, Bathory and Dorca. So basically that's it. Also again, if you note that the usage of F.E. Iris has dropped because they have learned that they can survive without FC Iris even though there are first gargants in other lineups. And also this number five is frequent add-ons. I've noticed that there are two pairs of heroes that have been splashed onto other teams. Notably you have Talia, I'm sorry. Notably you have Shell and Jani being splashed onto Wasted Red, which is Garf, Ruddy and Annie. So that is actually one of the teams that you should watch out. And the other one for Linombe, FC April and FC Rachel has been splashed to Team Greenland, which includes Tantalor, Rera and Bathory as well. So take note that these teams actually, if you want to build these teams as a splash to your current team, they're actually good. They can be very useful even only as a pair. So more or less that is it for the top PvP teams and heroes as of February 21. So basically guys, if you have any comments write them down below. Please subscribe to my channel. This helps my channel a lot. Anyway guys, you always take care. This is The Warden and I'm out.