Greetings, RISC-5 friends. If you looked at the live streams that I recorded over the past week, you'll see that I did some conversion of the abstract logic in the sequencer to actual chips, not physically but essentially simulated chips, and I ran it through formal verification, and it worked just fine. So this is very good because it means that I can essentially translate the logic of the sequencer into actual chips and be pretty sure that things are going to work out okay. So one of the things that I did, and this wasn't in the live stream, but this was actually after the live stream, is if you look at this section here, so this is the equivalent of this. So this is the abstract logic here, and this is basically selecting what goes next into the program counter. So you can see that in general there's an if and then a load statement, right, an else if and a load statement, and so on and so forth. So in converting this to a chip, two chips, I wrote this simple function called multiplex to reg, and the idea behind multiplex to reg, and I'll draw this out in the moment, is that there are these selectors, and these are the same selectors as above from here. There are these selectors, and there are also these signals, and the idea is that when one of the selectors is active, then that signal is loaded into the register. That's basically it, and if none of these selectors are active, then the register retains its previous value. Now I explained during the live stream that there are two ways that you can do this. One way is to simply route the output of the register back into one of the inputs of the multiplexer, and just say, well that is one of the selection possibilities, and the advantage of that is that then you get to clock the register on every single clock cycle without having to pass the clock signal through any logic. So the idea would be that actually let's just go to the drawing and take a look at it. Okay, so here we are in the drawing pad, and what I'll do is I will show a register here. Let's select a marker, and here is a register, and it's going to be a 32-bit register, right? And it's got an output, and it's got an input, and it's got a clock. So one of the ways that you can do this is you can stick a multiplexer in front of the register, and let's suppose there are four possible inputs, and there are four selectors. And the idea is that if none of those selectors are selected, well then you just sort of gate the register's clock. So here's the clock input, and here's the actual select. So the idea is that you gate the register's clock with the selection signals, so that you don't clock it when none of the selectors are active. So there's a little bit of a problem with this.  Well, the idea is that we want to make sure that that positive edge doesn't make it to the register when there is nothing being selected. So let's suppose we have a signal which goes high when any one of the selectors is active. So we would want to do something like this. So when you and these together, you get something like that, and there's the edge. Now, that's going to work fine except when your clock looks something like this. When it's high all the time except there's sort of a low pulse, and you're going to be clocking on the positive edge. So in this particular case, here's your gating signal. So you need to be sure that your gating signal changes its value during that pulse because if it doesn't, if it changes its value before that pulse like right over here, like let's suppose your gating value looks like that, then the problem is that when you and these two together, you end up with a gating signal that looks like this, which actually has two positive edges, which is not really great. And the reason that this might happen is that this gating signal may actually be generated from another clock. So for example, you know, maybe you have two clock phases, here's one clock phase, and here's the other clock phase. And this clock phase generates the gating signal, which is going to be used for this clock phase. So that's not really great. So the alternative. So let's call that the unsafe version, because you really have to think to make sure that you know when your selection signals are going to be changed relative to the clock that you want to clock the register on. So the safe way is to simply take your register, there's your clock, there's your output, there's your input, and there is your multiplexer. And then instead of four inputs, for example, you have five inputs, and that input comes straight from the register's output. And then you have a clock, which now is unencumbered by logic, it's just the straight clock, because now you're clocking it on every single cycle. And your selection is going to be, well, one of these four, and if it's none of those four, then it's going to be this top one. And that's really all there is to it.  Let's suppose this is your selector, and you know, one of it goes high, well, it's still not going to get clocked until the positive edge of the clock signal. So you don't have to worry about when your select signals go high or go active relative to your clock pulse. So that's why I kind of like the safe version. And yes, it does involve increasing your multiplexer size by one. But I think overall, it's, you know, it's safer, it's less prone to error. So let's just use that. So that's what in the code, that's what multiplex to chips multiplex to reg actually does. So if none of these are high. So let's see how many selectors we have one, two, three, four, five. So this actually sets up a six input multiplexer. And it automatically routes the output of this register here. Am I showing the right thing? Yeah, it automatically outputs this register here to one of the inputs of the multiplexers. The register is always clocked on this clock. So in this case, it's phase one. There's the program counter. And there are the five possible inputs right over here. Plus, of course, the register itself, that makes six. So what I wanted to do today is see how viable that is to actually convert to hardware. So I'm going to be using Kycat, I'm going to be slapping down some chips and, you know, routing some things together and, you know, see if I can, I can make this this program counter register. Now, here's one of the ideas that I had for this program counter register. So let's oppose that on the main sequencer board. We have a 32 bit bus for the PC. We know that these are all the other inputs that can go to the program counter. So there's the program counter plus four, the X bus, the Z bus, the mem address and the mem data. And all those are 32 bit buses. And then we have the controls. And basically, the controls are going to select one of these six inputs, or, you know, one of these five inputs. And if none of them are selected, then it's going to select the sixth input, whatever, we'll figure out that logic later. So this is going to have at least five lines, if not six, probably five. So the idea that I wanted to try out is looking out at the side view, let's suppose this is the printed circuit board for the sequencer, there would be a bunch of headers over here. And that's what these things represent. These are all headers. Let me put another header over here. And each of these headers is connected to these 32 bit buses. And this header over here is for the selectors. So from a side profile looks kind of like that. And then you would stick the program counter board on top of it. And that would be that, you know, maybe a long thin board. I don't know. It's a thought. And I just want to explore it. So then the question is, well, what do these connectors look like? Well, obviously, I need 32 signals. Plus I need some grounds, because of course, you want a signal to go next to ground so that the impedance between the signal and its return path is low enough. And you know, I could use your standard 0.1 inch headers here. Yes, that means that ground and signal will be separated by 0.1 inches. But yeah, okay. There's also the possibility of using those PCIe slots. But the problem with the PCIe slots is that they're card edge connectors. So, you know, in that case, if this were the PCIe slot, then my card would have to go up like that, which doesn't make sense because it has to sort of span a whole bunch of connectors. The other possibility is that I can instead of laying these out along, say, the x-axis, I can, you know, maybe do them along the y-axis like this and then have the card span this. But then the problem is that my PC is going to have to run like this, PC plus four, x, z, and so on. And then I'm going to have to have more card edge connectors like that. That's another possibility. The problem is that I don't like the fact that these PCIe connectors are now sort of perpendicular to the signal path because now the distance between these buses is pretty large, you know, as opposed to maybe something like this, where the connector is actually parallel to the bus. So, I can stuff them a lot closer so that the bus to bus distance is a lot lower. So, I'm going to try this and see what happens. Okay, now, I am actually using, if you can see down here, I'm actually using one of the latest nightlies of KiCad. And the reason I'm doing that instead of the production version is that this has kind of a few nice features, which I kind of want to explore. You can see that the user interface looks slightly different.  And I have already one built. So let's create one here. Okay, so here we can see the sheet properties. So I'm just going to call this, let's see. So we know that we're going to need to feed the PC. Let's start with the register. Okay, so RegPC. And I have already created a schematic for that. That's called Reg32. All right, so let's zoom in a bit. So there is our RegPC. If we go in, we can see that this is formed out of two 16 bit registers. These are 16374s. I chose the FCT logic family, just, you know, because I needed to select something. Actually, there is a particular reason, and I'm not sure it's still valid. But when you have two buffers, and you connect their outputs, the question is, if you disable one buffer and enable the other buffer, what is the disable time versus the enable time? Because if the disable is slower than the enable, then you're going to end up with two buffers enabled at the same time. And then their outputs are going to fight, and you're going to have a problem. But if you disable faster than you're enable, then both buffers will be disabled, and then one buffer will come up and be enabled. So, and I looked at the FCT datasheet, and it seemed to imply that the disable time was always faster than the enable time. The disadvantage is that FCT is a five volt logic series. It's not 3.3 volts. So when I looked at something like the LVT series, it wasn't so clear because at some voltages it was faster, and at some voltages it was slower. So I don't know what I'm going to do about that. But let's just stick with the FCT parts. So in any case, this is my 32 bit register, right? I've got the data coming in, I've got the data coming out, I've got an output enable, which I'm always going to tie to ground, because that's the way the multiplexing register actually works. And that's the way the sequencer works. You never disable the output of a register. And it's got a clock, and all the clocks are tied together, and all the output enables are tied together. Okay, great. Let's go up one. And let's go ahead and import the signals. And this is something that the nightlies have. So this is probably familiar to you when you actually use a hierarchical sheet in the production version. So you may have seen this. You can actually put signals on any edge now, which is kind of neat. All right, this is Q, which will go on the outside. This is D, which will go on the inside. And then we've got the output enable, which I'll stick over here. Notice something else, that the labels that are buses are blue, just like buses should be. So that's kind of nice to. All right, let's go ahead and resize this. So to resize, and the key binding also changed a bit. So I have to click this, and then I can drag like that. Okay, so that's my register. Let's stick a buffer down. So let me start another hierarchical sheet. Let's make it just as big. Oh, wait, there's a clock that I forgot. Let me just stick that in. There's the clock. Okay. So now let me get a hierarchical sheet. Let me call it a buffer. Okay, so this is going to be the buffer for the PC. And the idea is that the multiplexer is just going to be made out of buffers with their outputs put together. And again, I have already pre created a 32 bit buffer. Okay, so if we look at that, oops. That's not what I wanted. So if you look at that, it's basically to 16244s with all of their output enables tied together 32 bits in 32 bits out. And the idea is that you just put a whole bunch of these together in parallel and tie their outputs together. And you know, the output enables are your selectors. And that's it. You're done. So um, let's go ahead and put the signals into here. So there's output enable, there's a that's your input and why that's your output. And there aren't any more, right? No more. Okay. Let's move this down more. So the idea is that you're going to have a bunch of these, right? So I'm going to grab this and control C for copy, control V for paste, control V for paste. So how many of these are we going to have? Six, right? Because there are six inputs. So one, two, three, just copy this, put that there. Okay, let's rename the sheets, rename the sheets. So this is buff PC. Can I use plus plus four? This is there was an X in there. There was a Y. Oops. Y. Okay. What? That's weird. Try again. There was a mem address. And address. And there was a mem data. Okay. So those are our six buffers. Let me go ahead and maybe move this down here. Okay. So the idea is that I just want to take a bus and connect it up to the input of the register. And all the outputs of all the buffers get tied together. Okay. And then the output here goes to this input there. Okay. And now we just have be paste, paste, paste, and paste. So these are our five other inputs and the output enables will work on a little later. The output enable here is going to be tied to ground. So let's just go ahead and do that right now. Grab a power symbol. Okay. It's ground. Let's just use that symbol. And the reason that I want to use this symbol instead of ground ref is that electrical rule checking sort of throws up a warning when the chip has ground has a ground has its power called GND and you connect it to GND ref. I just don't want to see that. So I also don't like the fact that the cursor is this big thick cursor and I sort of have to zoom in now. So maybe they'll change that. Maybe they won't whatever. Okay. So now we have this clock signal that's going to go out to the output. That that's sorry, that's that's going to go out to a connector. So on the sequencer, of course, you know, we have all the clock signals. So this has to go on to a connector. Okay, let's go ahead and move this a little bit. Okay. So the next thing that I want to do is put some connectors in here, right? So at this point, I don't know whether I want to use a 2x32 connector or maybe a 4x16 connector or, you know, maybe I'll do something which is a little bit more clever like I'll have ground signal signal ground signal signal ground so that any signal can couple to at least to one ground.  In fact, let's draw that out. Okay, let's move all this out of the way. And let's take a look at what something might look like. So here is one of the pins of the connector and we'll just connect it to a signal. And then we're going to put a ground here. And if I put another signal next to it, well, that signal can couple to this ground and this signal can couple to this ground. And yeah, you know, the return path is going to be composed of both of the signals returns return path. But, you know, it should be a relatively low impedance signal, which basically means that hopefully that the two things won't interfere. Well, that means that I can just put another signal over here, another ground over here and another signal over here. And the interesting thing is that if you look at the 16244 chips, they do exactly the same thing. They have two signals and separated by a ground, two signals a ground, two signals a ground. And in fact, in the middle of the chip, they actually have four signals for whatever reason. So anyway, if we do that signals, let's count the number of signals here zero, one, two, three, four, and then ground, and then signal five and signal six and ground and signal seven. So that's eight signals right there. So how many, how many pins is that? That's five, 10, 12, that's 12 pins. So notice that I that these are eight signals. So I didn't have to, if I interspersed ground between every single signal, then that would be 16 pins rather than the 12 over here. So, you know, I could just repeat this and then end up with a two by 24 connector. Or I can make it a little more compact. And let's suppose I have four rows. So a four by 12 connector maybe, because that'll be half as short, which is kind of nice. I don't know what I'm going to do at this point. So let's just let's just go with a four by 28 with a two by 28 connector. And you know, I can maybe change it later on. I just want to try something. Okay, connectors. So let's see, I have created this sheet here. Okay, so it's basically just a two by 24 connector. So there are 48 pins total. So there are the signals grouped into two sections.  So, okay. And what I can do then is just, you know, copy this and let's go ahead and import my pin. Great. And let's resize this doesn't need to be so big. Well, it's going to be big because of this thing. Can I, yeah, I can make that invisible. Oh, okay, that's that's convenient. All right, so here is my connector. I'm just going to stick it right over here. Well, okay, let me leave some rooms that I can name this bus, copy, copy these. And I am going to still need a connector for that, because that's going to be the PC output really. And then one down here for this input. Okay. How do I, how do I grab a bunch? I don't know how to grab a bunch. Again, they're changing the key bindings. So maybe it's right click. No, middle click. No, control click. No, shift click. No, alt click. No. Um, yeah, I don't know how to, how to grab all the end points for, for a bunch of wires. So I guess I'll just do this, like an animal. Okay. Oh, and I need a bus for this. Okay, let's go ahead and rename these sheets. I believe that in the production version, you can actually name the sheets all the same thing. But here, when you copy a sheet, it immediately adds a number to it. So, you know, maybe we should name all the sheets differently. So, oh, on PC plus four. Yeah, I don't like that when you hit enter. The sheet name goes away. That doesn't make too much sense to me. Oh, wow. Okay. Yeah, actually, it's a multi-line input. Wow. Okay. I'm not sure I like that. Okay, edit. Oh, this should be connector for x connector for x connector for y. Do I have to do like alt enter? No, control enter. Yeah, control enter apparently hits the okay button. So this is now mem address, mem data. And this one is PC now. Okay, so that's pretty good. I am going to need another connector now for the different output enables and the clock. So let's see. Well, I could just leave the output enables out and not like decode them through like a 74138, which is a three signal to eight signal decoder, which I could do because that means that then I only need three signal lines instead of six signal lines, which could be significant. So maybe I should do that. Yeah, why not? Maybe I should do that that way. If the if the selection is zero, then I'm going to decode it to to retain. Otherwise, this is one, two, three, four, five. And then of course, six and seven are are illegal values, which is kind of unfortunate. But maybe I can somehow or them together to to fall back into zero, maybe. I don't know. Okay, so let's go ahead and grab a 74138. I hate these symbols so much. These are like the very old style symbols. This is like totally totally incorrect for the for the current standard. But I'm going to go with it anyway. So let's just stick that down here somewhere. And let's see. So we want a wire to go up to zero. And the 138 is nice because all the outputs are negated, which is exactly what we need for these output enables, which are also negated as 34. Okay. So the question is, what do we do with these with these other outputs? So I could just leave them unconnected. Do I want to put it? No, I'm just, all right, I'm just going to make them disconnected and just say, well, you know, if if your if your input is six or seven, you deserve what you can't, I guess. Okay, so we have this now. Insert still works. That's nice. Let's go ahead and copy these. Okay. Actually, no, that's not what I want to do. So these are the various enables, which are highly useful for additional decoding, since we don't need any additional decoding. We are just going to tie the active low signals to ground and the active high signal to power. Let's go in here and grab me this five volt thing. Copy, paste. And I'm just going to leave the capacitors out, the decoupling capacitors out, because again, I'm just interested in sort of the layout of this thing. So there's ground. All right, so all right, that is our circuit with the exception of the other connector that we're going to want. So we have three inputs here. Here's the fourth input. And we're going to want power and ground. So assuming that ground is going to be... Yeah, okay, so basically six inputs. And we're going to multiply that by two so that we can have adequate return paths grounding for the signals, especially the clock. I mean, that's going to be kind of important. So what I'm going to do is I am just going to grab a connector and it's going to be an O2 by O6, odd even, because that's the way the pins are on the physical form factors. So we have this. That's nice. Let me move that down, maybe. Move that down a bit. And let me move the entire thing up a little so that I have some room at the bottom to route some signals. So here we go with the selections. And then we're going to have a... Let's put the ground here and then the clock. All right, so the clock is sort of nicely sandwiched between the grounds here, here, and here. There's clock. Okay, so this is going to be ground. So let me first remove that value since we know what it is. Copy, oops, copy, paste that to there. And this is going to be our five-volt connector. So copy and paste. Why don't I just connect these together? Well, because that that way, if I need to move this, I can just move it without having to worry about redoing the connection. And these are like that. Okay, so because the spacing is the same vertically and horizontally, we get coupling across the connector like this. So we don't really strictly need grounds between each of these. So that's it. The other thing that you typically need to do is add power flags to any power inputs. So power flag. And that just lets the design rule checker or electrical rule checker know that these signals actually generate power. Because the chips here, these are defined as power input. So there needs to be a power output somewhere. So if we just tie this net to a power output, that works. So let me grab this, copy and paste and rotate this so that it's upside down. And there are our two power flags. So let's just run a quick electrical check. So where is the design rule check? First, I have to annotate all of the things so that they all get numbers. Okay, save. And here's the electrical rule check. Let's run ERC. We got 148 warnings. And the warnings are right. This is what I was saying, where ground and ground ref are attached to the same items. And ground is going to be used in the net list. I'm fine with that. Same thing with plus five volts in VCC. And those are all the warnings. Yeah, I don't see anything else. But without the warnings, there are no errors. So that's good. Okay, let's name these buses. So we're going to name the buses. So this is going to be PC 0 to 31. Okay, now this is going to be, this is really the output of the multiplexer. So I'm just going to call it, well, not, maybe not why because we do have a Y bus. I'm just going to call it M, M for multiplex. Okay, and now I could also name these buses. So this is PC plus four, zero to 31. Nice that I can do that. I'll just stick that there. This is X. So this is X, zero to 31. This is Y, zero to 31. And the reason that you have to specify it like this for a bus is that I believe Kycat is going to match up the numbers, I think. So, you know, I don't know what would happen if you had like, let's suppose we had a 64 bit signal and we had two of these. If I did like PC, like X, zero to 31 going to one of these and X, 32 to 63 going to another one of these, if it's just going to apply it consecutively or if it actually matches the numbers, I don't know. And I guess I don't really care because I'm not doing that. So, all right, this is mem address. So I'm just going to call this MA, zero to 31. And then here, this is going to be mem data, MD, zero to 31. Zero, zero, zero to 31. I guess I can move these all over and then move the labels over because that would probably make more sense. Okay. Now, I just want to label these things. So I'm just going to label this S zero for for the selector. So S zero, S one. Yeah, I can just hit insert for S two. This is the clock. So I'm just going to call it clock. Okay. And then we've got each one of these lines. And I do like to label almost every net. So that when I go to the printed circuit board, I can, you know, the net appears right on the on the trace. So this one, I'm going to call negative select zero. Okay, doesn't look great, but okay. Negative select one, negative select two, negative select three, negative select four, kind of running out of space here. And negative select five. Sure, that'll do. Okay, that is that's the entire thing. Okay, so now I can move on to creating the printed circuit board. So let's see what that's going to look like. So let's grab the printed circuit board. And it's going to open up probably way too big. Okay, so before we go to the printed circuit board, we do have to assign footprints to each of things. So let's go ahead. Okay, so here we go, assigning footprints. So all right, so we need to pull out the connectors. So I'm just going to use the generic connectors, the pin header connectors that are point that are 2.54 millimeters or point one inches. And that is four. It's going to be two by six vertical. Okay, now for these, these are also going to be two by 24 vertical. And these have already had their things assigned. I'm using a SOP, which is fairly small. Although you want to use the same library, because one of them is the old style library, and one of them is the new style library, and they're going to look different on the 3D view. So is it housings or package? I think it's package that we want to use now. So where's package package SO. And it's going to be the one that's seven and a half by 15.9. So it's going to be this one. So I'll select these two and replace it with those. Okay. And then the 74 LS 138. I think I'm just going to use an SOIC. And which one is it going to be? I think it's going to be this small one. So we have SOIC 16 and SOP 16. We also have SOP 16 and TS SOP 16. Now, normally I would go to like Digikey or Mauser or wherever I'm buying it from and look up the right dimensions. At this point I don't care. So I'm just going to select that. Okay. All right. Now I can save and go to the printed circuit board. So let's go to the printed circuit board. All right. And going to import from the from the schematic. And there are all the parts. So these are all the parts that we have to fit in. If we scroll in, you can see the labels here. Labels on each of the pins and so on. So let's turn off the rats nest for now. So these are all the things that are going to make up our printed circuit board. Okay. So let's see. So the plan was to basically space out the connectors. Where's the where's the other connector? I thought there was a two by six connector somewhere in here. Okay. Let's go back to the PCB and see why that is. Yeah. Did I there we go. Okay. That looks a little weird. But okay. Let's just roll with it. But in any case, yeah, I I miss assigned the import. So now that's the right footprint. Okay. So as I was saying, the idea is that we want to space these out and put the chips between them. So just grab these and move them out of the way for now. Okay.  And as you can see, this is not actually on the pins themselves are not on a point one inch grid. Well, they are in this direction, but not in this direction. So select this and move. Okay, there we go. So I'm just going to stick this here. I'm not going to make a board outline yet. Yeah, this is one inch right here. And then the question is, can we fit the chip in between? Yeah, we can with some room to spare. I'm not convinced that that's going to be enough room. So I'm just going to grab this and move it over point two. And then I'll just do the same thing with the others. Okay, so now that I have them all spaced out. Let's see which one is PC. Okay, PC is this one down here. So the thing about the PC is that I'm going to need both buffers and registers somewhere in here. So, well, I guess, you know, luckily I can stick maybe the registers on one side and the buffers on the other. So I guess I'm kind of lucky in that respect. So let's just go with that. All right, what have we got here? We've got M and M. So for the Ms. So I'm a little unhappy with the placement of the registers because it means that, you know, if I have a register for like, let's see, what is this? This is PC plus four. What's this? MD. This is memory data. And this is memory address, I think. Well, one of these is memory address. So yeah, here it is. So if I want to do the same thing for a card where the registers are for the memory address, where the memory address could get the PC, well, you know, the problem is where do I put those registers? Maybe I can just put the registers on the end because no, I can't put the registers on the end because the outputs of the registers have to go to the inputs of that particular buffer, which means that I would have to stick them like in here somewhere, which could mean that I have to put these chips up here somewhere. So let's just do that exercise. So I'm just going to move this down this up so that it's right next to it. So let's suppose that that's the way we're going to orient things. So we've got the register here. In fact, since I want things to be a little symmetrical, I'm going to take this chip here and this chip here, right. So the idea is that we have buffer register buffer register. Okay, right. And then this connector, we're just going to move it like here, say, and this thing, I guess we can just, you know, put wherever we want. Let's just put it over there. Okay. So let me grab these and move them out to here. There we go. All right, my pins are on the grid. Excellent. So like I said, I'm not going to put down any of the capacitors. I'm just interested to see if the routing is going to work out on this. And the spacing in here is a little bit unsymmetric. Let's see what happens if I do that. So if that works, then I can shave off a few tenths of an inch. So what I'm going to do, let's see, see, I don't know how much room I'm going to need in here on the top layer. So I'm just going to leave it like this. And I'm going to route these signals over to these signals here on the connector. And we'll see how it ends up in terms of space. So if I need more space, I'll just move everything over. If I don't need that much space, then I'll just move everything a little closer together. Okay, so that's where we are right now. Now, before we actually start routing things, I do need to set up the number of layers and the design rules. So how thick, how wide the traces can be, what the spacing is, how small a hole you can drill. And I typically use JLCPCB for my printed circuit boards. So I'm just going to go with their design rules. So let's take a look at those. All right, so here are their capabilities. So we can see that they can go up to six layers. And if we look at, let's see, what do we want to see? So first of all, the minimum trace in space, right? So we can see that for four and six layers, the trace width is 3.5 mil, 3.5 mil. So that's what we're going to do, because I definitely go at least four layers, because that way you can have signal, power, ground, and signal. So that way you don't have to route ground and power on the same layers as signal. And four layers is cheap enough. There is a jump in price when you go to six layers. So with six layers, what I typically do is signal, ground, signal, power, ground, signal, like that.  But because of the thicknesses of the various layers, you don't get really good coupling between signal and ground that way. So it's just signal, power, signal, power, signal, power, sorry, signal, power, signal, power, power, signal, something like that. Okay. So that's the minimum trace in spacing. Let's take a look at the drill size. So what we want to do is look at the vias, or vias. Here we go. So for multi-layer PCB, the minimum via is 0.45 millimeters across. So that's what we're going to deal with. And the via hole size is 0.2 millimeters. So that's what we're going to have. Let's see. What else? We have annular ring. So annular ring is just the size of this part for plated through holes. So we're not going to look at that. Minimum clearance is the distance between things. So we can see that the distance between a via to a track, oddly enough, they have it between the track and the hole, which doesn't make a whole lot of sense to me, but okay. It looks like they're pretty consistent with that. So it's 0.254 millimeters, which I think translates to 10 mils. Yeah. Oh yeah, and here's pad to track 0.2 millimeters. Okay. So we need to set all this up. So let's do that. Okay. So here's our board setup. So what we're going to want to do is let's start off with six layers because we can always remove the layers afterwards. So copper layers goes down to six. And I know you can't see the drop downs. That's just OBS doing its OBS thing. So it's going to be signal, power plane, signal, and then two power planes, and then signal. All right. Physical stack up. We don't really care about that. I'm not too concerned about the sizes of things. Okay. So tracks and vias. Okay. So for the tracks, we're going to add. So the tracks are 3.5 mil. So let me go ahead and add a 3.5 mil. Oh, this is in inches. Okay. Let me just change that. Okay. So what I've so what I've done is I've gone ahead and changed the measurements to mills because some of the measurements are in mills and some of the measurements are in millimeters. Um, actually, even even the traces are in millimeters, but typically space and trace is in mills. So it's three and a half mills trace in space. So let's go ahead set up the board again. So now when we add this, we can say 3.5 tracks. Okay. And that's design rules. No constraints. Yeah constraints minimum clearance is I think 3.5 mils minimum track width 3.5 mils minimum annular width. We saw that. Let me see what that was 0.13 millimeters now. So I'm going to need to change back to millimeters. Okay. So 0.13. Now the via diameter is 0.45. And the minimum through hole is 0.2. And the whole to whole clearance is, well, it's via to via clearance for the same net is 0.254. But for different nets, it's 0.5. It looks like it's 0.5 millimeters. So let's just say it's 0.5 millimeters. Okay. And now we can go back to tracks and vias and add the default via size 0.45. What was it 0.45 with the drill of 0.2 millimeters. Okay. So I just got an error. You can't see it because OBS. But it's saying that the diameter and the drill leave via annulus less than the minimum of 0.13. So I can either increase the drill size the via size to 0.46. Does that work? Yeah. Okay. So now so now you can see up here that I've got my track and via size set. Now these can actually be set depending on the net class. So you can make some traces thicker than others, some holes bigger than others. But we're just going to work with this right here. Okay. Now the next thing that we're going to do is start routing some signals. So I'm going to take my grid and I'm going to change it to the lowest possible setting. And so let's just we're supposed to have some we're supposed to have six layers here. Did that not take? Okay. So I just had to set up the layers again because I forgot to save that. So here we have the smallest possible grid. And we're going to start routing on the front face front layer. And here's our routing. So what I can do is I can simply say, okay, there's MA0. And now I'm just going to route like that. That's really small, isn't it? That's 3.5 mils right there. So that's pretty cool because I think it means that I can probably maybe squeeze two signals in between each of these. Well, I guess we'll find out. Here's MA1 and MA2 goes right here. And here's MA3, MA4, MA5. And you can see that that this is actually going to be pretty easy to do. And it looks like I've got plenty of space. I mean, with a trace in space of 3.5 mils, which is 0.09 millimeters, that's really easy to do. And the thing is that JLCPCB does automatic electrical testing. So it will test from point to point electrically automatically. So any boards that have cracks in the traces or whatever, they're going to fail electrical testing and then they won't send it to me. So this is perfect. This is great. I wonder if I can fit like a trace in between. No, I guess I can't fit a trace in between these. That would be a little too much to ask for, I think. So okay, so I've squozen everything a little bit together. So from one end to the other, it's something like six inches or about 150, 160 millimeters, something like that, which is, you know, it's not bad. Here's my ruler and there's 15 inches right there. There's my pen. So it's, you know, you know, it's not it's not that bad. I can deal with it. So now the real question is will it route? And I'm pretty hopeful about this. So we've got one slight issue here. And that is if you look at this column here, you can see that for the outer layer, the trace width and the trace in space is 3.5 mils. For an inner layer, it's five and five. So this does have some restrictions on our layers. But, you know, hopefully we can stuff a lot on the top and bottom layers. And on the inner layers, you know, hopefully we won't have too many traces. And, you know, if we do, then we'll just go with five, five and five. So that's just something that we have to watch out for. All right. So, so as you can see, I've routed these 16 signals. Now the other thing that I need to do, so these are these are the inputs to the buffers. And then there are the outputs to the buffers, which all get tied together. So I think the idea is that on the bottom layer, I'm going to have just lines going straight across, right, because all of the outputs are on this side of each of the buffers. So I'm going to need vias for that. So I'm going to start with this one right over here. And I'm going to take one of the vias. I'm going to start from here. I'm going to bring this out. And I'm going to put a vias right over here. And I'm going to do the same thing with M4 like that. Now for M, now for the other ones for M2, I'm going to bring this out over here. And then for M1 on the other side. So basically, I'm going to stagger them. And the reason that I want to do that is that there's going to be a large, oops, there's going to be a large ground area here, a large ground area here, a large ground area here, because if you look at these traces, what's going to happen is on the bottom layer, I can just do like that. See on the bottom layer, we're going to have a line going straight out like that. And it's also going to go straight out here. And then, you know, probably in between here. So the idea is that all along that trace, you want to have a ground plane sitting just above it or just below it. Well, since it's the bottom, it's going to be just above it. And the only place where the ground plane is not going to be able to be right next to it is around the vias. So in other words, the return path is going to follow the line here, and then it's going to go around the vias. And unfortunately, that's going to lead to inductance, which means that your edges are going to be a little bit smeared out, which means that you won't be able to drive your circuit as fast. Now, to be fair, it's likely that the inductance caused by this via is not going to be a lot, especially if I'm just going to run this at FCT speeds, which I think is like one volt per nanosecond, which means that, you know, it's a swing from zero to five volts of five nanoseconds. So it's a five nanosecond rise time. Actually, the rise time is measured from 10% to 90%. So it's a little bit less than that. But you know, we'll just say it's roughly five nanoseconds. You know, we're not talking about sub nanosecond edges here. So we're not, you know, in the, we don't have frequency requirements in the gigahertz, you know, where we have to start worrying about stub lengths and things like that. So I think it'll be fine. But, you know, just for good practice, we do try to have plenty of ground surrounding the vias. Now, if I had all of these vias on one side, and if they were so close together that I couldn't get the ground plane in between them, then it could mean that the return path for one of these signals would have to go like this, and then it would have to go around all those vias and then come back. And that is a large area, you know, no matter how fast you're going. That's pretty huge. So that's why you really want to space out your vias so that there's enough ground plane between them. So now that I've done both the upper chip and the lower chip, what I could actually do is remove these traces from these other chips and just copy this entire section over and over and over. So I'm going to do that. Okay, so that is that taken care of. So you can see that all of these things are routed. So we've got all of our wires running across for the outputs. And we've got all of our inputs connected to the inputs of the chip chips, with the exception of the final program counter register and buffers, which probably won't be too much of an issue. So the only interesting thing is that these wires here, or these pins right here, do connect up to here. But they also connect up to here. And in addition, these m's connect over to here, but they also connect over to here. So this is going to be an interesting routing problem. I could rotate the chip by 180 degrees, which is a possibility. So that way, all of these pins and all of these pins are just connecting on this side. And that means that PC15, which is over here, would end up over here. And then I could just run wires like that. The same thing over here, m15 here would end up with m15 over here. And then I can run wires across like that. But then the problem is, how do I get these over to that side? So I could keep PC0 over here and rotate this upper chip so that PC0 is over here. But then I've got the problem of, well, PC0 has to go to here and to here. And then PC1 has to go to here and to here. And then PC2 would have to go here and to here. And if I do that, then I think I'm going to get some wires that have to cross. So that is not going to work. Because PC0 goes over to here, then well, okay, maybe I could route PC0 under the chip to here, PC1 down to here. And then I could take PC0 up to here, PC1 up to there. That could also end up working. So maybe I should try that. Let's try that. Okay, so now I've got this section routed. And now it should be a matter of doing the same thing for this other side, except of course now we've got vias in the way. So I can't really do this unless I can shove another 16 signals under here. Or I can just, let's see, I can't really route it with the green layer going up and down. Well, okay, let's just go with it and see what happens. Okay, so what I've decided to do instead is put all the vias on just one side. And yes, there is this plus five volt rail. And I would have to put a capacitor like right over here, instead of really up against the plus five volt pin. But hopefully that short distance won't make too much of a difference as long as I make the trace a little bit thicker. Then I can simply, you know, route the 16 signals underneath the chips and then run the wires on the bottom layer from here to there from here to there in parallel. So I think that'll work out. Okay, I haven't finished it. But I mean, it looks like it's it's going to work. So in fact, I was able to get away with only two signal layers. So I can use a four layer board, which is great for expense. And again, like I said, this is this is about six inches across. So I can measure this and it turns out to be 150 millimeters, which is pretty good. Let's take a look at the 3d view. Where's the 3d view? Okay, there's the 3d view. That's basically what it's going to look like. I don't know why there is no 3d model for this, but whatever. But yeah, that's kind of what it's going to look like. So if you can imagine that this is just for the program counter. So we also have, you know, one board for the temporary register, one board for the memory address register. So it's basically going to be this size, multiplied out by pretty much the number of registers that we have, which could be a lot. I know we have PC. We have temp, we have memory address, and we have memory data to write. That's four. What else do we have? Yeah. And then we've got all the CSRs. And I think the CSRs are going to be their own thing. Unfortunately, the CSRs are going to have to have their inputs multiplexed, which means that they're kind of going to look like this, which isn't that great, because there are seven CSRs that I have. So there would be, you know, like seven boards like this. So the total already is up to 11. 11 of these boards. Let's just see how long this board is. This board is about 75 millimeters. So, you know, 75. So we're talking about a meter wide board. So that's obviously not going to work. Another possibility is maybe to stack boards like this. So I know that I can get connectors that are actually stackable. So I don't have to run things in parallel. I can run things sort of up vertically. And if I do that, then maybe things go a little better. So if I have 11 registers, let's just call it 12, and I stack it four high, then I only need three across, which is, you know, something like 225 millimeters, which is doable. So that's a really interesting idea, just basically, you know, stack it in the third dimension. Yeah, I think that'll also help in terms of signal lengths, because, of course, now instead of having a signal going, you know, a meter across the board, now I just have a signal going, you know, maybe a maximum of 250 millimeters and then up, you know, a bit, you know, call it, I don't know, 50, 50 more millimeters or so, maybe a little more than that. So that's pretty good. Yeah, maybe I can do that. Okay, okay, I think, I think that's a plan for the sequencer board. Now the ALU boards and the register boards are, again, going to be their own thing, but I think I'm going to go with this and see what happens. Now the other thing on the sequencer board is, well, the sequencing itself, because all I've got right here are the multiplexers and the registers, and there's another section, which is basically the logic to control the multiplexers, and that is going to require something, and I'm not sure what, I would love it to be ROM based, but unfortunately ROMs are too slow, so that would be sort of like a very long instruction word. Or I may just build it out of some logic. I'm not really sure how it's going to work. I may end up using a whole bunch of gals, but you know, we'll see. So I think that in the next video, what we're going to do is we're going to take maybe a closer look at the actual sequencing part of things to see what sort of chips we can use for that. So until then, take care. Bye.


Welcome, in this lecture we are going to introduce notions of generalized solutions to wave equation. The outline is as follows, first we mention that the notion of a classical solution is inadequate and thus there is a need to generalize the notion of a solution and then in step 2 we show how to arrive at a generalized notion of a solution and then we demonstrate some generalized solutions to wave equation in 1D and in higher dimensions. In this lecture, we discussed the inadequacy of D'Alembert's formula, Poisson-Kirchhoff formula for a classical solution to the Cauchy problem for wave equation for describing physically relevant situations. We present the standard procedure to arrive at notions of generalized solutions also known as weak solutions for the purposes of this lecture to Cauchy problem for wave equation. Generalized notions of solutions to IBVPs may also be defined similarly. So recall the Cauchy problem for wave equation, here the data is given phi, psi and f and we are required to solve non-homogeneous wave equation D'Alembert's u equal to f and ux0 equal to phi x, utx0 equal to psi x for x in Rd. Recall from lecture 4.7 where we have derived the solution as given by this formula in 1D. This formula represents a classical solution if phi is C2, psi is C1 and assumption on f is that fx is continuous apart from f itself being continuous. So when the string is plucked at a point x0, what does that mean is this? Suppose this is a point x0, so string is pulled up so as a consequence how this string looks is like this is lying up to here and then let us say like that, like that and like that. So at this point x0 it is raised, this is a graph of u of x0. This is a situation clearly such a function cannot be differentiable at this point x0. The initial profile that is a graph of phi of x looks like a triangle as we have seen. In this physically relevant example the function phi is not differentiable at x0. Therefore this formula does not make sense as a classical solution because the function will not be u of xt will not be C2 because phi is not C2 it is not even differentiable. So therefore this formula is inadequate in this scenario. So in such a case where the Cauchy data is not smooth this formula let us still call it Dalambert formula even if we have a right hand side the source terms here right hand side in the wave equation. So this let us still call it by the name Dalambert formula. So this does not give a classical solution to the Cauchy problem. Worse Cauchy problem may not have classical solutions. Not only that this formula does not is not a classical solution it may not even have a classical solution. Thus there is a clear need to change the concept of a solution. So can we require some last ground? See this is the formula we have derived in 1D right for the solution of Cauchy problem. It is a classical solution if these conditions are satisfied by the data phi is C2 psi is C1 f should be continuous on this domain and fx should also be continuous on this domain. The formula itself makes sense for much bigger classes of functions because what all you need for this phi can be any function because there is no differentiability requirement on this. It can be any function this makes sense. Here I have a psi I need to integrate therefore psi should be integrable. But this is for every x and t it should be integrable on the interval x minus ct and x plus ct. Psi need not be integrable on whole of r it is enough it is integrable on every interval of this form or more generally any interval of the type a comma b closed interval a comma b. Similarly f, f has to be integrable on certain as we already observed this domain is nothing but a triangle. This integral integration is done on a domain which is a triangle which is called characteristic triangle. So we need f to be integrable on that. So let us see some assumptions on phi psi f which guarantee that the right hand side is meaningful therefore it defines a function. The question then is is it a solution or in which sense is a solution etc. For example phi psi are continuous functions as I told you there can be any functions f is continuous and hence it will be integrable on any triangle that you take. Psi is continuous therefore this integral is meaningful for every x and t that is what I have written here phi and psi are L1 loke. L1 loke simply means that this function is integrable on every compact set or equivalently on every bounded set. So similarly f is assumed to be L1 loke locally integrable this is a notation for that. Please note that we are using this notation L1 loke just to mean these are locally integrable functions it means functions are integrable on every compact set. Please do not confuse this with the Lebesgue function spaces of L1 L1 loke because these kind of things the point wise evaluation do not make sense if I say that this is the Lebesgue spaces but when we see the weak formulation their L1 loke it makes sense so there is no problem. So whenever we see point wise evaluations like this L1 loke stands simply for those functions which are integrable on every compact set and when we see in the weak formulations this stands for the usual Lebesgue L1 loke spaces. Now look at the formula in 2D. 2D formula is slightly more complicated than the formula in 1D because here phi comes along with the derivative also psi appears like before so it is not a problem but phi has a derivative. Now these are classical solution to the Cauchy problem where phi is C3 and psi is C2 and f should have this kind of smoothness properties. But the formula itself is meaningful for the following classes of functions when phi is C1 so these are continuous functions and you are integrating on closed disk so it must be fine integral will exist similarly psi continuous so integration is not a problem and f continues. We can further weaken the smoothness requirements on phi psi f by saying phi should be C1 that seems to be there seems to be no alternative because grad phi appears in the formula. Now we are looking for conditions on the data so that these integrals make sense. So phi should be C1 because grad phi is there and psi is L1 and f is L1. Of course this is not the exhaustive list of classes of functions there are much bigger class of functions for which this is meaningful and discussion of such things is beyond the scope of this course. Now solution in 3D same issue here because phi comes with a derivative. So the formula represents a classical solution to Cauchy problem if phi is C3 psi is C2 and f has the regularity or smoothness properties which is given here. Formula itself is meaningful when phi is C1 psi is continuous and f is continuous or more generally psi you can allow to be local integrable function and f also local integrable function. So from the last few slides it is apparent that each of these formula delambed formula Poisson Kirchhoff formula defines a function even when the Cauchy data and source term do not have enough smoothness to guarantee that the function is a classical solution. We have identified a few classes of functions to which such Cauchy data and source term may belong to in order that the expression for u of xt is meaningful or makes sense. This gives us a hope for the recovery of some last ground due to lesser smoothness of the data. Indeed there exist notions of weak or generalized solutions which admit such functions u as solutions to the Cauchy problem. We understood the need to admit functions which are less smooth as solutions because Cauchy data itself we have to admit which are lesser smooth. It may happen that solutions defined by this formulae delambed or Poisson Kirchhoff may give rise to a classical solution in a restricted xt domain. We have seen that such things happen in the case of burgers equations and conservation laws. We may use a formulae to study how the lack of smoothness in the Cauchy data propagates with time that is propagation of singularities. Lack of smoothness means it is called a singularity something is not smooth at some point that point is called a point of singularity. So, propagation of singularities in the Cauchy data with time. This we will discuss in lecture 5.7 arriving at a generalized notion of a solution how to do that. So, there are guidelines for relaxing the notion of a solution. We have seen this in lecture 2.16 where we have introduced in the context of burgers equation and conservation form of that. Three requirements on a relaxed solution. Any notion of a relaxed solution or weak solution or generalized solution whichever word you may use it must have the following properties. What are they? Any smooth solution should be a weak solution. This requirement is usually the guiding factor in defining any notion of a relaxed or generalized or weak solution. Any weak solution which is smooth enough should be a classical solution. Proving that the notion of a relaxed solution that we are going to introduce soon motivated by one the point one that is the requirement one has this property is left as an exercise because the ideas are very similar to what we did in lecture 2.16. Now the third requirement any reasonable problem should have a weak solution or a relaxed solution. Any notion of a solution is useless when reasonable problems do not admit solutions. Discussion of this requirement for the notion of weak solution that we are going to introduce soon is beyond the scope of this course. We will not discuss that. So, deriving a notion of generalized solution to Cauchy problem all the details will be presented in one space dimension. For higher dimensions obvious modifications are needed and we get a similar formulation we are going to show that formulation. So, let zeta be a C2 function on R cross R this 0 stands for compact support. That means support of zeta is a compact set. So, support is contained in a big enough ball equivalently. So, multiply the given equation the non-homogeneous wave equation with zeta and integrate with respect to xt over this domain R cross 0 infinity what we get is this that is simply integrating both sides after multiplying with zeta you get this equation.  Here we can do something here we see that there are derivatives on u and we are not looking for smooth solutions to the wave equation therefore we would like to relax this requirement and that can be done by transferring these derivatives to zeta which is integration by parts. So, nothing much to do on RHS we would like to integrate by parts on the LHS. So, this is the LHS first term in the LHS because there is also a dou 2 dou x square term. So, this on integration by parts you get this one derivative shifts to zeta and a minus sign will come and there will be a boundary term with respect to this 0 infinity t 0 infinity. Because t equal to 0 is a lower limit you will get another minus sign minus zeta x 0 dou u by dou t x 0 upper limit will not contribute because zeta has compact support. So, this is what we have but what is dou u by dou t of x comma 0 that is ix. So, we have got so we have done one integration by parts. So, let us do once more transfer this dou by dou t to this one that will make this minus as plus and the transfer is done and similarly as you had this term coming out of the integration by parts we will have one more term coming from this. So, that is this and the other term which we had here is written here. But now what is u of 0 it is phi x. So, this is what we get by integrating by parts in the first term on the LHS.  Again integration by parts here there will be no boundary term because with respect to x zeta is supported once again compactly and we do not have this situation of 0 infinity in when we are doing with respect to x that is why there will be no boundary terms that is why 0. So, it is do once more integration by parts we get this no boundary terms because integration by parts when you do you get an integral on the domain and you get an integral on the boundary. So, this is what we have. So, this equation we are going to use the standard notation this we call D'Alembertian 1 right square 1. So, in that notation I am going to write so I have just interchanged the LHS and RHS because this is where we are going to write expression for this. So, expression for this that we derived using integration by parts that is why I am writing here. So, this is what we get in fact what we got by integration by parts is this term on the RHS equal to this term on the RHS. So, what we did is that any classical solution to the Cauchy problem satisfies this equation which we have derived. So, this is the requirement 1 in fact that was a guiding principle now we are going to define what is a weak solution based on what we have got here. So, the above equation is meaningful for you meaningful for you which is not necessarily C2 because nowhere there is a derivative on U U is only here right nowhere else zeta is a smooth function with compact support C2 function with compact support. So, this is a continuous function with compact support essentially you need to integrate on a compact set. So, if U is L1 locally integrable this is meaningful. So, a notion of weak solution gets defined once we mention what kind of function we would like to be solutions. So, in d space dimensions any classical solution satisfies this equation derivation is exactly same. We have shown the derivation when d equal to 1 but exactly the same steps will give us this. The last equation is meaningful for locally integrable functions not only U for phi psi f also. So, we are now in a position to define a notion of generalized or relaxed or weak solution. Let phi and psi be local integrable functions and f be local integrable function on this domain r decrease 0 infinity. Let U be also an L1 log function the function U is said to be a weak solution to the Cauchy problem for the wave equation if this equation is satisfied by every zeta which is C2 uncompactly supported in rd cross r. The requirement 1 is automatically satisfied every classical solution to Cauchy problem is a weak solution. The weak formation itself was derived based on this requirement. Proof of the requirement 2 as I told before is similar to the idea which we presented in lecture 2.16. So, if U is smooth then it can be shown that U is a classical solution by doing integration by parts in a weak formulation. So, in the definition of the weak solution we had an equation right valid for all zeta in C02 C20 functions that is called weak formulation of the Cauchy problem. So, U is smooth means this because this is what we need for a classical solution. If all those conditions are met by our weak solution then it is actually a classical solution and that is left as exercise. Important questions it was easier to define the notion of a weak solution it is always easy to define something that is not a difficult job. Do we know some of the weak solutions? Do the Dallambert formula Poisson-Kirchhoff formula represent weak solutions to the Cauchy problems? This is the question. As mentioned earlier we are not going to discuss the existence of weak solutions. We limit ourselves to checking whether the named formula quoted above namely the Dallambert formula or Poisson-Kirchhoff formula are weak solutions. Let us look at some of the generalized solutions to wave equation in 1D. Recall U of xt equal to f of x minus ct plus g of x plus ct we have obtained this as a general solution to the wave equation whenever f and g are c2 functions. Now we are going to ask the obvious question is this a weak solution when f and g are not c2 functions. So we are going to show that this formula f of x minus ct plus g of x plus ct is a weak solution even if f and g are not c2. We will show that f of x minus ct is a weak solution. Similarly we can show that g of x plus ct is a weak solution therefore it follows some of 2 weak solution is a weak solution because equation is linear and homogeneous. Here what do we require if you want to show f of x minus ct is a weak solution. Definition of a weak solution wants local integrable functions so we can as well take f2 may be local integrable function. Since we are checking interested in checking that f of x minus ct is a weak solution to the wave equation and thereby we are not worried about the Cauchy problem. So this weak formulation where we insisted that zeta is c2 0 of r plus r now it reduces to exactly same equation without these terms and zeta we can take to be open 0 comma infinity and automatically these terms are not there. So essentially f is not there homogeneous wave equation so f is 0 and phi and psi are not there because zeta is compactly supported in open 0 infinity. Therefore what we have is just this and I want u of x t the candidate I am proposing is f of x minus ct. So we want to show this equal to 0 we need to show this. So let zeta be compactly supported function c2 in defined on this domain r cross 0 infinity. We would like to do integration by parts here but unfortunately we cannot do that because we are assuming f is not c2 function therefore I cannot transfer all the derivatives to this by integration by parts. So we have to do something else in particular we are looking for f to be a weak solution therefore this will be a l 1 low function we want to show that this integral is 0. Therefore there is no way we can do integration by parts but here somebody helps us with namely change of variables. Let us set x minus ct equal to xi and x plus ct equal to eta then this integral becomes this integral this is f of xi and this wave operator dou 2 zeta by dou t square minus c square dou 2 zeta by dou x square becomes minus 4 c square w xi eta of xi eta. W is nothing but xi eta expressed in xi eta coordinates then dx dt become d xi d eta by 2 c and the integration domain is the is upper half plane is given by eta bigger than xi. Now we can do integration by parts in this formula with respect to eta because f is l 1 low but depends only on xi so there is no eta dependence. So once we do integration by parts here the domain integral will be 0 and only boundary contribution remains and the boundary of this domain is precisely eta equal to xi which is nothing but the x axis. So therefore we should know what this quantity is and this is equal to 0. Here w of xi eta is nothing but zeta of xi plus eta by 2 comma eta minus xi by 2 c. So we will differentiate this with respect to xi and evaluated eta equal to xi. As the support of zeta is contained in r cross 0 infinity w xi of xi xi is nothing but zeta x derivative of zeta with respect to x at the point xi comma 0 into derivative of this with respect to xi which is 1 by 2 minus 1 by 2 c zeta t at the point xi comma 0 and that is equal to 0 because the support of zeta is contained in the upper half plane and here evaluation is happening because of the t equal to 0 we are on x axis therefore this is 0. Let us look at the example 2 of a weak solution. Dalambert formula whenever meaningful is a weak solution to the Cauchy problem. However the proof is not as simple as the one we saw in example 1 in which a change of variable yields the desired result. We will handle this proof using approximation procedure. In lecture 4.11 an IBVP for wave equation was solved a formal series was proposed as a solution. It was shown to be a classical solution if phi was C4 which is unreasonable we saw the example of plug string is unreasonable. However if phi is C2 the series nevertheless converges uniformly and it defines a function and that function let us call it u of xt because the series converges this is meaningful so that will be only be a continuous function not more than that. So it cannot be a candidate for classical solution but it can be a candidate for weak solution. So the nth term may be written as forget about this are numbers look at this term that can be written as this using sin a cos b formula we get this. Now something interesting is happening here this is a function of x plus ct this is a function of x minus ct. So each of the terms here is sum of 2 terms which is a function of x plus ct another one is a function of x minus ct. So we can split this series into 2 series then what we will have one series will be a function of x minus ct one series will be a function of x plus ct and we whenever you see a function of x minus ct alone it is weak solution to the wave equation homogeneous wave equation similarly other one x plus ct so and therefore it is a weak solution this represents a weak solution to wave equation. Let us look at another example in lecture 5.1 the following equivalence was established for a c2 function what was that u is a solution to the homogeneous wave equation if and only if u satisfies the parallelogram identity on every characteristic parallelogram. Parallelogram identity is meaningful for any function it just involves values of the function at the 4 vertices of the characteristic parallelogram a relation between the values of the function. So if a function u satisfies the parallelogram identity on every characteristic parallelogram then is it a weak solution to the wave equation that is the question. What we have shown is that if u is c2 then it is a classical solution to the wave equation. Now the question is u is any function which satisfies parallelogram identity nothing more than that no extra hypothesis on u being c2 therefore we ask this question is it a weak solution of course to define the concepts of weak solution you have to start with the L1 log function. So let us assume u is L1 log function can I do this. The answer to the above question is yes. So any function u satisfying parallelogram identity on every characteristic parallelogram may be written as u of xt equal to f of x minus ct plus g of x plus ct for some functions f and g this proves that you use a weak solution to homogeneous wave equation. In view of the arguments we gave in example 1 because the sum of two functions one is a function of x minus ct alone another is a function of x plus ct alone but how do I get this f and g I am given a function u which satisfies the parallelogram identity on every characteristic parallelogram how do I get f and g how do I catch them. At this point I would suggest you to pause the video try to find f and then g using the requirement which is here this is a requirement before you resume the video it is fun okay let us see how to get these functions f and g in the characteristic coordinates it is always easy it is easy to find f g such that w xi eta equal to f xi plus g eta now exactly do the same exercise as before pause the video try to find f and g from this requirement first you get f and then you get g once you try for some time then even if you are not successful it does not matter but you have tried so now you can easily follow what is being done on the next slide I have also tried like this I was not successful I try to define a function f of xi I have defined then g of eta when I am using this equation directly that is involving w xi eta minus f xi okay that is not a function of eta alone because xi is also there then I also paused for some time thought about it and then I got the answer so please try yourself okay let us see now fix l and k in R because we have to use parallelogram identity right without using that any formula that you try to do will not work I am sure about that once you try you will also be sure okay so fix l and k any f and g as above should satisfy this right if they exist w of lk must be fl plus gk so define f of xi equal to w of xi k g of eta equal to this now you see there is no xi in this expression that is a trick which works so let us compute f xi plus g eta I have to show if this is equal to w of xi eta so this computation will give us this and that is equal to w xi eta because these 4 points are the vertices of a characteristic parallelogram but in the characteristic coordinates system it is a characteristic not parallelogram but a rectangle so these are the vertices and you know the parallelogram I will do holds therefore this all the combination of 3 terms is giving you w xi eta so we have shown what you want to show but in characteristic coordinate system writing the proof for x t coordinate system is left as an exercise to you if you recall in lecture 5.1 we have shown the equivalence of a function being a solution to the homogeneous wave equation and if it satisfying parallelogram identity on every characteristic parallelogram in that proof we have presented only in x t coordinate system but if you think of a proof in xi eta coordinates it is very easy as I have presented here in this context so what we have done there you have to imitate that here in x t coordinate system so that is a hint for solving this exercise so please go back and watch lecture 5.1 again carefully. Try the proof of that theorem in characteristic coordinate system and see how we have written the proof in x t coordinates now exactly you should be able to do that by translating these ideas into x t coordinate system. Now let us look at some generalized solution in higher dimensions so in d space dimensions any classical solution satisfies this that is how we have defined the notion of weak solution based on this in particular when the Cauchy data is smooth as required the function you would define by Dallambert formula or Poisson Kirchhoff formula are weak solutions okay if you are thinking of d which is greater than or equal to 2 we need not mention the word Dallambert formula we would like to show the same even if data is not that smooth as required for classical solution but good enough to make these named formula namely Poisson Kirchhoff for D equal to 2 and 3 and Dallambert formula for D equal to 1 they are meaningful and define a function. So the idea is to approximate the non smooth data f i psi in the Cauchy problem with smooth data f n phi n psi n what is the meaning of smooth data smooth data means it is that data which when you take the Cauchy problem it has a classical solution and is given by those named formulae let that solution be denoted by un un is a classical solution corresponding to this data once it is a classical solution it is also weak solution. So therefore this is satisfied now I have written this with n everywhere okay it will be very nice if you can pass to limit f n goes to f u n goes to u pi n goes to phi psi n goes to psi so that the corresponding integrals will go to the corresponding integral where there is no n that is a dream always if the convergence is good enough to allow passage to the limit in the above equation then we would get that u is a weak solution. So what is the requirement on the data f i psi should be such that the named formulae define a function in 1D define a function which is also l 1 look in 1D f i psi in l 1 look is enough as we already observed in 2D 3D the formula feature derivative of phi therefore we assume phi or phi is c 1 f psi can be l 1 look so requirement on the approximations there should be as smooth as required to guarantee that the named formulae give classical solutions the following convergence must be guaranteed also which is that f n goes to a phi n goes to phi psi n goes to psi and u n goes to u because you please note that u n you have a formula in terms of f n phi n and psi n so u n has a formula and that u n should go to some function u in l 1 look then we can pass to the limit in this integral and get that u is a weak solution. So remark on weak solutions in higher dimensions we would not further elaborate on the existence of smooth approximations as proposed our intention was to present the ideas that would convince us to deal with bad Cauchy data without worrying much we dealt with many examples involving discontinuous data and we promised to justify it later and we have fulfilled to an extent in that promise so constructing approximation as required needs more background in analysis and this is another reason for skipping the technical details but the idea we have presented that is good enough. So we had the requirement on the data f phi psi in 2d 3d the Poisson Kirchhoff formula featured derivative of phi so we assume phi is c 1 so what to do if phi is discontinuous in fact one of our examples in lecture 4.6 there we have solved problems in higher dimensions there we have used a discontinuous function for phi so what happens perhaps we need to go for a weaker notion of solution than the notion of weak solution introduced in this lecture let us summarize what we did in this lecture so during our discussion on wave equation we have derived in many a context formulae for solutions if data is smooth enough the formulae gave rise to classical solutions at times we need to work with non-smooth data in such cases there are questions on what actually the formulae stand for in all those contexts we have given an assurance that we can make sense of the formulae to yield solutions in a generalized sense this lecture is an attempt to introduce notion of generalized solution in the context of wave equation so this is at the expository level we have not presented really details in this lecture d equal to 1 d'Alembert formulae parallelogram identity series solution for IBVP they were analyzed and for their candidature for weak solutions if you recall wherever we use d'Alembert formulae with discontinuous initial conditions parallelogram identity and the series solution we promise that we do not have to worry there may be some new notion or generalized notion of a solution which will admit them as solutions go ahead and compute so this lecture was an attempt to justify those statements d equal to 2 3 we had partial success in interpreting Poisson Kirchhoff formulae as a weak solution in the sense that we needed to assume phi is c 1 we assume that that is why only partial success we could not handle phi which are discontinuous functions in such cases as I mentioned earlier one has to introduce notions of more weaker solutions than weak solution. Thank you.


Hi, traders. Today during the webinar, we're looking at the S&P E-mini and started to combine the context of the market structure, the limit order book, and the transactions of trades where they're taking place to give insight to the future price movement. This is just factual data here that is displayed very clearly in book map, and combining those elements gives a nice context to the potential for that future price movement. So let's take a look. Cash open here at 9.30. We had the initial drive to the upside, and then we started to make a series of lower highs. You can see that we made lower lows down to the 67 level, but we started to note here in the limit order book very high liquidity at 67. Look at the amount of transactions that took place into that liquidity, and there's very few as you can see. In fact, they got more aggressive with their limit buys, and they raised their bid to ticks here. You can see that we traded into it, bounced away, and then traded through that area, but they did not trade through 67. In fact, look at the amount of transactions trading at these areas. There are very few market sell orders here. Now we can also note here them getting very aggressive, lowering the offer with their limit orders down to 69. There were 1,400 contracts here, and price did not come up and test that area. In fact, they even got more aggressive here, as you can see, at 68.5 with their limit sell orders. We were looking for a break of this 67 level, but due to the lack of transactions down at 67, we were looking for a break of 67 and then a rejection of that breakdown and to trade back into the range here. We ended the webinar actually right around this point here, and we can see some nice order flow activity. Note the breakdown here at 65.5, and look at the amount of transactions trading down here. There are very few market sell orders. Combine that with the intent of the traders here in the limit order book, and note how they're getting very aggressive. We were looking for a swing back up into 67, which we did see, and then we're seeing if we're going to accept or reject. It's this large volume here of aggressive market buy orders that gives insight to the potential to trade to the other side of the range here at 69. We ended the webinar here, but as we move forward, we can see that that's exactly what unfolded. Price rejected out of this area and traded into the other side of the range. It's looking at these elements of the price structure, where the transactions are taking place, and how the traders are behaving in the limit order book that gives insight to these types of movements. We go over information like this every day during the live webinars. Come and join us.