Welcome to this lecture on programmable logic devices in the course digital system design with PLDs and FPGAs. The last lecture we have seen a fitting exercise in PLD 22V10 that we have tried under some constraints to see whether an 8 bit odd parity generator can be fitted in the PLD. Then we have looked at the programmable technologies like EEPROM, EEPROM flash and how a wired and wired ore is constructed out of these transistors which is area efficient. Then we have an introduction to the complex PLDs which is kind of built out of the symbol PLDs ok which takes Q from the symbol PLDs. So today our focus will be the complex PLD before that we just run through the last lectures the material once. So we have basically seen the 22V10 structure, the macrocell and the summary of it that you have variable product terms, asynchronous preset product terms, synchronous preset product term. You can choose combination or registered output, you can choose an inversion at the output of combination section or registered section to apply de Morgan's theorem and optimize the number of product terms. An example is shown here basic timing details, combinational timing propagation delay and with respect to the flip flop and with or without feedback you know that is that means sometime with feedback you know like you have extra time delay added to the array because of the input delay and all that ok. And we have this was the question we asked 8 bit old parity generator. So it is nothing but 8 2 input exclusive or gates if you consider like that with you know one output is like 2 input bits go to at first XOR gate, the first XOR gate output and third input goes to the next XOR gate and so on. But the main thing is that we assume that this is expanded into product terms I mean that is complete expression is converted in like AX or BX or up to the 8th input is completely expanded into the product term which consists of 2 raise to 7, 1 to 8 product term. And the IO requirements because there are 12 dedicated inputs so 8 the requirement is less than that and one output but there are 10 IO so that is also IO satisfies the resource IO resources satisfies properly but we have to see the product term. And when we turn we assume that it is expanded then there are total 120 product terms possible but we need to cascade, we need to combine everything together in a 2 pass logic. So we need at least 9 product term to cascade because there are 10 total sections are there we take out 1 for cascading. So we have left with 9 sections so we need at least 9 product term to cascade. So we choose a section with maybe the 9 product term so the closest one is 10 one with the 10 so we have to remove the 10 from this 120 so we are left with 110 product terms. So when you expand this XOR implementation it is not possible to fit that into 22V10 PLD but if you like if you think of it as a cascaded 2 input XOR gates they assume that the first 2 inputs come here and 1 XOR gate that means 2 product terms are formed and that XOR gate output is cascaded to the next 2 input XOR gate and so on. You know like a chain in the 8 section then it is possible to implement or you take a tree approach 2 input XOR gate 2 input such 4 2 input XOR gate which will consume all the 8 inputs 4 outputs that can be combined in the next 2 XOR gates. And so you will get 2 output and that can be cascaded in the next section 1 XOR gate say 4 2 1 that is also possible so you can think of various other scheme maybe 3 input XOR gate 3 input XOR gate because 3 input XOR gate when expanded will occupy only 8 product terms so 3 3 2 which can be you know given to a 3 input XOR gate and you get the output. So various possibilities are there so if you the moment you assume internal nodes it is possible to implement but if you expand it to complete product terms it is not possible to implement. So that is what I have written maybe this was not there in the last same I have added that you can think of cascaded 7 XOR gate with 6 internal nodes it is possible to fit a lock structure that is 4 2 1 2 input XOR gates ignore this dynamic this is a mistake lock structure of 3 input XOR gates possible or lock structure of 2 4 input XOR gate that means you have 2 4 input XOR gate. But this will expand it to the 8 product terms you know 2 raise to n-1 and then that output is cascaded into 2 1 2 input XOR gates all these are possibilities various other possible maybe there are other cascading scheme you can apply but these are kind of low delay sensible structures which can be easily implemented. But a default approach of expanding into product terms will not fit into the PLD 22 V10 and the application of a SPLD we have seen it is glue logic random logic you can implement encounters finite sheet machine but this wide decoding is not required for many application one disadvantage is that it has hardly any number of flip-flops just 10 flip-flops with which you can do very minimal thing. But still it is useful when there is more of logic than the flip-flops and the application require less number of flip-flops and more logic than that can be used. And we have looked at the programming technology EEPROM transistor how the transistor is used as a switch in the normal case it acts as a n transistor when charges are trapped here it is kind of it is the gate has no control so it is switched off and we build the ion gate with this kind of transistor and once it is programmed it is permanent it is not volatile non-volatile but if you expose to UV this gets out and it becomes normal transistor. So to kind of remove the connection we trap the carrier charge here by applying a programming pulse here grounding it applying the normal drain voltage it gets you know trapped and it is removed by exposing to UV. So we have seen how an ion gate say a 32 input ion gate is formed with this transistor. So it is simple you have one line which is pulled up these transistors are connected to the ground from the line the gates are the one the inputs you know these inputs like one input is one kind of it is connected to the gate of one transistor second input is connected to second gate and so on like third fourth and so on. So when input is one this is pulled low so that means it is a wired NOR to make it wired NAND we have to invert the input PC because in a PLD both the input and it is complement is available. So wherever the I1 is implemented use I1 bar okay where I2 is implemented use I2 bar because both complement and the signal is available. So just do a swap then it works like a wired AND and then we have a wired OR structure which is again a wired NOR followed with an inverter. So it does not occupy too much you know it does not consume too many transistors as one thing because of this wired structure that is what you know the advantage of using the wired functions and the EEPROM transistor it is similar to the EEPROM and flash is similar to the EEPROM this silicon oxide layer is thin. So it can be programmed by applying the positive voltage programming voltage on the gate electrons get trapped it can be also erased by reversing the condition. So electrons get out so it can be electrically programmed electrically erased only problem is that when it is not programmed this conducts normally because of its construction.  So that is how it is programmed and the wired AND and wired OR is formed and the programming uses a standard file called ASCII file called ZEC and the usual normal IO pins are used to program it there are address pin, data pin, control pin, program pin and all that. So the programmer will apply a programming pulse to program pin then these functions of this program pins are exposed to the user IO pins and that is programmed and then in the normal mode these IO pins can be used that is how the SPLE is programmed and that needs a separate programmer you cannot program it within the circuit okay. So it cannot be programmed in circuit it has to be programmed in a programmer erased in a programmer but put to the board. So essentially it means that you cannot use some packages which can be directly mounted onto the PCB if it need to be reprogrammed okay if it is kind of one time programmable the design is frozen the designers are sure about it then it can be kind of mounted on the PCB directly no problem and we looked at the complex PLE and we said that there is no point in like you take a 22V10 kind of PLD and this already is quite huge you know you take there are section with 16 product terms and which many a times one does not require that and each AND gate is kind of 44 input AND gate. So it is a very wide AND gate with lot of product terms and now there is no point in blowing this up as I said you know there is no it does not make sense to have a 100V50 that means there are kind of say like 200 vertical lines and 50 outputs with huge number of product terms but what makes sense is maybe replication of these kind of 22V10 structures which is interconnected okay so that is what is a complex PLD is that simple PLD sections are interconnected. So the requirement is that output of any block like you have a SPLE block output of any block should be able to go to one or more input of other blocks suppose we have 4 blocks SPLE block one SPLE output any of the output should be able to go to any of the inputs of the other 3 blocks then only we can cascade and implement some useful function. Similarly you have input signals okay that those input signals should be able to go to one or more inputs of any block okay and now so the complex PLDs or CPLDs are hierarchical PLDs. So these are the simple PLD section interconnected okay so there is a product MRA that is nothing but RA of AND gates not big numbers like 22V10 where there is 8, 10, 12, 14, 16 these are small numbers say 5 product terms but there are ways to expand it we will see that and the macro cell is nothing but a flip flop with bypass and choice of the clock lines, choice of set and preset, choice of clock enable and so on. Now this the product M itself is not kind of permanently connected to an OR gate so in between comes a switch called product M allocator or distributor which allocates this product M to the OR gate or to an XOR gate or to control various functions of the flip flop okay. So we will see that maybe you can use a global clock pin to clock all the flip flops or you can use a product M as a clock okay or you want to reset the flip flop you can there is a global reset pin that can be connected to the reset of the flip flop or a product M can be connected it depends on the design maybe that in the design there is an FSM which need to reset a counter under some condition. Then a global reset would not help global reset helps during the power on at the power on you can bring all the flip flops to some required state but if an FSM need to control a particular reset then you need to have the product M as reset and that is done by the product M reset which is that this allocator does this allocator allocates a product M for not only for AND gate and sorry OR gates and XOR gates even to the control inputs of the flip flop okay. So let us come back to the slide then you have IO cell basically which is these are pins with tri-state gate which can be used as output and input and at the end is this programmable switch which connects the various PLD section okay. So we have various PLD section I have programmable switch to interconnect them not only the programmable section the IO cell also within each PLD section you have product MRA product allocator or distributor and macro cell okay. So let us so essentially it means the 22-eaten like sections are replicated okay. So we have seen the manufacturers Xilinx as XC9500 and Coolerunner, Altair as max 3000 and 7000 max 2 and 5, Atmel as ATF 15, Ladders as ISP and MAC and things like that okay. So here this is the Altaira max 7000 CPLD this is taken from the Altaira data sheet I will be using the data sheet of both Altaira and Xilinx because some diagrams are good in Altaira some diagrams are good in Xilinx the architecture is kind of similar. So you need not worry maybe specific the numbers input output and all may vary between the devices but otherwise the architecture is similar. So you will be able to you know understand by using a mix of Xilinx and Altaira device diagrams okay. This is what I call a simple PLD section the Altaira called a lab logic array block A, B, C, D. So depending on the device there may be 2 blocks 4 blocks 8 blocks 16 blocks 32 blocks like that you know. Now each block you see there are 16 macro cell that means there are 16 sections of AND or and flip flop okay. But it is all fixed it is not variable like 22V10. So you have 16 macro cell when you say macro cell it includes everything the AND gates, the distributor, the flip flop all the programmability everything is together is called macro cell in this data sheet. My description kind of is little different I combined the flip flop and associated thing I have called as macro cell but this is just a matter of kind of name do not worry too much about it. So now you look at this you have a macro cell section the input of it. So here we have 36 input comes from a huge switch okay. So you can think of it as a cross bar okay we will see what is a cross bar. But this switch output is connected to the input of the AND gates okay. So that is programmable. So you have 36 means 36 inputs and it is complement is available as a vertical line as in the picture okay. So and you have an AND gate and the few AND gates go to an OR gate, XOR gate and flip flop and so on. So there are 16 flip flops, 16 section, 16 output and that can be connected to 16 IO pins or it can be fed back you know it is not that it can be just taken an output can be fed back to the array back. So that the idea is that this output you implement some logic function the output of it can go to the input of some other section maybe it can go here it can go here it can go here some of it can go here some can come here and so on okay. So all that is available okay and in addition to that you can see that not only the output goes to the IO pin and it is fed back to the array you have IO pin itself acting as input and that inputs can come straight as input to the this huge switch okay. Now you see this switch if you take just assume there are only two sections okay to make the description simple this is not there this is a device with just two blocks two laps then we have you see 16 plus 16 32 plus 32 64 input to the switch and 72 output 36 plus 36 72 output from the switch. So when you say cross bar it means that like all these 72 inputs can be any of them can be connected to this sorry this 64 can be connected to any of the 72 maybe the first pin can be connected to 10 then 15th 7th can be connected to 6 and 2 and 9 can be connected to 1 and so on. So all possible connections are possible that is called and why it is called cross bar is that you know the inputs come like a horizontal row and the output goes as vertical row and the intersection you can assume a switch then all possible connections are possible that is why it is called cross bar which essentially come from the telephony old telephony nomenclature it is those exchanges used to be cross bar because if there is a 10,000 line exchange in principle 5000 people can conduct 5000 people okay.  So for any 5000 can conduct any other 5000 that was the idea. So that is the basic architecture we will see the internal detail but you see here there are additional signal one is a global clock pin there could be multiple of them in this particular CPLE there is only one and that goes to this all the sections you know the same thing goes to all the sections basically you can choose to clock your flip-flop with this clock okay if needed it is not that you are limited with it you can use a product term to clock it but you can use this also. If you are not using this as a clock then it can be used as an input to the it is not wasted like as a dedicated pin if there is no global clocking you are using then it can be used as an input to this switch and can be taken as input to one of the logic block okay. Similarly there is a global clear that is a asynchronous reset which can be connected to the flip-flop once again if it is not being used it can be used as an input to this huge switch okay. And similarly you have output enabled because there are tri-state gates which can choose to output enable either of them depending on your need or you can choose you know to permanently enable it permanently disable it and so on. So, in case if it is not being used again not waste the pin that can be used as input to this crossbar switch okay. So, that you should keep in mind so this you know explain the architecture from the top level architecture how the logic blocks are arranged, how it is interconnected, how the output is able to go, output of macrocell is able to go to the IO pin as well as to the input of various section. The IO pin itself various IO pins can go to the inputs of any of the section you know that is what is shown here. So, let us move on so it is a crossbar switch. So, we have this programmable interconnect array is a crossbar switch satisfying the connectivity requirement discussed before. It means that any output can be connected to any of the inputs, any IO pin can be connected to any of the inputs that is the requirement. N by N crossbar can be implemented using N, N to 1 multiplexer we will see that. Interconnection between blocks use just one switch okay. So, it means that when you take an output from a macrocell and connect to the input of a macrocell it need only just one switch okay. We will see that as when we go to the FPGA when you interconnect some output input most of the time it encounters lot of it goes through lot of switches. But in a PLD like straight from one output to one input there is just one switch programmable switch. So, this interconnection is very fast and the timing analysis is also fast like when you want to do timing simulation the timing model of the device itself is simple. So, it is very fast the timing analysis is simple. But the problem is that this crossbar won't scale well because if you so this can become very huge because in one section itself it is 74 cross 32 switch and you can imagine if there are 16 section this switch will be very huge and so it cannot be kind of expanded to lot of macrocell you cannot say millions of macrocell then this switch will heat up all the space occupy lot of area and then because of the area the things can slow down okay. So, I am showing an example of a 2 by 2 crossbar. So, you have two inputs I0 and I1 put O0 and O1. So, the requirement is that any of the input should be connected to any of the outputs. So, you put a 2 to 1 max for each output with a select line and inputs are connected to two inputs. Now by selecting S0 any of the input can be kind of taken to the output for both and if you want I0 to be connected to both it is possible there is no problem there is no clash it is not that you can connect only one input to one output it can go to multiple output. So, if you have a you can imagine if there is a 16 by 16 crossbar then you will have to the each output there are 16 to 1 max connected and such 16 of them. So, that is how an n by n crossbar require n, n to 1 multiplexes. So, you can imagine if you have huge switches these very wide multiplexes are required and that can occupy lot of area and the delay can be quite high in that case okay. And these are the max 7000 devices you have EPM 7032 it means there are 32 macrocell. So, basically each macrocell has 16 each logic array has 16 macrocell. So, for 32 macrocell you need 2 of such section for 64 you need 16 into 4 of them. So, that is what is shown here 7064 need 4 logic array blocks and it has 68 pin. So, you can imagine this as IO pin plus the clock output enable and VCC ground and things like that. So, that is how it comes. So, the highest one is there are 16 logic block which is which has 256 macrocell. It is quite a you know big device with lot of the macrocell 256 macrocell is quite high and you can implement many medium complexity design in such a CPLD. So, let us move on. So, this is the crossbar of the silings XC9500 this is not the crossbar of max 7000 it is a silings XC9500 crossbar. I just wanted to show the picture and that was clear in silings data sheet. So, you have an IO pin there is an array like which is here and a distributed flip flop and the bypass and such 16 outputs are coming to the 16 pin and you can see that that is also fed back to the crossbar switch to be kind of you know you can take that into the various logic blocks. And similarly the input is also coming as input to the crossbar switch which can be taken inside the logic block. So, that is how the crossbar is formed this the outputs of the macrocell as well as the input IO pin input is going as vertical line and the AND gates can take you know choose any of them by programming the crossbar okay. So, depending on how you design how you code these switch status will be decided okay. So, basically your VHDL code will be converted into this kind of what switched to program at the end okay. So, that is a basic game. So, this is the real macrocell okay or the logic part of the one section. So, you have one IO pin which is with a tri-seat gate and all that which is not shown here. So, what is the one section circuit is shown here. So, basically you have to look at 5 AND gates okay. And you see one of the AND gate is fed back into the array itself okay. So, this is kind of can be cascaded this AND gate can be cascaded to other AND gates. And there are 16 section like that. So, there are 16 AND gates from each section can be used by any of the section. It is not that this AND gate from this section can be used only by this particular section it can be used by other sections also other macrocells also. And you can see this is the input signal from the crossbar or PIA programmable interconnect array. So, there are 36 signal coming its complement is taken. So, 72 vertical lines which can be programmed to the AND gate to form the product terms for whatever requirement. So, basically 5 AND gate 1 AND gate is an expander product term which is fed back into the array. So, there are 16 sections. So, there are 16 expander product terms. And now this is a normal OR gate which AND gate output goes. But mind you this is not permanently connected. There is a switch here which is called product term allocator or distributed or silings call its product term select matrix. And that allocates the AND gates to the OR gate or XOR gate or various other purpose which we will see that. So, this is a kind of a switch which you know you can choose an AND gate whether it should be connected to OR or XOR or this inverter and so on okay. Now, let us look at the flip flop you see that the OR gate output is going to XOR gate output input and XOR gate output is coming to the flip flop input. And the flip flop Q is going to a bypass MUX. So, here there is a 2 to 1 MUX which get the output of the flip flop as well as the input of the flip flop. So, if you choose this path then you are not registering the output you are taking it directly. So, if you want to implement some combination circuit without register then you can use this path the tool will choose this path. And you can see that this flip flop can be used as a D flip flop or a T flip flop. So, if you have counter applications you can program it as a T flip flop it has a asynchronous reset which you see can be controlled by a product term. So, that is how the switch comes suppose you want to reset it using this product term it is possible there is a connection here which the switch does and then you can reset that. Similarly, there is a asynchronous clear pin which now has two options one is there is a global clear pin for the PLD chip. You can use it to clear along with all the resist all other flip flops or you want to very under some condition you want to clear it. Then you can use this line and the product term allocator can allocate an AND gate to this. So, depending on some condition you can reset it okay. And what we are left with is a clock and the clock enable. The clock enable is nothing but a recirculating MUX with the select line as enable. So, maybe I can show that we have learned that when you want to control a register what you can do is that you can put a 2 to 1 MUX. And if that condition is satisfied this input goes there and otherwise it retains its value. Now, when the max 7000 flip flop as a inbuilt recirculating MUX and the select line of the MUX is called clock enable. So, you want to kind of do such a structure just connect this select line here. Now, the condo signal here you do not need to do anything and automatically it works. So, that is what is this clock enable is about enable A and now you can have permanently enable it or you can control with a product term okay. So, it is quite versatile you know you have 5 product term one of it is an expander product terms. And this can be distributed to an OR gate set clear the clock enable and so on. So, very flexible the device is very flexible. And you can see there is a fuse which is a programmable register that means you can choose depending on the value program here it will become a D flip flop or a T flip flop. So, you can imagine a simple circuit where it can buy 1 out of 0 you can switch between D and T maybe you can think of such a circuit it is very simple. Now, not only that you know you see here there is one issue you just have 4 product terms anyway one is common. So, 4 product terms only or combined with this 5 or some common things, but many a times you want to implement say 10 product terms. Then what you can do is that suppose the previous macro cell as unused product term say for some reason suppose the previous macro cell used only the flip flop then what can be done is that that unused product terms can be steered to the input of this OR gate. So, basically you can cascade the unused AND gate from the previous adjacent section to the OR gate. So, it is a great advantage because if you need more than 4 product terms or 5 product terms then if there are some product terms which is left unused that can be kind of steered to this OR gate through a cascade of steers you know it goes all the way like if the previous section is not used here it can be used in the next section and so on ok. And it can go in some devices only in one direction in some other devices it can go in both directions and so on ok. So, I think you get a good idea and or and this XOR gate now can get the input from one of the AND gates. So, XOR gate can be used for you know the product term optimization as I said you can apply de Morgan's theorem and instead of having Y here you can implement Y bar inverted and take the Y there if the number of product terms are less it can be used for programmable polarity that if it is 1 it is inverted if it is 0 it is not inverted it can be used for arithmetic circuit like half order full order or for parity all that you know all kinds of use you can make use of this XOR gate so that is pretty much the architecture of the macro cell and so the summary of that is that you have 5 product terms per macro cell you can choose between D or T flip flop. Flip flop can be bypassed for combination output XOR gate for polarity PTE optimization comparator arithmetic circuit parity you have product term set product term reset or global reset global clock or product term clock product term clock enable all that is possible in this architecture. Now mind you in this device suppose you had a say an input synchronization has to be done we have seen how a single state synchronization can be done. So there is a signal which has to be taken to a flip flop to synchronize it. So in this max 7000 CPLD if you want to synchronize it it has to suffer an IO delay it has come through the switch and switch delay it has a gate into ion gate then the OR gate then it has or one of the ion gate output can be connected to the flip flop. So it is before getting to the flip flop it suffers a lot of delay. So it will be good for input synchronization directly one of the input can be taken into the flip flop. So such a thing is possible in max 7000 S they have apart from all these connection from the IO pin there is a direct connection to the flip flop which allows low setup time otherwise you will have to set up the input if it is taken through the cross bar you have to set it up much before the clock edge. But with this it is can be set up very fast you know little time before the clock edge it can be set up and that is the advantage of this and that is so from the IO pin there is a direct connection to the max before the D of the flip flop. So you get output of XOR gate or from IO pin directly for the fast input and that is pictorially shown like here you can see that the max 7000 CPLD is like this max 7000 S is little different everything is same you have input you have output feedback IO pin but you can see that from the IO pin there is a direct connection to the flip flop inside ok. So here, here, here like that so it has some timing advantage so if you choose max 7000 S it has some timing advantage it has instead of 1 clock it has 2 clock it has a output enable which is little more elaborate and so on ok. So that is about max 7000 S. Now let us take an example we want to see like say we are showing a code how this code get translated into that CPLD architecture. So look at this which say process clock reset begin I hope you remember the VHDL we have discussed. So if reset is 1 then Q is 0 else if clock event clock is equal to 1 then under that if enable is 1 then Q gets AX or B ok. So naturally upon this is an A flip flop with asynchronous reset and a clock and this enable naturally we know that this AX or B should be connected to the D input of the flip flop because it is synchronous upon the clock if Q has to get that it has to be connected to the D but there is a control if enable is 1 then only this should happen otherwise the Q will be the previous Q ok that is the meaning of end if there is no else and this shows the memory ok. So that is implemented easily through a recirculating max. So the synthesized circuit will look like this you have a flip flop the clock goes to the clock reset goes to the reset and the Q is coming back to a 2 to 1 max and enable select line of the max is connected to the enable. So when enable is 1 this AX or B goes to the D otherwise it retains and if the reset comes it becomes 0 ok. So that is how basically it is implemented now if you look back at the architecture you can see that we need an XOR gate. So XOR gate can be implemented here. So taking 2 inputs here A and B and A can be connected here B can be connected through the OR gate here ok and enable signal as we implemented that can be connected because the recirculating max is built in that can be connected to another AND gate. So then we have the clock and the reset and all that. So that is what I am going to show that. So this is the code upon the reset Q is 0 upon the clock if enable is 1 then Q is AX or B and that is the circuit A flip flop with a recirculating max select line is enabled and to the 2 to 1 max you have AX or B. So naturally this is built into the flip flop so we connect the AX or B output to the D directly ok. So look at this diagram so we have the flip flop we have a reset global reset. So that is connected through this switch to the clear so that it is when it is reset asynchronously it is cleared. We have only 1 clock so we can assume it is global clock so this switches program for the clock and you have A and B pin which I am not showing which is going to the cross bar switch and the cross bar output is coming here to say A is coming to this AND gate B is coming to this AND gate and this particular AND gate goes to the one of the OR gate input and go to XOR gate and B directly goes to this AND gate and go to the XOR gate here. And we have an enable signal which again comes through the IO pin and the cross bar switch and come directly through the switch to the enable because that is there is a recirculating max built in and the Q is taken directly to the pin. So if you write a code like that then this is how the macro cell gets programmed in addition to that you know that there will be A and B pins connected here and which will be taken through this the cross bar into this array okay and similarly enable. So that you have to remember there is more programming within the cross bar switch. So that gives you an idea and this can be easily worked out you know given a code we have seen how given a code you can infer the synthesized circuit and we have learned enough about the architecture of PLD and CPLD and you can work out the connections and you can even estimate how many what all the sources are used within a CPLD. So that is the power of it by understanding the low level details rather than you know just writing the code and hoping that everything works properly. So you are able to suppose I give you a counter and if you work out the equation and you will be able to come and you know infer the circuit out of that VHDL code then infer the connection in CPLD and you can see how many pins of the CPLD is used how many macro cell how many product terms to that detail you can go and some of the tools allow you to see this detail within the device and you can view that and kind of verify that it is right you know that what we have kind of estimated is right ok. So this shows let us move to this kind of this product term select matrix I am going to this is an Altera data sheet but this for that I am going to the Xilinx XC9500 product term allocator which may be little different from the Altera because there may not be an expander product term but nevertheless it shows the idea of the product term allocator. So you can see there are 5 AND gates and there are OR gates. So you can see that this AND gate output one of the like there is a demarc one input is connected to this AND gate sorry OR gate and this one also can be connected. So all the 5 are connected to 5 input OR gate but not that you see that if you are not using this product term for this OR gate it can be used for setting it ok can also use a global set or reset. Similarly take this product term it can be used and this can be used with the OR gate or you know to as an input of XOR gate. Now XOR gate itself can be can in one of this input of XOR gate can come from a product term it can be permanently one by you know kind of controlling I mean inverting the signal or 0 by letting it through similarly this one can go to OR gate to clock it or and this one can you know go to the OR gate it can go as clock enable it can go as product term reset and so on ok and this can go as a output enable. So the design is architecture is little different between the max 7000 and XC9500 but this shows the steering product term steering all these 5 product terms are odd and given to this structure which can be taken to the upper macrocell and lower macrocell and you can see that what happens in that upper macrocell and lower macrocell is that. So this is coming from the upper macrocell that means that there is a section there with 5 product terms and there is an OR gate XOR gate that is kind of diverted here and now you see you can take that and put this is connected to this OR gate. So you can cascade the previous AND gates through an OR gate right down here. So if you have more than one product term and this goes through so it can be like you can you can see that it gets combined there. So you can and so if you look at this section you see this 5 product terms can be combined with the previous one, the top one and the bottom one. So you have 15 product terms that can go up or down which wherein it can be taken to the OR gate of that section. So that is what is this product term steering is what we are calling. So you can if you are left with if you need more than 5 product terms that is possible by product term steering. So basically these are demultiplexes at the output of product term which then can be steered to the XOR input product term clock, clock enable, set reset, steering and all that. Basically it is steer you know that steer from the upper to lower combine various sections and use it and all that. So it is quite useful and if you look at the max 7000 S IO control, there will be a tri-state gate as IO pin. There is output if it is enabled input it is disabled. So there is a max by which you can permanently enable, permanently disable or you can choose the various output enable from this huge switch because we have seen there are output enable multiple output enable pins which is coming to the product term this cross bar. So either it can come through the cross bar to this or some product term can control the IO status of a particular pin. So it is quite flexible under some product term which is in some other block can control a particular pin you know. So that adds to the flexibility. This is the timing model of the CPLD max 7000. So it captures all the delays. Suppose you have a signal which is coming through an input pin. So there is a delay ingot it goes to the cross bar it incurs a delay then it goes to the logic array. So it an AND gate delay is incurred and if there is an expansion by parallel expander additional cascading is added. Then if it goes to a flip flop setup time is added and if it goes to the tri-state gate there is a delay. So similarly if there is an input there is an IO delay and then again it is PIA or for fast input it directly comes to that max delay and come to the flip flop. So the timing model is very simple and the tool basically tool use this model to estimate the time but you yourself can put this picture and estimate the timing manually without even writing a code you know that is possible to do that if you have the idea of the circuit you want to implement. Basically the timing model of the PLD is very simple that is what I want to convey. So when we come back CPLD versus FPGA so though we have seen the FPGA basically the PLD still use an AND or structure to level number of registers are very small which is not the case with FPGA. Timing is simple which is little complex in FPGA. Architecture variation that means across the manufacturers they have the similar architecture the programming technology is flash and the capacity is kind of 10 gate maybe we will look at the FPGA part after going through the FPGA. But the basic thing is that it is non-volatile up to kind of medium complexity or low complexity can be implemented and it is very fast you get reasonably fast implementation and number of registers are small. So you cannot think of the FIFOs and memories and things like that it is very difficult to implement. So the application is that very small design comprising of counters finite sheet machine small logic all that those are the target application maybe you can build a memory controller DRAM controller a protocol translation some optical encoder small control circuit for instrumentation power electronics data acquisition and things like that. So small and medium kind of application you cannot you can use this CPLD. But designs which require lot of registers and memory cannot be implemented in this like signal processing like various filters complex arithmetic circuit packet processing modems codex like the cryptographic circuit all that will be difficult to implement in a CPLD. So that is the limitation of the CPLD. So I think we have come to the end of the CPLD what we have seen today is basically the CPLD architecture how it is a hierarchical PLD is formed out of symbol PLD sections. So there are logic blocks a crossbar which interconnects which allows the output to go to the other inputs IO pins to go to any of the inputs. And then there is a product terms product term allocator which allocates it for various things a flip flop with clock enable the recirculating MUX fix you have the set reset which can come from globally a product term. The clock can be global clock or the product term clock enable us can be global or the product term. And there is in some cases there is a fast input and we have seen the crossbar is nothing but multiplexers at the output. So N by N means N, N to 1 multiplexer product term allocator is nothing but demuxes at the output product term. So that it can be connected to various other inputs like or XOR and flip flop controls and things like that. And there are additional or gates which can be kind of used to steer this unused product term to the next section and chain it you know like that to build quite a bit of product terms. And it varies from device to device how it can combine but you can refer to the data sheet. And we have seen the timing model which is very simple and we have seen the application you can use kind of best product called translation DRAM controllers small power electronics instrumentation data acquisition control circuit can be implemented using CPLD. CPLDs are also ideal for the counters have some small random logic all that okay. But it cannot implement lot of memory complex arithmetic and so communication signal processing computer architecture applications may be out of it networking all that will be out of it but then CPLD has use as advantages. So we should focus on the advantages and use wherever it is required. So I wind up here the CPLD part we will in the next lecture we will move to the FPGAs and please revise it try to understand that that will be very useful and I wish you all the best and thank you.


Hi and welcome to your session. Let us work out the following question which says, the sum of the perimeter of a circle and square is k, where k is some constant. Prove that the sum of their areas is v, when the side of square is double the radius of the circle. So in this question we are given combined perimeter of circle and square which is equal to k and we have to prove that combined area of circle and square is v, when the side of square is double the radius of the circle. Let us now begin with this solution. Let r be the radius of the circle side of the square. Combine perimeter, combine area and the square is equal to perimeter of the circle that is 2 pi r plus perimeter of the square that is 4 x and in the question we are given that combined perimeter of circle and square is equal to k. Now this implies x is equal to k minus 2 pi r divided by 4. a is equal to area of the circle that is pi r square plus area of the square that is x square. We have to prove that this area is least when side of the square is double the radius of the circle. Now x is equal to k minus 2 pi r divided by 4. So this is equal to pi r square plus k minus 2 pi r divided by 4 whole square. So a is equal to this. Let us name this as equation number one. Now differentiating with respect to we get b a by b r equals to 2 into k minus 2 pi r divided by 4 into 4 and this is equal to pi r minus k pi by 4 b a by d 0. Now this implies substitute the value of k at minus pi square r by 2 minus pi x plus pi square r by 2 is equal to 0. Now this and this gets cancelled out and we are left with 2 pi r minus pi x equals to 0 and this implies x is equal to 2 r. Now we will find b to a by d r 2 this is equal to so by second derivative test we can say that this minimum is equal to 2 r. This is the session bye and take care.


Okay. Hello, everyone, and thanks, Javier, for your introduction. So, yeah, the talk topic is how to build a Python community. And, well, yeah. So, let's get started with the annoying parts. That's me. That's my Twitter handle. The picture actually from Python, Finland, 2012. I think, yeah, I think it's a Python, and you can reach me in that email address, and so forth. So, the talk topic is how to build a local Python community. So, what we're going to go through in this talk is that, well, first of all, like, first thing is why build a local Python community? How do you manage expectations? If you build something from scratch, like, how do you deem if it's a success or not? What resources do you need? And if I have time, I try to leave some time for the question in the end. If I have time, I'm going to go quickly through, like, how do you grow up your community once you establish something? But, first, the internet is an amazing place, not for the old parts of it, but some parts. Like, there are really good guys online. There's the pip install PyLadies, there's the Django girls' organizing document, there's also a conference organizer handbook by PPK, and then there's the form Python.info conference by, I think it's written by Justin Oliver, right? I might be wrong. But, anyway, the slides will contain links to all of these. The latter two are about conferences, but they're still, like, skimming through them while they talk about, like, hundreds of people in a two-day conference with one track. They still give you some ideas of what, like, running a community, like, a local community means. The two first are really amazing when you're starting from scratch. Like, even if you won't be doing a PyLadies or Django girls' community, just written through because they give you billion, billion tips. And then the last point, like, there's plenty of people like me, all the people in this conference or people in other conference or meetup groups that are willing to help you if you just ask them tips what to do with your newly built meetup groups. All right. So let's talk about the why part. The why part I found really interesting because I think it's a really hard question. Like, I can't tell you why you should build your own local Python community. I sort of hope that because the people who are here, either you just happened to stay here after the previous talk or you actually are really interested in building your local Python community. Maybe, like, maybe you as people want to do it because you think your Python is a really cool conference. So you just spent a week here. Maybe it was your first time. You feel like, oh, damn, this was really nice. And you want to replicate that one. Not necessarily as a conference, but you want to get, like, same kind of people together. Maybe you don't want to meet people who are interested in Python. I remember when we were starting, like, in Finland in 2010, back in then with my co-founder in a company I was working on, he just said, like, he has no idea who works in Python in Finland. Like, zero idea. We were two guys. We knew a few others there and there, but we had no idea. So we decided, let's build a conference. And we found, like, 30 other. And next year it was 150 other. And now we know about 200 other Python developers in Finland. Or maybe you want to create, like, a sub-community. Maybe where you are, there's already a really nice Python community or other communities. But you want to focus on something. You want to build your private issues. You want to build your own Django goals. Or you want to have a local twisted user group, where it's going to be you and Hinnak. And that's it. Something like that. Like, there's plenty of reasons. Just what I'm trying to say, like, try to have a reason. Because that helps to you to motivate. Like, if you have a sum, even a wakey idea, that motivates you a lot. So then why do I do this? Like, why have I been involved in Python Finland, Python Sweden, the Stockholm Python user group, and so forth? I think that there's a lot of good in the community, especially in the Python community, but still there's a lot of bad in it. It's a kind of a technocracy where people are merited in weird ways to give them leadership positions. And I think, like, actually to make it more diverse, actually make it more a community that accepts more people. And so that, and that you can actually, like, change the community. I think, or I feel that I need to get my hands dirty. I want to be part of building that community. And the easiest way to do that for me, it seems to be that I start organizing this stuff. And then when I'm organizing that, when I'm part of the people organizing those, I just keep tracks on, like, all kinds of potential stuff around diversity and try to emphasize as much as I can. But no matter what reason you have, I strongly suggest you to go for it. Like, if you just have some motivation to do this stuff, if you really want to have a local community running, like, go for it. All right. So you came up with a nice reason.  So how do you manage expectations? How do you deem that something was successful? Like, you want to announce your first meetup, your first, like, a gathering of the local Python people. Do you, like, count the number of people that showed up? Do you count the number of speakers that showed up? Do you hand out feedback forms and, like, ask them, was where the pinch is good or bad? And then judge from that. I think, screw all those. Back in 2009 or something, I was a part of organizing an agile conference. And we had an amazing metric for the first conference. There's someone else. Like, if you're the organizer, there's another person. It doesn't matter if you're, it's your friend or your parent. Like, if there's someone else, like, if someone actually is willing to spend their free time to come into an event, doesn't take part in the organizing part, then deem it a successful event. If it's someone else that you don't even know, then, like, then you blown all the expectations to the roof already. So don't overcommit. Don't, like, expect that your first meetup is going to be billion people. It might be you and two others or you and five others and you and one other, but you might still have amazing talks. Don't also overcommit by, like, taking a too big of a slice of the pie at the beginning. We sort of did that with Python Finland. That the first Python related event in Finland was a whole conference. We had no idea what we were doing. I think, like, 100 people signed up before got to send them invoices, so they didn't pay, pay, pay at all, like 30 of them actually showed up in the conference, and our company back in the days ended up paying the whole thingy and we never invoiced anyone. So, like, if you start too big, you might get kind of turned down. It was still an awesome conference, but a lot of work, and we clearly started from too big. If you think about the Python in Sweden instead, its origins are in the Django Stockholm user group that then became more generic like a Stockholm Python user group, and then it grew up in a conference.  All right.  What kind of resources do you need to run the stuff? First, we can start talking about the most important resource when you run a conference, which is you. Because you alone are the one that can actually make the conference happen, like, not conference, but the meetup and community kind of stuff.  You need the one person, and that one person needs to be you if you're interested in having a local Python community. Of course, if you find other people, those will help. I tend to classify the other people like in two buckets. The one bucket is the other organizers, and the other part is the, like, speakers, trainers, and stuff like that. So if you get other organizers on board, that's really great. Like, if you actually meet someone else who's willing to help you with that, that is a superb thingy. And when you get other people on board, you should have only one aim. You should actually aim to make yourself replaceable. Like, if you get other volunteers on board, like, start sharing responsibility. Don't just hug on stuff because you were here first.  A good example of this is, like, the PyStockham community, where my friend Tume, who ran it for a long time, actually won in the Green Card lottery and just left to New York. And he could just hand out the community to other people. And it kept on running on its own without him, even though he was kind of viewed as, like, a driving force behind that. But remember that when you have other people on board, they're also volunteers, so you can't force them to do anything. The only thing I usually stress to people, and I try to keep in mind myself too, is that if you work on this kind of stuff and you feel that you lack the time or it's too much or you want to drop out, like, fine, just do it, like, please don't break yourself by building, like, voluntary communities, but actually stop, but please do tell the other people. So don't just disappear, but say to the other people, hey, I feel like I'm running out of time. Can someone take over my stuff? And usually people can. So remember that you're also one of the volunteers in this thingy and there's no point of breaking yourself in it. Then you get to the other part, like, speakers and trainers and stuff like that. If you want to run a meetup, you don't need any of these. You don't need anyone to talk about any topics. Just get people together, just regular people interested in the topic, whether it's Python, whether it's other pilates, whether it's Django developers or whether it's you and Hineck with the Twisted stuff. And that's it. All right. So that was the people part. Next part, people usually think about, like, how much do you need money to run this stuff? I didn't view money and time as a kind of two currencies. That you're going to exchange one to the other.  Money will use more time and get away around. So first, the time is the tricky one.  I can always tell the same words to everyone else, like, learn to prioritize, focus on what's important.  All of a sudden, you find out that you're tweaking your communities. You haven't done any meetups because you want to build a web page where you want to build a signup form with Django. And then you heard about this new database technology and you're just cramming everything together. And then you want to maybe add that bootstrap on that and design stuff. Forget all that kind of stuff. The easiest way is just to send out emails to the people.  You need to learn to build a network. You need to find a place where you can get together. And then you try to reach out to those people somehow. We're going to talk about later how that works. The money is a thing that you don't need at all. If you look at this, it might kind of feel kind of weird that you don't need money running stuff like conferences, stuff like that, for sure. But if you're going to run a community event, you can just gather together somewhere. If it's a country like this, you can even go in a park, given that it's not raining.  If you have some money to use, then that's really nice because then you can use money to reduce the time you spend. You can use money to buy a meetup.com account which kind of offloads some of your organizing stuff and such stuff. Yeah. Anyway, money is a thing that helps you but you don't really need it. So don't feel like you need to gather a billion partners and sponsors to help you. The partners and sponsors are also interesting thingy because while they help, they're also not needed. But if you happen to be in any city that has some tech scene in there already, what I found out the best thing with partners and sponsors for meetups is that you can ask them that, hey, can we host a meetup at your place? Usually the companies are pretty willing to do that. They have a meeting room or something where you can gather together. They probably have an overhead projector if you want to show some slides and stuff like that. Or if people want to show stuff on their computers.  But also, this is kind of a bonus stuff that you don't need. All right. So we got to the point that you have a nice motivation of why you want to run a Python community. You figured out that you're going to do it all your own because you don't need anything else. And then you kind of end up with this question, like, if it's a new community, if there's nothing in there, like, how do you tell people about that? Of course, like you have your friends and stuff like that, but how do you tell the people about that? Well, there are a few things I found useful when that was especially when we bootstrap it to the finished Python community. Like, go nuts with existing user groups. Even if they're not, like, Python user groups. Just like, especially in smaller countries or smaller tech scenes or more connected tech scenes, like, if you send the PHP user group that, hey, we're going to have a Python conference, there's probably some poor soul who has to write PHP, and it's in the PHP user group just for that, but it actually likes Python. Or you just go bold and, like, send to the Python unknown, announce that, hey, there's going to be the first Python user group of our city gathering in this one town. And that's a really nifty way of, like, reaching out to people that you don't necessarily even know, but who might be still be interested in a topic. Another quite handy one was internal mailing list of companies. So if you have some bigger companies, like, I'm blanking on bigger major enterprises. Oh, well, let's say, I'll throw some funny ones from Microsoft, if you know people who work in these bigger, like, mega corporations or even, like, let's say companies of tens or hundreds of people, they usually have internal mailing lists. So you can ask those people, like, hey, I'm doing this event. Can you promote this in your internal mailing list?  And we found out that when we did this around Finland, we actually found a lot of people who didn't follow, like, Python scene at all, but work with Python and only way they heard about it was that someone sent this email to the mailing list. And now there are regulars in the meetups and also in the conferences in Helsinki. And then, of course, there's the usual stuff, like post public, post on Facebook and go nuts on the Twitter. And if you have some money and if there's existing text scene that uses meetup.com, spending a few bucks per month to meetup.com is actually pretty neat. Because if there are other meetups, they will get notifications like, hey, there's a new meetup called the local Python meetup at your neighborhood. If you don't have any other user groups using meetup.com, the value of the service is kind of questionable. All right.  So the first thing I would ask you to think about when you think about growing up to be a conference or maybe more recurring meetups and stuff like that, do you actually want to? Because that's going to imply a bit more work. That's going to imply some other stuff also. But if you're really happy with the community as it is, if you don't grow for the sake of growing, because if you have a nice community that people actually like being a part of, why do you want to grow it? Maybe you can wait for another year or maybe you can wait for half a year and see how you feel then. If you don't feel like growing, then don't try to force it to be a bigger community. Now, if you and the other were going to feel that you want to grow it, then first thing you need is the other people. It would be kind of madness to think that this, not even this kind, well, that's kind of like, let's say you would like to run like a hundred person conference. Running that alone is probably possible, but you're going to just burn out and feel really bad afterwards. So you actually need other people. Another tip I've learned is that you want to organize. You want to spin up a nonprofit. If you're going to start handling more and more money, you want to spin up a nonprofit because that gives you, not only is it usually easy in any country, but that also gives you like a sort of legal structure and makes you to actually track how the money flows and add some responsibility. But there's also a caveat in this because if you actually add like a legal responsibility when people join your nonprofit as board members, and that's going to stress them out. So there's a sort of balance you have to have. And in the end, I want to stress this, that don't be afraid to reach out to an experienced people or reach out to us who have done all the mistakes down the path when taking a community and building it to a conference and asked from us what kind of advice would we give you. All right. And in the end, like whether you grow it or not, whether you run in your community or not, just keep in mind that you keep doing it only as long as you feel like it. If at some point you feel that it's going to take too much time, then that's it. You can always step down. If it's a successful community, someone will pick it up. And amazing quote from Django girls that be proud of yourself if you're going to do this stuff because that's what matters the most. So go build your Python communities. And thank you. I think we have time for a break with them, so three. Thanks for such a nice talk. I have a question. So even thinking positively like being proud and so on, my question is about the community side. If there is some, how healthy is it? For example, there are always people like trolls or people like aggressive recruiters or perhaps someone else. Do you have some experience or how do you either approach it or just ignore it? Or is the spirit being damaged or not? And if yes, how? Thanks. So let me just recap. So you're asking like if there's people who behave badly and that kind of stuff like how do you approach it? Yeah. Well, I've been lucky enough that I haven't met anything too bad. But of course, like the stuff that conference-organized handbooks and those promote that if you're going to start setting up something that you might consider setting up like a code of contact or something, because that also gives you a nice basis of like if you get this weird behavior that you can reference this like commonly accepted rules and say like, hey, that's not right. But of course, a hard question like if you have a really bad case, like how do you solve it? Like you can have like one person poisoning the whole community. Unfortunately, I don't have any ready made answer to that. And I've been lucky enough to not be having to deal with stuff like that. I know that there are like individuals in the communities that are kind of iffy, but then like if the rest of the people tend to keep their mouth shut and just sit and enjoy the show on the side. Unfortunately, I can't give any more specific answer on that. But don't let it stop you. Like just deal when it becomes a problem. Don't be too afraid of it beforehand. No question. Just a remark. It's always good to organize yourself on an other conference. The Python user group Cologne was founded on the free open source conference in St. Augustine because we met always there and we know we are a Python user and you should just consider to find people of your town here. It's a good idea to talk if you want to make your own small community. That's a good advice. Thank you. Another question. Thanks for the great talk. I just wanted to mention that if I'm not mistaken the Python Software Foundation pays for the Meetup.com registration. I actually had it in my speaker. Apparently it blows it through it, but thank you. So yes, Python Software Foundation will reimburse you the Meetup.com for Python Meetup, not like everything. With what place for one more question? Thanks for the talk. Do you have an experience how to reach people who have children? How to make it more possible to them to get involved? In Stockholm my employee in Spotify has done a few things where we hosted a kid coding session or how to teach kids coding. So I think that's one good thing. I also want to involve the kids. If you have smaller kids I think we have had a few Meetups where we have had actual small kids involved. It's a hard question because people might react to the what I find pretty stupid is that people react to the bringing kids sometimes in weird ways while they usually don't cause any harm. And then sometimes talking more about the Nordic culture like they expect Meetups to have beer and stuff like that. So we've also tried sometimes to have Meetups completely without alcohol. Cut down these barriers that make it iffy to bring your kids in there. We haven't had any great effect on that though. So we haven't seen anything. But I don't know if the kids are big enough to take part themselves, then try that. And then maybe you could have a Python parents Meetup or something like you can drill down and you can try to make the event to be as much as people in the same state of life as the others and maybe make it a bit more welcoming so that people actually feel that they are welcome with their kids. It might be really hard if you have a common Meetup with 120-year-old males in there and the one parent. Okay, we've run out of time. Thank you, Jerky, for our questions and answers. Thank you.


Hello everyone, I once again welcome you all to MSP lecture series on interpretive spectroscopy. I started in discussion on EPR spectroscopy from my previous lecture. So let me continue from where I had stopped ESR or EPR measures the transition between the electron spin energy levels. So transition induced by the appropriate frequency of radiation and required frequency of radiation depends upon the strength of the magnetic field. As we increase the magnetic field, what happens? The energy gap between the nucleus spin steadily increases and if you go for higher field strength magnetic field, then higher microwave radiation is required to achieve the transition. So common field strength are anywhere between in the range of 0.34 to 1.24 Tesla, this about magnetic field B and then 9.5 and 35 gigahertz is the microwave region between 9.5 to 35 gigahertz is the microwave region that is used that is applied in a direction perpendicular to the applied magnetic field to perform transition of electron spins. And this is how the typical EPR instrument looks like, this is the magnetic field and the sample is kept here and the signals will go to the detector and then that goes to the plotter for plotting the spectrum. So how does the spectrometer work can be seen here, this is the source and this is the detector is there and sample cavity is here and this is the electromagnet and phase sensitive detector is here and modulation input comes from this part here. So that means the radiation source usually usually is called Klistron. Klistron are vacuum tubes known to be stable high power microwave sources which have low noise characteristics and thus give high intensity. That is the reason we use this source of microwave radiation called Klistron. The sample is placed in a resonant cavity in between the magnets I showed you which admits microwaves through an iris, the cavity is located in the middle of the electromagnet and helps to amplify the weak signals from the sample and most of the external components such as the source detector are contained within the microwave bridge control, additionally the other components such as attenuator, field modulator, amplifier also included to enhance the performance of the instrument. So EPR spectrometers typically use electromagnets and the microwave absorption is monitored as the field is varied. When an electron is placed within an applied magnetic field B naught the two possible spin states of the electron would have different energies. In the absence of magnetic field the spin states would have the same energy but the moment it is electron is placed in a magnetic field they possess two different energies. The lower energy state occurs when the magnetic moment of the electron is aligned with the magnetic field and a higher energy state where M is aligned against the magnetic field. So that means when the spin is aligned against the magnetic field we will be having here plus half. In case of NMR the one that is aligned with the magnetic field would have lowest energy that is to be plus half whereas here opposite of that one comes here. The lowest energy in case of NMR is plus half and higher energy is minus half in case of NMR. So here is opposite. So the two states are labeled by the projection of the electron spin MS and the direction of the magnetic field where MS equals minus half is the parallel state and MS half is the anti-parallel state. So this is actually aligned in this direction whereas this one is aligned in this direction here. Whereas here this is aligned in this direction and this is aligned in a direction opposite to the applied magnetic field and that is shown here and of course plus half you can see in this direction and that minus half is in this direction. And again it is always convenient to compare these two methodologies NMR and EPR. Similar to NMR EPR can be used to identify the geometry of a molecule through its magnetic moment and the difference in electron and nucleus mass and EPR is mainly used to use it for the detection and study of free radical species either in testing or analytical experiments. Pin labeling species of chemicals can be a powerful technique for both quantification and investigation of otherwise invisible factors that you cannot really detect using other methods. The EPR spectrum of a free electron shows only one line single peak whereas that of the hydrogen displays two lines two peaks due to the interaction between the nucleus and the unpaid electron. This is called hyperfine splitting so that means this electrons with spin half and minus half can also interact with nuclear spin and the lines can be further split and this we call it as hyperfine splitting. In NMR we call it as coupling spin-spin coupling. The distance between two lines is called hyperfine splitting constant A and then we call coupling constant in case of NMR spectroscopy. By using the simple 2Ni plus 1 rule number of hyperfine lines of a multiplet of a EPR transition can be calculated where N is number of spin and I is the number of equivalent nuclei. For example, for nitroxide radicals the nuclear spin of 14N is 1 so N equals 1 and I equals 1 therefore 2Ni plus 1 if you see we get three lines here. That means EPR transition for a nuclear spin equals 1 consists of a triplet. To observe microwave there must be unpaid electrons in the system that means of course only when we have an unpaid electron or a radical species that we subject for EPR study. So to observe microwave there must be unpaid electrons in the system. In a diamagnetic system or having no unpaid electrons no EPR signals will be observed as there will be no resonant absorption of micro energy that means EPR cannot be used for diamagnetic species and molecules such as NO, NO2, O2 do have unpaid electrons in ground state and EPR can also be performed on proteins with paramagnetic ions such as MN2 plus, Fe3 plus and copper 2 plus and other relevant transfer metal ions. Additionally, molecules containing stable nitroxide radicals, nitroxide radicals such as 2, 2, 6, 6 tetramethyl, 1 pridinyl, oxyl that is called tempo and di-terstributyl nitroxide radical. Now let us look into the energy levels associated with these two spins. For a molecule with one unpaid electron in a magnetic field the energy states of the electron can be defined as this one. So E equals G mu B B naught M s that equals pressure minus half G mu naught B naught. So where G is the proportionality factor we call it as G factor and M B is the Bohr magneton, B is the applied magnetic field and M s is the electron spin quantum number. The two spin states have the same energy when there is no applied magnetic field that means E equals 0 in the absence of magnetic field. The energy difference between the two spin states increases linearly with increasing magnetic field strength. So the energy gap is directly proportional to the applied magnetic field strength. So we talk about proportionality constant. What is this one? This is measured from the center of the signal for a free electron this is 2.00232 that is G for organic radicals typically close to free electron value of 1.992 2.01. For transition metal compounds large variations due to spin orbit coupling and zero field splitting 1.4 to 3.0 is observed. Now let us look into the techniques that are employed in EPR spectroscopy and of course we know this energy difference between the two states even given by H nu equals G beta B naught. This can be recorded either by varying H nu the micro frequency or B naught. Usually B naught is varied at a constant microwave frequency. So microwave frequency is kept constant and magnetic field strength is varied in case of EPR technique and here in case of X band EPR typical magnetic field strength is 3000 Gauss and the nu is 8398 gigahertz or H nu equals 9 gigahertz and in case of Q band the magnetic field strength is 12500 Gauss and H nu equals 35 gigahertz and in case of W band EPR H nu equals 90 gigahertz and B naught equals 3.5 Tesla or 35000 Gauss and you can see here in this one E versus B naught you can see steadily the value is increasing when you go from X band to W band because of increase in the overall magnetic field strength. Of course if the magnetic field strength is increasing obviously the energy required to excite change the nuclear or to observe a spin transition microwave radiation also energy also increases. So this gives a correlation between various bands and the corresponding micro frequency employed in various EPR methods where we are using X band Q band or W band. And then if you look into the spin states energy of an electron in a magnetic field is denoted by mu B naught and then of course I already refer to this equation here mu equals G B MS and beta equals E HO 4 by MC E is charge of electron and negative for electron and beta is negative for electron atomic unit of magnetic moment is called Bohr magneton and E can be simplified as E equals G beta MS B naught and then of course S can have plus and MS can have plus or minus half when MS equals minus half the expression this is the expression and when MS equals plus half this is the expression here. So this becomes something like this as I said in the magnetic field they will be aligned and opposing the applied magnetic field this is the low energy one minus half and this is the high energy one plus half and then if we consider here the corresponding energy is also M I and MS is also shown here and this is the energy gap between these two is represented by this term this is what is shown here. And a typical EPR spectra can look like here number of peaks in the absorption curve equals number of maximum or minimum in the derivative curve. So that means when you look into a typical EPR spectrum you should observe the number of peaks in the absorption curve is equal to number of maximum or minimum in the derivative curve you can consider the maximums or minimums they will be essentially same. This absorption intensity when you look into it this is absorption curve it looks like that and this is B naught and this is A versus B naught is given the first derivative of the absorption intensity is represented by this one is how you can see a derivative curve. And again professionality factor is measured from this center of the signal for a free electron G equals 2.00232 for organic radicals typically close to free electron value that is between 1.99 to 2.01 for transcendental compounds large variation is observed due to spin orbit coupling and also larger variation is spin orbit coupling also observed as a result what happens and plus zero field splitting also we come across as a result the range is 1.4 to 3.0. Now let us look into few examples here. So even number of protons are neutrons here zero so you do not observe any EPR signals for those which have no unpaired electrons for example 12 carbon i equals zero 4 helium zero 16 oxygen zero you do not see and if you have odd number of protons or neutrons integral spin for example 2H 14N 10B i equals 1 and here in case of 10B i equals 3 and 11B i equals 3 by 2 odd mass even that means even or odd combination we have these things half integral spin this is very similar this is about nuclear spin I am talking about and then if we look into different main group elements and then the isotopes we have for these and also the spin abundance and also how many EPR lines are expected is given in this table for example H if we consider we are considering 1 as well as 2 that means hydrogen as well as deuterium and then in case of hydrogen plus half is there in case of deuterium plus 1 is there so this is 0.015 percent abundance and then we can see in case of first one two lines in case of the deuterium we see three lines in EPR spectrum and in case of carbon we have 12 carbon and 13 carbon 12 carbon shows no signal I mean i equals 0 and whereas in case of 13C we have i equals half this constitutes about 1.1 percent and in case of 1 we get only one line because 2 Ni plus 1 if you take plus this whole term will be 0 so 1 will be there and in case of half we get two lines and in case of nitrogen we have both 14N and 15N 14N has i equals 1 and in case of 15N we have half that is only about 0.4 percent so we get three lines and two lines respectively in case of 14N and 15N and in case of oxygen we have 16, 17 and 18 and 16, 0 and in case of 17 we have 5 by 2 0.04 percent and 18 can be ignored so in case of 5 by 2 we get 6 lines 2 Ni plus 1 if we use here 2 into 1 we get 6 lines here and in case of 0 we get simply one line. In case of F only one isotope is there 19F i equals half so we get two lines and similarly in case of 31P also 100 percent abundant 31P isotope we get spin is half and we get two lines. In case of sulphur we have three isotopes 32, 33, 34 again 32 has spin i equals 0 and whereas 33 and 34 have 3 by 2 that constitute about 0.8 percent so in case of 32 we get 1 in case of 33 or 34 we get four lines in EPR spectrum and in case of chlorine we have two isotopes 35 and 37 both have 3 by 2 and in both the cases we get four lines and in case of arsenic we have 75 is the only 75 is the isotope have 3 by 2 value and we get 4 and in case of selenium we have several isotopes 76, 77, 78, 80, 82 and 76 is 0 and others have half spin value and that constitute about 0.76 that is 77 so we see 1.1 and 4 lines. Again in case of bromine very similar to chlorine we have two isotopes 79 and 81 both have i equals 3 by 2 and we see 4 lines here and in case of iodine again 127 we have 5 by 2 spin we see 6 lines here and similarly we can have a table for transfer metals also if you consider vanadium in plus 4 state isotope 51 and spin is 7 by 2 so we get 8 lines in EPR spectrum in case of manganese 2 plus 55 isotope 5 by 2 is the spin i value and we get 6 lines here in case of iron 3 we have 54, 56, 57, 58, 54 has 0 spin and whereas 56 and 57 can show half there is about 2 percent so we see 2 lines whereas in case of 0 we get only 1 line here and in case of cobalt we have 2 cobalt 2 59 isotope 7 by 2 we see again 8 lines here and in case of nickel we have nickel 3 as well as nickel 1 again 58 is 0 in case of 60 to 62 and 64 we constitute only about 1 percent and we see 3 by 2 4 lines there is about 0.25 percent and in case of copper 2 we have 63, 65 and again spin 3 by 2 we observe 4 lines in case of malbdenum in plus 5 state 92, 94 to 98 and 100 and 92 is 0 and in case of other one we see 5 by 2 is about 25 percent and constitutes and whereas we see 6 lines only in case of 4 percent and here tungsten also very similar 5 oxygen state 180, 182 to 184 and 186 again 14 percent has half and other one is 0 so what we see is we see about 1 and 2 lines and that is about 97 percent. Now let us look into hyperfine interaction like spin-spin splitting in case of NMR that is very similar here in addition to the applied magnetic field unpaid electrons are also sensitive to their local environments frequently the nuclei of the atoms in a molecular complex have a magnetic moment which produces a local magnetic field at the electron the resulting interactions between the electrons and the nuclei is called as hyperfine interaction because of the induced magnetic field generated at electrons and other nuclei surrounding the nuclei we are considering we see spin-spin coupling so here in a similar way this is the interactions between the electrons and the local magnetic field generated either independently or depending on the applied magnetic field so that results in the further splitting of the line this we call it as hyperfine interaction so that means here the resulting interaction between the electron and the nuclei is what decides the number of lines in the hyperfine interaction so number of lines again is given by 2 ni plus 1 n number of equivalent nuclei and i equals spin value the relative intensities of the lines is determined by the number of interacting nuclei so same thing in case of NMR as well so for example if you consider here we have half and minus half minus half and plus half here and they further interact and then nucleus with spin half to give four lines like this here so now let us look into hyperfine splitting with the different nuclei having a nuclear spin and also how many such nuclei are there for example when no interaction is there here so we see single peak for one unpaired electron when the interaction with nucleus with i equals half one nucleus with i equals half when it interacts it splits into two lines and then when this electron interacts with the nucleus spin i equals 1 this will be three lines here and then in case of nucleus spin i equals 3 by 2 there will be four lines four lines and then two equivalent nuclei with i equals half we will see again three lines and then three equivalent nuclei with i equals half we will see the four lines and then four equivalent nuclei with i equals one you can see nine lines will be there 2 ni plus 1 2 into 4 so we will see nine lines here so this gives some idea about hyperfine splitting so let me take some specific examples in my next lecture and then continue discussion on EPR spectroscopy until then have an excellent time thank you.