Today's lecture the plan is to discuss briefly sketchily role of so called timing analysis in the context of physical design flow, physical design automation flow. Most of you would be already aware of the timing analysis in particular. In fact, static timing analysis you would have used in while using the tools FPG CAD tools or ASIC tools cadence tools. Just this lecture would aim to give you some brief idea behind like at about the core techniques core algorithmic idea used in this timing analysis. The concepts notions of so called directed acyclic graph topological sort couple of notions which are only present in the algorithms of this kind. So, first of all I mean physical design as I said it is about layout right. So, what is the connection with timing analysis I mean what is the connection of timing analysis with physical design. First of all most importantly you see recall that we I mean I mentioned that in the automated process of layout generation lot of importance is given to minimizing the wire length right. So, why I mean first of all yes might I remark that must I remark that if wire length number of wires or length of wires is very large that would kind of lead to more complexity for routing. That is if route if you have want to route within some limited area then of course, it becomes harder to route if you have very long wires if wires are running very long from I mean and so on. Of course, number of wires is going to be same as number of nets, but like you know if you have done a poor placement then it could possibly mean that a lot of wires are running very long from one side of the chip to other side. So, that is why while doing placement one like one of the primary goals of good placement is to ensure as low as possible total wire length. Of course, until one does one does routing one does not really exactly know accurately know what wire length is, but after placement one can get some estimates of how much the wire length would be and based on the estimates the placement heuristics would be would be guided to like to sort of make a better placement and so on. Yeah, so why was this wire length crucial? So, in particular suppose this interconnect delays the wire delays were insignificant or negligible then would be would be have been worrying so much about the wire length. Of course, wire length would mean like you know complexity of router it will be more headaches for the router, but the in terms of delay of timing the wires the length of the wires would not matter if the delays of interconnects were extremely insignificant compared to the delays of the gates themselves or the modules or cells themselves. So, in this case wire length would not be so crucial, but definitely that is not a situation of course, to some extent it will be crucial in terms of area optimization, but not in terms of timing, but like reality is that this wire delays are significant right are becoming increasingly more significant. So, they have to be kind of given good attention to. So, in this sense like because timing is very important and estimates of timings are important one would get an idea of what would be the acceptable wire length how I mean like we should not kind of I mean and so on so forth. So, also like certain tools or the so called static timing analysis would let it would tell you about would tell a designer about or that like automation tool about what is the timing critical portion of the net list and if one gets an idea about that then one the in a manual or automated fashion that timing critical portion which could involve some gates or which could involve some wires those gates could be upsized resized to improve the delays the inertia or the wires could be widened. So, as to reduce it the resistance or some appropriate buffer insertion would be done to reduce the delays along the long wires in the critical timing critical portion of the net list. So, net list restructuring can be done in case one gets a timing estimate. So, time like as accurately as possible or like as quickly as possible. So, one would have to kind of this will not be one step procedure because every time you make some tentative placement or routing layout decisions you have one like you know feasible kind of routing, but then you might want to improve upon it and then you look at a timing and identify the critical portions try to improve their hoping to get overall improvement in the timing and so on so forth. So, this is how the timing analysis tools will be interacting with the layout generation tools. So, many of this route placement routing algorithms would actually be getting a bit of feed quite a bit of feedback from the timing analysis every now and then. So, we aim to look at some core notions in this timing analysis with the help of examples illustration. So, since as I mentioned since wire delays are significant therefore, it is you know interest to have a high performance or optimum or close to optimum wire length or appropriate sizing. And other point I mentioned is that the timing analysis helps identify the critical portions of net list and this can be improved in various ways as I said like by upsizing resizing the gates. So, as to reduce the inertia like or like you know improving this interconnect or inserting buffers at appropriate locations many of this problems have been studied algorithmic for the algorithmic solutions. So, core notion in timing analysis and also one of the simplest to understand and get develop some good intuition about for more difficult concepts and problems. So, that is so called static timing analysis. So, this static refers to static means not dynamic means is something that does not really put any give any specific emphasis to the runtime behavior dynamic behavior more about most. So, this static means static analysis means mostly based on static information not runtime information. So, that is the delay estimate worst case delay estimates actually at the runtime the delays may not be as bad as the worst case delay estimates and also the topology that is graph representation or graph abstractions. By looking at topology and the worst case delay estimate one can fathom lot one can get a lot of I mean lot of useful information about timing requirements and timing optimizations and which will help in the automation I mean I mean hoping to arrive at good high performance layouts placement routing. So, when you hear about static timing analysis you will automatically I mean hear about the terms like a t which stands for actual arrival time r a t or some other notation for like mnemonics for this required arrival time. So, these are the times arrival times of signal transitions. So, I will will obviously elaborate with the help of examples. So, things will be very clear and based on these two concept there is a notion of slack which is quite important slack. Slack will be r roughly speaking it is a difference between r a t and a a t of individual nodes. So, in the timing analysis we will interestingly we will be kind of dealing with will only some kind of combinational. So, if you start looking at timing analysis algorithm many of them seem to be just talking about combinational circuit. So, I mean what does it mean? So, does it mean that there these things apply only to very restricted situation of purely combinational designs? No, in fact this combinational portion of any design is the really the core of it in terms of the logic part of it. The other than in any typically any synchronous sequential circuit there are going to be flip flops and there is going to be combinational logic portion. The flip flops are for the purpose of storing the flip flops are being used for storing the data or the state of controller or the state of the computation data path state and combinational logic that is the one I mean is the portion of the circuit which is actually like you know continuously working continuously kind of updating its outputs in the response to the changes at the inputs. So, that is the combinational part of the sequential circuit is the one which is which is kind of trying to compute the next state of computation next state of controller and the next the next values of the variables the data items and the flip flops are only like you know holding on to the state or the state of computation or the data current values of the variables the data items and so on so forth. So, for the timing analysis the flip flops really want I mean and we would not have to worry about the flip flop so much. In fact, at an abstract level we will kind of be cutting the circuit at a flip flops and once you cut this big sequential circuit at a flip flops if it is a well designed sequential circuit then what will be left with is obviously purely combinational, but more interestingly there would not be any feedbacks within the combinational portions. If at all the circuit obviously will have feedback there will be some like you know next state depends on the current state. So, that means and the next state is going to become the current state in the next clock cycle. So, there is a role of feedback in sequential algorithm sequential circuits, but every any time there is a feedback then that feedback path will include necessarily include a flip flop one or more flip flops. So, if you cut at the flip flops you are going to have all the feedbacks removed and whatever the purely combinational circuit that is left is feedback free. Of course, there is nothing wrong really in having feedbacks in the in a circuit with which has just combinational gates, but those kind of feedbacks can give you latches, can give you rise to memory elements or can give rise to oscillators configurations. So, there is no need like for designing latches and oscillators in a like you know in that using just they would be one would in large designs one would typically make use of them as black boxes or as well designed components and the combinational gates would be purely used for the in the feedback free manner for generating the next state logic or the output logic milli or more output logic. So, one of the things about static time and analysis you will notice is that this example the circuits that we will be dealing with are will be shown to be purely combinational and without feedback also. So, again I am emphasizing cautioning that like feedback free is not the absolute necessity in designs especially feedback free I mean, but like you know well designed circuit the combinational part did not have feedbacks. If at all feedback is meant for holding like you know like designing a memory element like a latch then you could as well use a well designed latch in that particular implementation technology. And it helps a lot to like you know assume that there are no feedbacks that makes the algorithm design process analysis process very smooth and efficient interesting and efficient. So, I will take an example right away which will be kind of exploring to show some concepts. So, here is one circuit I have some labels or notations over here about a moment I will explain what this mean all right yeah. So, this is again an example courtesy here is 0.15 the book VLSI physical design from graph partitioning to timing closure by Cahang, Linig, Markov and who Springer I think it came out last year ago or couple of years ago may be good book like fairly elementary introductory and well written of course, there are other books, but I chosen to use examples because this is not a core course like a full flash course on VLSI design automation just for the overview of some concepts I have try to keep the matter simple examples and notions simple simplistic overview essentially. In this particular example here we have a net list again what you notice is that there are no flip-flops here it is purely combinational gates and also what you notice is that there is no looping there is no feedback here there seem to be this ABC we can regard them as they are there to be regarded as inputs and F is the only output of course, you could have multiple outputs and many more inputs much more complex such combinational circuit the annotations the labels here 0 0.6 they kind of they represent the arrival time of signal transitions at this inputs. So, you know like from somewhere like with respect to certain synchronizing time let us say positive age of a synchronizing clock in the system this signal becomes stable at 0.6 nanosecond after the rising age of the clock this signal is let us say immediately stable and so on take it with the pinch of salt this things need not be 0 then the labels on this wire segments are like they indicate the delays of this interconnects the labels on the gates like this is the this is then and gate and this label name is wire and this quantity in 2 indicate the delay the worst case delay of this particular gate and this is the inverter with delay 1 this is or gate with delay 2 and gate with delay 2 and these are the wire delays 0.2 0.25 nanosecond 0.3 nanosecond 0.1 nanosecond 0.1. So, you do not worry too much about you know this net is being driven by this it is going here it is going here. So, like you know what is the delay of this common portion what is the delay of this portion one can study at that level also anyone studies the l more delay R C trees, but right now just assume that this 0.1 means that it is a delay the worst case delay for the effect of signal transition at this point to reach or this particular pin of this gate and so on. So, 0.3 is a delay between signal transition here and a corresponding signal transition over here. So, and let us assume that for the purpose of so called pessimistic static timing analysis the whole circuit all the elements of circuit the wires and gates are behaving in the worst case fashion that is all these numbers that we are showing which are worst case estimates they actually like you know the signals are stabilizing or like you know making transitions at the like with the worst case delays. So, things might turn out to be better than that in the at the run time and those things are also studying this subject, but that will complicate our discussion a bit. So, based on this feedback free combinational circuit which is which would have been obtained like you know out of a general kind of sequential circuit which has this kind of structure there is a controller a controller is basically a set set of trip flops which maintain the state and combinational logic which will generate the next state based on the current state this trip flops maintain the current state and these are clocked and this combinational logic is computing the next state which is to be loaded into the flip flops at the beginning of the next clock cycle or the end of the current clock cycle also this combinational logic is also influenced by a primary inputs or inputs from some other source not inputs from this flip flop. These are considered to be primary inputs of this particular controller this is the controller and then there is a data path. So, the data path might have some flip flops all by some combinational logic some another set of registers followed by and so on. It could be this is kind of linear picture I drawn just for I mean the in general data path can be far more complex there will be registers combinational logic all there will be multiplexers and so on. But again with the data path you see that there is there are flip flops and there are combinational logic clouds controller also has area of trip flops for maintaining the state and combinational logic for generating the next state and the outputs this outputs of this controller go to the data path and so on so forth. We are aware of that we are not going back I mean they can you know leading the discussion back to FSM plus data path. But the important like here we want to I want you to identify that this combinational logic is the one that we have to focus on for static timing analysis. Just cut this flip flops or like you know remove them from the picture what you are left with is possibly disconnected set of combinational logic clusters or clouds we can think of them as which are feedback free like in this example this circuit is feedback free of course this is must be a very small part of a very small sequential circuit if at all but in general it could be hundreds of thousands or million or tens of millions whatever very big like not everything would be one like you know monolithic combinational circuit there could be lots of separate parts of it and they can be after partitioning they can be separately identified separately So, partitioning has one big role in this timing analysis also. So, this was just a picture of a general sequential circuit which will have controller data path. So, highlighting which portion is the one that we are going to look at in the static timing analysis this combinational logic. So, the notion of timing critical this is like vaguely remarked that the timing analysis static timing analysis is going to compute this so called actual arrival times and required arrival times which will be illustrated on this example. But after doing that and after computing the slacks this tools the analysis will identify the timing critical portion and in particular this critical path is an important like concept which most of you all of you will be very well aware of critical path is the one which is going to like which is important because that is the one which is going to like which has the maximum delay from any input to any output and which will like influence the maximum frequency at which the sequential circuit can be driven. So, that will be influence the speed of your implementation. So, critical path is the path which has max delay from any input any output. So, how is critical path identified? So, this the state of our timing analysis has much more ability than just identify critical paths, but it will help to begin with like you know understanding how critical paths are found and like that is a core notion. What kind of algorithmic ideas model the graph models graph algorithms get used that gives you some kind of insight motivation to study the next level more advanced concepts. So, I will just focus on the basics. So, this concept of actual arrival time. So, actual arrival time at U say where U is a pin of a gate say it could be output or input pin. So, this actual arrival time at a U at a pin U say U is this is a gate and this is say U. So, how is it going to be defined and what will be what will determine this particular actual arrival time which is the arrival time of the signal transition. The signal transitions are happening at the primary at the inputs and like you know because of the delays of the wires and delays of the gates the corresponding signal transition will happen at certain time and the time at which that signal transition occurs assuming that all the gates and all the wires are working are acting in the worst case fashion with worst case delays. The time at which this corresponding signal transition occurs and after which the signal this signal at U achieves its correct value is the actual arrival time. So, this will clearly be like you know based on say this is v 1, this is v 2, this is v 3. So, if these are the signals which are at the input of this then this will be max of a a t in this example a a t of v 1 plus what the delay of this gate say the gate g comma a a t of v 2 plus delay of g comma a a t of course, I can say it will much more elegant fashion, but anyway let us see how our thought ideas develop. So, clearly this right. So, it will be influenced by the one by the pin which is kind of which has the latest or actual arrival time you know. So, if this particular input might like becomes stable very early, but it will not like you know it would be of no use if some other input is going to arrive much later. So, the one which is going to arrive input that is going to arrive at the latest time instant is going to define it is going to determine the actual arrival time at the output of this gate. The delay of this gate is also included that is common for all these cases. So, it looks like you know it hints at the fact that this actual arrival times are recursively defined and that is the main key of things. Similarly, the notion of r a t required arrival time is also going to be recursively defined and I will just come to that in a moment. So, like to do this recursive computation recursive computation of a a t's and similarly of r a t's. This recursive that this recurrence relation is with the help of dynamic programming of I did not mention this, but this if one is interested one can like look at this as note that these are very interesting important examples of dynamic programming like otherwise one can think like you know one can also invent this ideas or discover this ideas without like you know up into this sophisticated notions of dynamic programming very intuitive concepts. So, this recursive computation with the help of dynamic programming or otherwise is can be efficiently done done in iterative fashion. By that I mean like we are going to compute the a a t's at all pins of combinational circuit which is which does not have feedback. We are going to start at the inputs and then like iteratively start computing the like iteratively compute the a a t's actual arrival time is at different pins you know in certain order the pins or gates will be processed in a clever order clever, but natural and simple clever that I do not mean it is going to take you effort to it is a clever idea like so called topological sort clever simple natural. So, I do not want to clever to necessarily mean that it is something very hard to further or understand very simple idea. So, in some kind of topological sort again the word I mean it is one of the very simple notions in algorithms and quite likely you are already familiar with it is going to be used to like you know visit this nodes the gates or pins in certain order and compute the a a t's and similarly for r a t's may be the order is order would be different over there, but the idea is the same instantly like I think I have missed mentioning once small point the one of the reason I was like you know bringing your attention to the the flip flops and like you know while talking about while in that you will see the we will see the focus on combinational circuit although there is no most I mean genuine like digital designs will have flip flops the flip flops are for the purpose of storage combinational logic is for the purpose of computing the next state computing doing the data processing and computing the outputs. So, what are the the so called inputs to this combinational logic and outputs from the combinational logic of course, some of the inputs to the combinational logic are coming from the external world and some of the outputs are going to the external world. So, they are primary inputs and primary outputs, but other than that we should regard the outputs of flip flop also as kind of secondary input to combinational logic like this output of this flip flop would can be regarded as a as an input to this combinational logic and to differentiate it from the input coming from external sources I will call it secondary input. Similarly, output of this combinational logic is going to is not going to the external world, but is going to like over here it is going to flip flops again. So, this is to be regarded as a secondary output of this combinational logic. So, should be in some sense regarded as an output. So, and that is of course, crucial because this notion of critical path that I mentioned which you are already familiar with which says it is a max delay path from any input to any output, but that any input any output include not just primary input primary output. So, this secondary input secondary output which are respectively the flip flop outputs and the flip flop inputs. So, one says loosely like critical path is the max delay flip flop to flip flop path, but I mean also it should include primary inputs and primary outputs. So, basically any input output path where the input outputs could be either of the primary kind or the secondary kind. So, I am sorry for the digression, but we will come back to. So, we are just like you know going to get some more idea about this actual how to compute actual arrival times and required arrival times and I said there like at a sophisticated level one can think of all this as very good example of so called dynamic programming very important idea in the algorithms as well as in particular VLSI CAD has many applications of this. And this notion of topological sort some kind of ordering anyway this is what you will get to study when you do that course on design automation or course on algorithms data structures. So, a graph modeling is preferred one can do this on the net list itself, but like to make good use of standard packages standard libraries for implementation one should like and do a clean analysis clean algorithm development and use of libraries like the abstractions are very useful. So, a graph modeling and again there is no just a single way of single particular way of modeling things by a graph. So, that circuit that I had drawn this one I am going to model it as a graph. So, I will just draw the graph first this there are remember like we call that there are a b and c there are this primary inputs or it could be secondary input inputs and there were labels here 0 0 and 0.6. So, there were those this labels were denoting the arrival times of signal transitions at this input. So, I am going to have some kind of dummy source and arcs of this kind edges directed edges of this kind and this I am going to label with this. So, this is going to mean that a signal transition arrives at this input c at 0.6, but at a and b it is there from time 0 itself. Then a is connected to input of the gate y. So, I am going to represent y by one node and I am going to label this by 2 remember that y is a and gate with a delay worst case delay 2 and this connection this wire from a to y has delay of 0.15. So, that I am going to represent it as by this directed edge because this is the direction in which the signal travels is 0.15. Similarly, I am going to draw the rest. So, b b drives this inverter x which has delay 1 and I think I forgot this this was 0.1. So, 0.1 this is x with delay 1 output of x drives y as well as this gate z. So, z is like z is a or gate with delay 2 z is driven by c as well as by x the length of this delay along this wire from c to z is 0.1 this delay is 0.3 like you know do not go by the lengths they could be because of the width of the interconnects or the cap and so on and some other factors. This also drives y with delay 0.1. So, this 0.1 and 0.3 correspond to this x driving this pin of y with after 0.1 delay and this with 0.3 delay c driving z with 0.1 delay. So, let us complete the rest of it like there is another gate called w which is an and gate with delay 2 which is driven by y delay of the wire is 0.2 and also driven by z this delay is 0.25 and this is generating as shown in that picture like it is going to output and the wire connecting the output of w to this output f is of delay 0.2. This is your f. So, I have introduced this dummy source for the purpose of kind of capturing this arrival time information at the inputs a, b, c. So, a, b, c are not really gates there is think of them as some kind of input pads or some input terminals at which signal transitions are arriving at certain specific time time 0 time 0 and time 0.6. So, this all the information has been captured here and it should you should convince yourself that the like this will suffice to like you know know the essence of the timing information the input information that is delays of wires and delays of gates. Now, we can start building up this propagating actual arrival time information and similarly the required time arrival information. So, arrival actual arrival time at a, b, c are the points 0, 0 and 0.6. So, it is going to be bit of a clutter here. So, I say a, a stands for actual arrival time a at this is going to be 0, a at this node is 0, a at this node is 0.6. Sorry, actually yeah that is enough because signal comes here this nodes are not really gates or they can think of them as simple red thumb dummy gates with 0 delays. So, at the output of this like over here we can we know that the arrival time is 0, 0, arrival time is 0.6. Now, based on this which are which of this for which of the other nodes their outputs we can find arrival times the signal is arriving here at time 0. So, based on this can we find can we decide what would be the arrival time of signal at this output of y not exactly I mean we need we know this information this 0.15 plus 2, but it could this arrive signal transition here to a final value would depend possibly it could depend on some other input path you know. For example, it could depend on signal going along this wire getting delayed here getting close like converted and another delay. So, this would have lead to 0.1 plus 1 that is 1.1 plus 0.1 1.2 plus 2 3.2. So, just knowing this this alone would not give this knowledge 0.1 1.2 will not give us the actual arrival time here to know the actual arrival time at this point you will need to know the actual arrival time over here and over here to know this we will need to know the actual arrival time of this and so on. So, we have to kind of process this visit this in certain order. So, before visiting y we should visit x simply because y depends on x. So, this so called topological order is ordering of this gates and so on like nodes gates or nodes as in graph in such a way that we do not we visit a node only after we have visited all the nodes on which it depends. So, we will visit y we will process y only after we process a and we process x because y depends on a and x. X will process we can process as soon as we know information about b. Similarly, z will process only after we have process x and we have process c. C would have process quite quickly x we would have once we have process x and a b c then we are eligible to process y and compute do a computation at z. And once we have computed at z and we have got a a a t also at y then we can go on to computing this at f or the output of this w and so on. So, we have to go in this particular order and that is that topological that is an example of so called topological order that is simply visit the nodes in a manner such that you do not visit something before having visited all the nodes that it depends on. So, topological order here will be first we will do x because x does not depend on once we have done a b c x can be done like immediately, but y neither y nor z or not w can be done because they will depend on x. So, what will be the arrival time of the signals transition at the output of x a at this point will be see that because of this path 0 plus 0.1 plus 1 1.1 there is no other way x will be signal transition at x will be output of x will be influence. So, it is 0 plus 0.1 plus 1 1.1 so a is decided over here now a is decided at this point and at this at the output of x now because of the signal has made a transition here to its correct value after another 0.1 there will be a stable value available at this input pin of y and at this input pin of y the value stable value is available at 0 plus 0.15 that time. So, then there is a further delay of 2 nanosecond let us say at this gate y. So, at the output of y now we are ready to compute a or a actual arrival time and that will be max of how much 0 plus 0.15 plus 2 that is 2.15 comma 1.1 plus 0.1 plus 2 that is 3.2 right 1.1 at the output of this plus 0.1 plus the inertia of this gate that is 2 that is 3.2. So, this will be 3.2 similarly a over here can be computed because it is going to be max of 1.1 plus 0.3 plus 2 comma 0.6 plus 0.1 0.6 plus 0.1 plus 2 which is equal to how much 1.4 3.4 right and similarly what will be the actual arrival time at the output of w I will just confirm I will work it out yeah what will be the actual arrival time over here yes a will be this is 3.4 plus 0.25 plus 2 that is 3.65 plus 2 that is 5.65 and from this side it is 3.2 plus 0.2 that is 3.4 plus 2 that is 5.4. So, maximum is 5.65 and at f will be a will be 5.85 5.65 plus 0.2. So, it is a very simple calculation very easy to implement as an algorithm in any language like it is just looking at topology we define figure out an order in which this node should be processed all the labels are indicating all the information that you need the delays of the wires delays of the gates and based on that in a systematic in a very linear efficient time you can get all these values actual arrival times at outputs of all the nodes all the gates in this particular design. So, now that means we know that sorry we know that the signal will as a result of signal transitions arriving at a b c at this given times at time 5.85 we will get a correct value of signal f as a result of I mean correct combinational value of at signal f. So, now the related question is like if this is the actual arrival time what like you know what would have been the required arrival times of the signals at different nodes like you know should is it was it really necessary that at a the signal must should have arrived at time 0 was it really necessary that at this c the signal should have arrived at 0.6 could it have been that signal would have been allowed to arrive a bit later. So, what are the required arrival times at the nodes if now we know that we are being able to receive a receive a value correct value at time 5.85 and that is because of this assumptions that we have made about arrival times here these are these are the actual arrival times, but what would be the required arrival time. So, that we meet a certain target required arrival time at the destination at the sink at a target. So, that is a dual kind of opposite kind of question and as your intuition would be telling you that it would really amount to making a backward pass here we are going in some kind of forward direction of the signal flow. We process a node only after we process all the nodes which drive that particular node. So, that is we are going in the direction of the signal flow if you go from the target in the direction backwards reverse direction of the signal flow we will be able to similarly compute this logic like intuitive notion of required arrival times and why is that required arrival time useful or interesting it is because we get to know like whether we have been a bit too like you know too pessimistic and like you know trying to generate the signal very early. We could have afforded a bit of delay the signal might have at certain time it pins the signal might arrive later and still we will have our computation or like you know our result available at the required time say at 5.85 definitely 5.85 is like you know is the best that you can get because these are the actual arrival times of signals. But could the signals have arrived late supposing we get an information that signal can arrive at node y sorry node a at time 0.2 and still we will be able to get at point at time 5.85 correct value. If the required arrival time at a small a is to be is found as 0.2 then we know that there is some kind of slack over here 0.2 that means we could have the some circuit that is driving generating this signal transition here could be made could we can afford it to be less efficient in terms of delay and generate this signal transition a bit later ok. So, having computed the arrival times we know that a here has been found out to be 5.85 ok. Now, say we say that this is also the required arrival time r at is also 5.85 ok. We require this as like you know as has been given by this actual arrival time we also. So, we let us say we require it exactly at this time only like you know by this time we require it then if you do a backward analysis to see what are the required arrival times of signals at the other nodes. So, here we want it to be at 5.85 then over here over here the required arrival time will be clearly 5.85 minus 0.2 that is 5.65 ok. Then can we immediately go on go back to finding the like you know guessing the required arrival time over here no right because it would the required arrival time here would like you know intuitively depend on naturally depend on the required arrival times here and so on. So, we have to go patiently in certain kind of opposite order in a direction opposite to the signal flow that is in this direction and process nodes. So, w is known. So, we hope to find the required arrival time here and required arrival time here. So, how much say at z this is over at the output of the gate w it is 5.65. So, over here at the output of z will be this is a required at 5.65 there be a 2 because of the 2 nanosecond delay of this and 0.25 nanosecond delay of this wire over here at the output of z we must have we must require the signal transition to take place at 5.65 minus 2 minus 0.25 that is is 3.4 again ok. It just happens to be same as a like you know we will like understand the reason of this for this phenomenon that wise turned out to be the same that bit later over here now over here. So, this is 5.65 we require the signal there is a 2 nanosecond delay and the 0.2 nanosecond signal. So, we require this at 5.25 sorry 3.45 yeah 3.45 like 5.65 minus 2 minus this is 5.65 minus 2 minus 0.2 right 3.45. Can you compare it with the actual time here at this output of the actual arrival time was 0.3.2 over here it was 3.4. Somehow may be a coincidence we could, but like actually it is not over here we have found this required arrival time at the output of z to be 3.4 which is same as the actual arrival time at the output of z which is 3.4, but the 80 at y output of y is 3.2, but the required arrival time at the output of y is 3.45. So, there is a discrepancy here and there is a like you know thing matching over here anyway. So, we will just you would have probably guess the reason for that also. So, this is going to tell us something about critical path ok. Now, having known the required arrival time at y and z we will can compute a required arrival time at x and that will be how much will that be that is interesting. So, r a t at x at the output of x by x I mean that output of x is going to be you can like you know check for yourself. I mean I encourage it to I would really encourage you to kind of think about it on your own because all these are very intuitively natural concepts even though you may not have done a formal course on this subject or algorithms.  So, 1.1 is going to be 1.1 once again you notice that this is matching this particular arrival time of 1.1 over here is again it is not a coincidence. So, let us in fact wherever we find things matching like you know 5.85 and by design I have chosen this r a t also to be 5.85 and then r a t here was 5.65 which is matching this actual arrival time of 5.65. So, let me like you know color it differently. Similarly, here r and a are matching 3.4 see that 3.4 here and 3.4 and here also they are matching. So, from this let us quickly compute the remaining once we know the r a t here r a t at a is known and that will be r here will be 3.45 minus 2 that is 1.45 minus 0.15 that is 1.45 minus 0.15 is 1.3 sorry am I making a mistake 5.5 yeah ok here here r a t will be a please compare it with and it is obvious to note that it is like that here a t was 0, but r a t is 1.3 that means you know we got the signal here a bit too early we did not even have got a signal transition here it is time 0 could have got it as late as point 1 time 1.3 and still we would have been able to make it that is a meaning of it right yeah. So, now over here this is 1.1 this is 1 and this is 0.1. So, it is actually 0 that is interesting it is exactly matching the actual arrival time over here and that is why I will like you know kind of mark this. So, I will mark this mark all the things along which I am seeing things r and a matching. So, and over here it is going to be 3.4 minus 2 minus 0.1 that is 1.4 minus 0.1 that is r is going to be 1.3. So, here a was 0.6, but here it is now it is 1.3. So, they are not matching. So, now based on that r at this will be 1.3 minus 0 or minimum of that minimum of 1.3 minus 0 or 0 minus 0 or 1.3 minus 0.6 then that is clearly going to be 0 a was also 0 because this is kind of dummy source at arrival at some signal is at time 0 here and after 0.6 it arrived here and so on. So, this also I will mark it. So, what I have marked over here are this like you know is a path along which I have seen this r and a matching provided this r at t assume that I required the signal transition at f to be same as the time at which it actually arrives. So, r at and a at were matched over here and based on that I retraced and computed r at and along this path may be along some other path also it could have been matching, but definitely along this path things matched.  So, in fact, this is the this is an example of a critical path which is timing critical in the sense that if something if this components here the gates here are like you know if they are designed to happen to be poorer then the timing will become worse or if on the other hand if they become better marginally then actually timing can improve it is not necessary that they become much better the timing improves that much better like you know, but there is sensitivity to that. So, the timing of performance of this is going to be sensitive to the timing performance of the individual the wires along this path the gates along this path. So, this is what is considered to be critical path and a lot of attention is given attention can be given to this critical path things can be resized restructured the interconnects can be made more like efficient in terms of delay buffers can be inserted along longer wires of this kind 0.3 and things can be improved and design will improve. So, this is what roughly what roughly what happens in like timing analysis after doing this AIT RIT calculation the difference is calculated wherever there is a discrepancy that means there is a slack things could have been worse, but there is no slack that is along this RIT and AIT are matching the slack is 0 that is a critical path and that is helping that helps us to identify the critical portions which can be improved for better timing or and effectively better layout. So, this is how the timing analysis can give feedback to the layout automation algorithms let me just see yeah. So, I did not show the slack, slack were just the differences between the R and A. I am not describing this formally I am just wanted to bring out the intuition and the insights it is something quite simple. So, you will most encouraged to read of the book the book by Cahang Linig, Marko and who that title various physical design from graph algorithms graph partitioning to timing closure. The in fact the last chapter of this book is on timing closure bulk of the book is about physical design and last chapter tells you how timing analysis interacts or what kind of role it has in the context of physical design automation and so on. So, this is there are some more interesting ideas there is the timing analysis again is a big subject by itself with lot of interesting research contributions it should appeal to you are most encouraged to take a look at it and with help of a specific course on various I can.


Good morning. I will start my today's lecture. Before doing that, I will just briefly recapitulate the points that we discussed yesterday. We did a single phase inverter, then we started discussing the three phase inverter. We discussed voltage source inverter, wherein the input voltage is the inverter is held constant by a capacitor. In a voltage source inverter, in each leg, one device is conducting at a time. At any given time, one device in each leg is conducting. Having turned on the device, if I allow the device to remain in that state for 180 degrees, line-to-line voltage waveform has a pulse of 120 degree direction. The magnitude is the supply voltage V dc and for the remaining 60 degrees, the output voltage is 0 in the positive half and the negative half, it is just the opposite. So, if I take the Fourier series of this waveform, the harmonic spectrum is going to be 6 and plus or minus 1. If I want just a 50 hertz supply, the predominant harmonic is going to be 250 and 350 hertz. 11th is going to be 550 and 30th is going to be 650 hertz. When it comes to a star connected load, the phase voltage has a 6 steps waveform. So, hence the name 6 step inverter. In order to reduce the total harmonic distortion, what we concluded was instead of having one pulse of 120 degree direction in the line-to-line voltage or having turned on the device allowing it for 180 degree, we have a poor harmonic spectrum. Instead of having one pulse, I have a large number of pulses. So, if I do that and if the load is inductive, my current waveform is going to be approximately a sinusoid. Let me tell you one thing. Voltage is made up of large number of pulses, but the load is inductive. I can have a current power which is approximately a sinusoid, but then if you want a purely sinusoidal supply, a voltage source as well, voltage waveform should be sinusoidal, then I need to use an LC filter at the output of the inverter. I will repeat. If you want a voltage waveform also should be sinusoidal, then we need to use a separate LC filter at the output of the inverter. I told you there should be a large number of pulses in one's in half a cycle. How do I or when do I turn on and off the device? So, for that I need to use a PWM strategy. The most common PWM strategy being a sinusoidal PWM technique wherein there are three sinusoids which are displaced in time by 120 degrees. The frequency is equal to the 50 hertz provided if I want a 50 hertz supply is compared with a high frequency triangular waveform. Both magnitude and frequency of the triangular waveform is held constant. The frequency of the triangular waveform determines the switching frequency and therefore, the frequency of the predominant harmonic. So, this frequency is fixed based on the power level. At low power levels it could be high and as the power level increases, we need to reduce the switching frequency. The magnitude of the output voltage depends on the magnitude of the sinusoid or the modulating wave. If I want to have a constant magnitude, I need to keep the magnitude of the sinusoid also should be held constant. This is sinusoidal PWM technique. Second one which is very popular is the space vector PWM technique. What is a space vector? As a three phase sinusoid can be represented by one vector what is known as a space vector. In a two dimensional space if I plot, it has a magnitude as well as under angle theta. At any given time, if I know the magnitude and theta, I can get d axis and a q axis component and if I know the d axis and a q axis component, it is possible to determine the instantaneous value of V a V b V c. And we found that in a three phase voltage source inverter, as a three phase voltage source inverter, there are three legs. At any given time three devices are on. So, there are eight possible conducting states, two of which are zero voltage vectors in which all the three upper devices either they are on or off. So, in both the cases, the magnitude of the space vector is zero and the angle is also zero. In other words, we are at the origin. The remaining six vectors are known as the active vectors and we found that they occupy the six vertices of an x again. See here, V 1 vector is obtained by turning on phase a alone and the lower devices of phase b and c are on. See, right now I am monitoring only the upper devices conducting state of the upper devices. The upper device of phase a is on here in addition to phase a, phase b also turned on. And if I see from the difference between these two vectors is the conducting state of only one device has been changed. Conducting state of only one device is changed. See, from V 2 to V 3, I can go by changing the conducting state of one device.  And from V 3 to V 4, phase c is turns on, nothing happens to b and a. V 4 to V 5, b turns off, nothing happens to c and a. And 5 to 6, a turns on, nothing happened to c and b. So, from one vertex and other vertices can be travelled just by change the conducting state of one device. So, if I do that, in one cycle is completed in 6 steps. In other words, it is the 6 step operation itself. The harmonic spectrum is going to be same as that of the conventional square wave inverter. I said we have to decrease the total harmonic distortion. Therefore, we need to have large number of pulses. Somehow, I have to move in a very smaller steps. In other words, I need to discretize the given sinusoid or I have to digitize this given sinusoid. What I will do is, there is a sample and hold circuit. Every time it samples the sinusoid and that values held constant for a sampling time T s. Somehow, I have to realize this, the variable magnitudes using the space vector PWM type. Now, the important result I formed you was, if the 3 voltages are sinusoid, then V s can be represented m into e to the power j omega t, where m is the modulation index, omega is the frequency of the output voltage. And locus of V s is circle. Now, how do I digitize or how do I realize this? Here, the magnifying V by f or if I have constant frequency 50 at supply, I need to keep V constant. The philosophy is the space vector lies in between any two active vectors. Then these two active vectors and 0 vectors are used to synthesize V s. If the vector lies in sector 1, I need to use only V 1 and V 2 and 0 voltage vectors to realize V s. How do I do that? Assume that it lies in V s. I told you and V s is assumed to remains stationary for T s. T s is nothing but the sampling time. When this V s is flowing in a coil, it produces some flux. The same change in flux I should realize using V 1 and V 2. So, what do I need to do or what do we need to ensure? There should be a volt second balance. At any given time, if V s is making an angle theta, magnitude is V s. So, volt second of that is V s into T s. T s is the sampling time. That should be equal to V 1 into T 1, where T 1 is the time for which V 1 is applied, V 2 is the time for which or T 2 is the time for which V 2 is applied. These are the two active vectors and the remaining time I will apply the 0 vector. Since the voltage applied is 0, there is no change in the flux. So, if I satisfy this condition, I have realized V s. How do I ensure that this condition is satisfied? What I will do is I will resolve V s along x axis and y axis. That is V s into T s into cos theta is the x axis component of the space vector. V s into T s into sin theta is the y axis component. So, right hand side of the x axis component is V dc into T 1, where V dc is the magnitude of V 1. V 1 is along x axis. It does not have a y axis component and it is on for T 1. V 2 vector makes an angle 60 degrees. So, the x axis component is V dc into cos 60 into T 2. So, this is the volt second of x axis component of the right hand side. Left hand side is V s into T s or T c does not matter. T s into cos theta. I liquid it. Similarly, I will do for y axis as well. I have two equations and two variables. So, T 2 is given by time for which the V 2, time for which V 2 is on is given by this equation. T 2 is equal to T c is the sampling time. It is known. A is the modulation index. Sin 60 is the value is known. Only the variable is sin theta. And this theta is the angle which the space vector makes with x axis. Since this vector is rotating and if I know the time, I can determine angle theta. If I know the frequency of rotation, that is 50 hertz here and at any given and I know the time as well. So, I can determine sin theta. So, if I once I know T 2, I can calculate one as well. So, T 1 is given by this expression T c into A into sin 60 minus theta by 60. And the time for which 0 vector is applied is given by this equation. Do not get confused. I have been saying T s, but here it is T c. T c is nothing but T s by 2. Why it is T s by 2? I will tell you. So, these are the following observations. T s is the 0 voltage vector. T c is the sampling time by 2. T 1 is the time for which B 1 is applied and T 2 is the time for which B 2 is applied. And T z could be either 0 0 0 or 1 1 1. Does not matter. So, the observations are irrespective of the ratio in which T z is divided between the 0 sets. I can apply 0 0 0 or I can apply 1 1 1. You can divide as per your convenience. It does not matter. It does not affect your whole second balance. Active vector V 1 need not be applied over a continuous period for T 1 seconds. It need not apply, but then total time should be T 1 and total time for which B 2 is applied should be T 2. It need not be applied continuously. Let us not get into this final aspect. See here. The implementation period is here. Initially, I apply 0 0 0. The philosophy is attaining given time only once which is should be turned on or off.  In other words, I am at the origin. I will turn on phase A. Nothing happens to phase B and phase C. So, I am along the x axis. V 1, voltage vector V 1. After some time, T 2 turns on. After some time, phase B is turned on. I will apply 1 1 0 and at the end of T 2, I will turn on C as well. Where do I go? I go to the origin. So, you see here 0 0 0, 0 0 1, 0 1 1, 1 1 1. This is half of the sampling time and again I will go back the same manner 1 1 1, 0 1 1, 0 0 1, 0 0 0. So, if I see this figure here hexagon, what am I doing? What are we doing here? 0 0 0, 0 0 1, 0 1 1. I come back to the origin 1 1 1, go back in the same direction, something like this. That is what I have shown. You do not need to do this. What you can do is 0 0 0, 0 0 1, 0 1 1. Come back 0 0 1 and 0 0 0. You do not have to turn on C phase and go to the origin, not required because if there is no change in the volt second or it does not affect over that volt second balance condition. It is very simple to, why it is so popular is very simple to implement in real time. I need to calculate only T 2 and T 1 and only one variable is not known there or I need to have the truth table of sin theta. I will digitize 60 degrees, I will divide into some n parts. So, n by 60 I will make a table and depending upon the switching frequency. Rest all are known. T C is known, T sin 60 is known, A is the modulation index. If I want a constant output voltage, A also remains constant. Now, T 2 is determined by sin theta itself. Theta is the position of the space vector and it is known. For each sampling time, yes, for each sampling time space vector rotates by an angle delta theta. If T is equal to 0 space vector is along x axis, after T C it moves by an angle delta theta. So, I need to know only sin theta. I can have a truth table and I will save it in the memory. Similarly, for T 1 I need to know only 60 minus theta. So, very popular and very simple to implement. I do not want to discuss more details of the sinusoid, sorry, most details of the space vector PWM technique. There are finer issues. What is the magnitude of the voltage? What is the maximum value of V s that I can get? For which the output voltages are sinusoid? I said what is the maximum value of V s for which the output voltages are sinusoid? How do I determine? I know the condition. If the output voltages are sinusoid, then locus of V s is circle. So, that is nothing but the radius of the encircle being circle. What is that value I can determine? Because I know what is this, the radius of the circle is given by this value. So, I can determine or it is possible to determine the maximum value of V s for which the output voltages are sinusoid. More about it, you can read the literature. It is well reported. So, you can go to the slides also. They are very simple to understand. Here I have told you what should be the number of samples per sector? What should be the number of? I told you if there are n samples. So, I need to have 60 divided by n, the size of the truth table. Now, what is that n? I have explained here. All the sectors should be equally used in entire cycle producing a symmetric line voltage and samples of positions symmetrically about each of the sector with one sample at the center. If n is equal to 3, the samples of positions are 10, 30 and 50. So, these are rules should be followed for the three-phase limit. So, if I know n is equal to 3, I need to have sin alpha, sin 10, sin 60 minus 10, sin 30 and sin 50 and sin 10. That is all I need to have. That is about it. So far, we discussed DC to DC conversion and DC to AC conversion. Now, before connecting this AC power to the grid, let us see what should be the most elegant method of converting this low voltage or low voltage output from the solar to 230 volt supply. We know now, if I know the input voltage, I can get any output DC voltage that I can get by using the various, one of the various power electronic interfaces that we have discussed and given an input voltage, I can convert it to AC. Now, what sort of a configuration to use? Say input is, I have only a 24 volt solar panel, I want a 230 volts AC. Now, to get a 230 volts AC RMS value, what should be the DC link voltage that you need to calculate from this relationship? It depends on the PWM technique. See here, everything is given here. So, if I know, I told you we need a 230 volts RMS. So, therefore, peak comes around 300. To get a peak of 300, what should be the DC link voltage? Now, how do I get this a high voltage DC that I can get? If I know the output voltage of the solar panel and if I know the required DC link voltage, if the ratio is too high, depending upon the power, I can calculate, I can use either fly back, forward, push pull or full bridge or if you do not want to use this, use or if you do not want to increase a DC link voltage or if you do not want to boost the DC link voltage, what you can do is a low voltage DC, you can invert it to a low voltage AC, then use a 50 hertz transformer. So, I will show you the circuit diagram. Solar panel, low voltage DC, whatever I can get a low voltage DC here, invert it. I have a low voltage AC, step it up and then get a 230 volts, 50 hertz AC. Everything is being done at L V low voltage. It should be extremely careful while calculating the turns ratio because 1 volt, see if I have a 12 volts or a 24 volts, depending upon the power circuit configuration here 1 or 2 devices may be conducting. You need to take into account the device drop here plus the winding resistance here. It is not V 1 by V 2 is equal to N 1 by N 2. It is E 1 by E 2 is equal to N 1 by N 2. What is E? The voltage across the magnetizing inductance in the equivalent circuit. V 1 by V 2 is equal to N 1 by N 2. It is true only for an ideal transformer. It is not a non-ideal transformer and unfortunately we are using a non-ideal transformer. So, you need to take into device drops, but then entire electronics is working at low voltage. So, life is relatively easier. You can handle low voltage, but then you are using a 50 hertz magnetics, 50 hertz transformer, 50 hertz transformer. So, the moment I say 50 hertz transformer size increases as the frequency of operation decreases, size increases. How do I reduce the overall size? I need to increase the frequency of operation. Here I have to use 50 hertz because the fundamental frequency is 50 hertz. Now, can I reduce the size? To reduce the size one thing is I need to eliminate this 50 hertz transformer. So, what will I do? I will have a high voltage DC. From this low voltage, how do I get a high voltage DC? I may have to use a again a transformer there, but then it is a high frequency transformer. See, we convert this a low voltage DC to high voltage high frequency AC, high frequency AC using either using a push pull or a full bridge whatever configuration high frequency AC, very high frequency. I will rectify it again. I will rectify it and convert it to high voltage DC. By the way high voltage means the voltage the value of voltage that is required to get 230 volts RMS. Please when I say high voltage DC it implies the required DC link voltage to get 230 volts RMS. Now, this high voltage DC I will directly invert it. I will directly invert it and if you want a purely sinusoidal supply then I may have to use an LC filter. I may have to use an LC filter and if you want an isolation of course, you can use again a 50 hertz one is to one transformer. So, the entire configuration will change depending upon your requirement depending upon the application one or two typical examples I will we will discuss. So, far we discussed DC DC conversion block DC to AC conversion block and now irrespective to our independent of this voltage I have a here either a single phase 230 volts 50 hertz supply or 415 volts 50 hertz AC. Now, if you want to connect it to the grid what do I do? Now, the so called the hot topic there was so many questions being asked how do I connect it to the grid? How do I connect it to the grid? Now, we will discuss that topic. I have a source AC source a single phase AC source this is nothing but the grid and this is nothing but a voltage source inverter a voltage source inverter a single phase voltage source inverter. I am connecting this voltage source inverter to the source through an inductor what should be the value of an the question that was asked yesterday we will see. I told you it is a voltage source inverter basically is a volt two quadrant converter two quadrant converter current could be positive or negative but voltage will remain the same. Now, the power coming is coming from the DC side from the solar side this is the direction of power and it has to be fed back to the source how do I connect it? Now, let us not worry about how to connect it we will see assume that it has been connected assume that it has been connected how do I transfer the power? How do I transfer the power? Because this inverter does not know how much power is coming from the solar cell? Here as of now we are assuming that there is an MPPT maximum power tracker depending upon the sun insulation it extract the maximum power from the solar cell and it dumps to the capacitor that could be either at the input of the inverter or it could be the output of a DC to DC converter. So, only the MPPT knows the amount of power that is being drawn from the solar cell inverter does not know that power has to be fed back to the grid how do we control that power? Now, before doing that let us do go back to circuit theory by the way what sort of a waveform will I get here? What sort of a waveform will I get here? Voltage at this point is a pulse width modulated waveform that is what we have shown that is what I had shown you yesterday. This is the output voltage waveform of the inverter voltage source inverter there are large number of pulses. So, if the load is highly inductive I get a sinusoidal current.  So, if I use a LC filter I will get a purely sinusoidal voltage. So, I am assuming that there is an LC filter or I will neglect the higher order harmonics and I will draw the only the fundamental equivalent circuit. I will repeat I will draw only the fundamental equivalent circuit. I am assuming that there is a LC filter after we will see if there is no LC filter what happens do not worry. So, voltage at this point is a sinusoid. So, in other words I have a AC source here. So, this is the equivalent circuit the can I so this is how the equivalent circuit looks like I have a grid voltage V 1 voltage source V 1 V A B is the output voltage of the inverter output voltage of the inverter. This is nothing but again a sinusoid it is straight they are connected through an inductor as of now I am assuming that this inverter is connected how to connect it we will see the so called the synchronization. So, the equation for power transfer is nothing but two sinusoidal voltage source are connected together tied together by an angle by an inductor L power transferred from source V A B to V 1 is given by V I V A B omega L divided by sin theta V 1 V 2 divided by x into sin delta a very popular expression we have studied in either in the second year or third year V Tech power transferred when the two sinusoidal sources are connected together through an inductor L power transferred is given by V 1 V 2 divided by x into sin delta. Delta is the angle between V 1 and V A B so by controlling delta I can transfer the power or I can control the power fed back to the load how to keep that or how to choose the delta how to determine this delta what could be the control strategy the question number one that because inverter does not know the amount of power drawn from the solar cells inverter does not know only the MPPT knows how do I choose the correct value of delta here I am keeping see here V I is the input voltage of this the grid V A B is the fundamental V A B is the magnitude of or the RMS value of the output voltage V A B V 1 is the RMS value of the supply voltage V A B is the RMS value of the output voltage of the inverter omega L is this reactor how do I choose delta we will see see here is the two wave forms this is V I this is output voltage of inverter the fundamental equivalent circuit if there is no harmonics if there are sorry if there are there is no LC filter what is the equivalent circuit I need to draw the superposition I need to use the superposition theorem I am assuming that I am assuming that input voltage is pure sinusoid and there are harmonics here what is the equivalent circuit equivalent circuit is this is I need to consider the voltage of one frequency at a time this is the equivalent circuit at fundamental frequency at any frequency this is 0 here why input is a pure sinusoid here is the effective inductance now it is omega 1 into L where omega is the frequency of the harmonic that is present and here is the magnitude of the harmonic of the RMS value and I can determine the current that is being generated by this harmonic voltage I will repeat the harmonic equivalent circuit is going to be something like this omega n omega into L where n is the number of the harmonic that is present and here is the RMS value of the harmonic voltage that is present I can determine the current. So, I need to do for each and every frequency that is present as the frequency increases this inductor will practically will appear as if it is an open circuit. So, high frequency components get filtered out high frequency voltage components will get filtered out. So, if I know the various harmonic components I can determine the total harmonic distortion. So, if I know if depending upon the power level and depending upon the grid voltage level the with the various standards will tell me the total harmonic distortion and accordingly I will choose omega L and the switching frequency by the way switching frequency I will not be able to change because it depends on the power level. Generally, we do not change the frequency frequency we will keep it constant, but then I need to T h t has to be the total harmonic distortion that is present in the current waveform that is fed to the grid that should be satisfied by or this is given by the standards various standards. Therefore, I can calculate this inductor that is one of the ways that another criteria as well higher the value of inductor slower is going to be the response because if I there is a change and how do how does this circuit behave you will see once one of the ways to determine is I need to control T h d switching frequency is known. So, I will know the harmonic spectrum once I know the harmonic spectrum I can determine the current and therefore, yesterday there was a question how do I control the reactive power as well or I told you that voltage source inverter can supply any q it requires only delta p it has to either the delta p can be used from the d c side provided there is an input or in the night if there is no input power active power input this delta p can come from the from the grid and this inverter can supply q the reactive power what should be the. Now, if delta is equal to 0 consider an ideal case delta is equal to 0 and v i is not equal to v a b v i is not equal to v a b delta is 0 what happens if delta is 0 v i is in phase with v a b magnitudes are not the same. So, definitely there is going to be a difference potential across the inductor there will be a current flow what is that of a current now since delta is 0 active power transferred is 0 if the active power transferred is 0 there is no in phase component, but then there is a current flow why these two points are at different potential I told you v 1 is not equal to v a b and delta is equal to 0 if delta is 0 active power transferred is 0 if the active power transfer is 0 in phase component is 0, but then there is a current flow. So, it has to be reactive current it has to be reactive current. So, either it could be leading or lagging either it could be leading or lagging that depends on the magnitude of the inverter output voltage. I am assuming that grid voltage will remain constant by changing this magnitude I can make this inverter to supply either a leading current or a lagging current in other words this inverter can appear behave like a capacitor or like an inductor that I can do just by controlling the output voltage of the inverter. This expression says I will make delta is equal to 0 there is no active power transfer by controlling v a b if the magnitude of v a b is higher then there are two possibilities why two there are three if v i is equal to v a b and they are in phase there is no current.  So, these two cases corresponds to leading and lagging current that can be determined from this equivalent circuit see magnitude of source voltage is less than the magnet is less than the output voltage of the inverter the grid voltage rms value of the grid voltage is less than the rms value of the inverter at that time we found that I s the source current leads the source voltage. So, this is nothing but see it is a capacity circuit current leads the voltage if it is less current lacks the voltage this is nothing but an inductor. So, therefore, a voltage source inverter can act like an inductor or like a capacitor to do that it has to draw a very small amount of power that power which accounts for the losses here and the losses in the inverter. So, in non ideal case this delta is not equal to 0 this delta is again determined by the system losses. So, for both the cases we will see what are the both the cases one is when there is an active power transfer how to choose the value of delta and when there is no active power transfer it has there is only a reactive power delta value of delta approaches 0 it is very small just to account for losses how to determine this value of delta we will discuss this is the equivalent circuits yeah this is about it. So, here is an schematic I have a source load this is a voltage source inverter tied to the grid through an inductor as of now we have not discussed how to tie this inverter to the grid have patience we will see there could be a power coming from the DC side from the DC side that power has to be fed to the grid assume that there is a spare capacity because sun insulation has come down and grid requires grid requires reactive power in addition to this active power this grid can supply q how to supply q we will see if it can supply active power it can supply reactive power it can also supply harmonic current as well now how to how it can supply the harmonic current we will see it is not a issue here see here this is equivalent circuit load is non-linear in nature assume the load is non-linear in nature the moment I say load is non-linear in nature current drawn by the load is non sinusoidal when the current drawn by the load is non sinusoidal using the Fourier series I can get the various harmonic components input voltage is sinusoid I want that the harmonic source the harmonic current supplied by the source should be 0 what we should do what we need to do is this inverter should generate the required harmonic current assume that the load is drawing the fifth harmonic current and the seventh harmonic current depending upon the impedance of this inductor my inverter has to generate a fifth harmonic voltage and a seventh harmonic voltage how to generate it is possible so in principle we can control this inverter such that it can supply active power it can supply reactive power it can supply q as well it can supply the harmonic current as well I am assuming that I have used a faster devices power handling by this inverter it is relatively low therefore it can compensate the harmonics that is about it I will take a break I will take few questions now we are ready Nagpur go ahead for your question sir my question is on SV PWM question on question on in case of state space vector PWM in space vector PWM while implementing the vector we put 0 vector at the starting as well as at the end of TS okay go ahead go ahead isn't it so is it necessary to bother about the dead band I told you 0 vector need you need not put 0 vector in the beginning as well as at the at the end this is I have just shown you I do not you do not need to have 1 1 1 you can have 0 0 0 0 1 1 0 1 1 and again come back straight away 0 0 0 0 0 0 1 0 1 1 and go back you do not need to have 1 1 1 you do not need to have 1 1 1 so at the end of TS oh yeah okay fine end of TS I am at the origin fine we do have 0 0 0 0 yeah okay all the is it necessary to implement the dead band oh you mean dead time oh you mean dead time yeah yeah yeah voltage is inverter 0 0 0 1 1 1 what does it mean either three devices are on or three devices are off I am measuring the load to be highly inductive load is load all the three points are connected to the positive DC bus and load is freewheeling through either to the positive DC bus or to the negative DC bus devices are carrying current there is a current flow depending upon the direction of the load all three points are connected to the same point load is a current source highly inductive there is some current flowing there is some current flowing in the load now after 0 0 what sort of where are you going in the same what is the conducting state it could so happen that you may be going to the second second sector and there has to be a voltage there has to be a dead time between these two there has to be a dead time between these two here 0 0 0 fine but then there was there is current flowing through the load devices are carrying current either the current is flowing through the device or it may be flowing through a diode I do not know it depends on the load we have assumed that load is highly inductive on there is current flowing through the load just because you have applied 0 0 0 or 1 1 1 it does not mean that there is no current flowing in the load is that ok and if you are switching the complementary device there has to be a dead time in a voltage source inverter see for example, if you are going from 0 0 0 if you are going 0 0 1 you are turning you are turning on this switch initially there was some current flowing and when I turn off this current has to flow through this switch either to the switch or diode I do not know it depends on the load power factor it depends on the load power factor immediately when you turn on the switch I do not know whether this switch will start carrying current I do not know that is a load current load current but then what will happen if there is a voltage source here there is another path as well oh my goodness the question is question is you said that high power level we need to reduce the switching frequency on what basis this is done now question my question to you is why we should reduce the switching frequency depending upon the power level what happens if I if I keep the switching frequency same and gone increasing the power what will happen as the power level increases current flowing through the device also will increase and every time I turn on and off there is going to be the switching losses turn on losses turn off losses and at any given time the operating point should lie within the safe operating area and I told you that there is what is known as T j max junction temperature maximum junction temperature has to be controlled so that is the reason we need to reduce the switching frequency so as the switching as the power level increases current increases voltage also may increase voltage also may increase because kilowatt rating I may have 450 volt input as the power rating increases I may go in for 1.1 kv 3.3 kv or 6.6 kv so every time you switch the device there is going to be on turn on losses and every time I switch off there is going to be a turn off losses I need to control the junction temperature and this may be the third or fourth time I have been saying this same question is being asked in power circuit why third harmonic is not applicable what do you mean by in power circuit why third harmonic is not applicable I never said this could you please frame this question properly in power transfer circuit why third harmonic is not applicable in a 3 phase 3 via system can line voltages have third harmonic in a 3 phase 3 via system can I can the line voltage have third harmonic this is being thought in may be in the third year BTEC what is advanced sinusoidal PWM for single phase inverter I do not know what is advanced sinusoidal PWM for a single phase inverter I do not know be more specific what is advanced yesterday there was a question how do I how how do I have PWM what is a PWM technique for a single phase inverter single phase inverter has take one sinusoid of required frequency and magnitude if you want to have a 50 hertz supply the frequency of this sinusoid should be 50 hertz you want a constant magnitude therefore you keep this magnitude constant compare with the high frequency triangular the intersection point determines the switching instant for the inverter if you use half bridge only turn on you there are only two devices and if there are if it is a full bridge you turn on s1 and s2 together s1 s2 s3 s4 if you have half bridge you turn on only s1 at a time when s1 turns off turn on s4 and if you use full phase full bridge s1 and s2 are turned on and off together s3 and s4 are turned on and off together that is all this is for a single phase single phase inverter now what is advanced for single phase I do not know in power factor improvement using a VSI which factor we need to vary for smooth control of power factor improvement let us see in power factor improvement which factor we need to vary for a smooth power factor come on that you need to answer power transferred is V1 V2 divided by x into sin delta this is the expression for power what is the expression for q forget about if you do not know the expression for q it is ok now you tell me I am assuming I am taking an ideal case delta is equal to 0 V1 and V2 are in phase V1 is 1 voltage source this is V2 this is x so this so this is V1 V2 this will be your I current flowing now you want to have a smooth control of this magnitude of current how do I do that that I can do by smoothly changing the difference of V1 minus V2 difference of V1 and V2 V1 minus V2 I need to change smoothly so if V1 remains constant I need to change V2 how do I do that assuming that V2 is the output voltage of the inverter that is V2 is given by m into VDC that is what I told you this is the output voltage of the inverter now I can change VDC or I can change m I will keep VDC constant I will change the modulation index m so if I change the modulation index m in a smooth manner out V2 will change accordingly since V1 is V1 is assumed to remain constant I will change smoothly that is what you want and for non-ideal case delta is finite and this now you derive an expression and you find out or the controller will do all this you have to change modulation index sir this next question is sir how VSI can supply both lagging and leading reactive current not at a time it cannot supply together it either it can either it can supply either it can supply leading or lagging even I do not know how it can supply but from this vector diagram you can infer isn't it this is the equivalent circuit both are in phase so active power transfer is 0 but the magnitude is not the same if the magnitude is not same there is going to be a current flow but it is not active current in phase current so that has to be quadrature current so either it could be plus 90 or it could be minus 90 so this vector diagram tells me in this case when output voltage of the inverter is higher than the grid voltage current is leading if the output voltage of the inverter is less than the grid voltage current is lagging so I need to just control the magnitude of the grid voltage with the rest the magnitude of the invert inverter output voltage with respect to the grid now how do I do that BAB is proportional to m into VDC if VDC remains constant change m that is all yeah any other question yeah I will it is 10 11 now we will start at 10 15 a 4 minute break I will take


In this video I will describe the characteristics and function of enzymes, describe the various factors that affect enzyme activity, including concentrations, temperature, pH, competitive inhibition, and allosteric regulation. An enzyme is a biological catalyst, and a catalyst is a chemical that will speed up a chemical reaction, but is not consumed in the chemical reaction, and therefore can be reused over and over again. An enzyme is typically made of protein, although some enzymes are made of nucleic acids, for example the ribosome has a catalytic region that's made out of RNA, but the majority of enzymes are proteins. An enzyme has an active site where the reagents will bind to the enzyme. These reagents are known as substrates, and the reagents or substrates will be converted into products as this chemical reaction proceeds. An enzyme is a catalyst and therefore enzymes speed up chemical reactions by lowering the activation energy required for that chemical reaction. The overall Gibbs free energy change of the chemical reaction is not affected by an enzyme, however by lowering the activation energy an enzyme can make a spontaneous chemical reaction, proceed more rapidly. Enzymes will also facilitate the coupling of endergenic reactions to exergenic reactions facilitating the non-spontaneous endergenic chemical reactions. Temperature influences the activity of an enzyme. This graph shows the activity of the enzyme represented in percentage of maximal activity on the y-axis, and temperature of the enzyme's environment on the x-axis. Enzymes will have the highest activity at an optimal temperature. If the temperature is lower than the optimal, there will be a lower rate of the chemical reaction. This is largely related to the decreased kinetic energy of molecules. As molecules are more slowly moving, it takes longer for those molecules to bind to the active site of the enzyme. If the temperature is higher than the optimal temperature for that enzyme, the reaction rate will also decline, but notice that there's a steep decrease once the temperature is greater than the optimal temperature. This graph is representing an enzyme that has its optimal temperature near body temperature of around 37 degrees Celsius. Once the enzyme is heated beyond its optimal temperature, it will start to change its shape and become misfolded. As the increased kinetic energy causes movement of the amino acids within the polypeptides of a protein for the enzyme, the enzyme can become misfolded and that is going to disrupt the function of the enzyme, changing the shape of the active site, preventing it from catalyzing the chemical reaction. So when a protein becomes misfolded as a result of an extreme environmental condition, that enzyme has become denatured. So denaturation is misfolding of a protein as a result of an extreme environmental condition. The example here that we see in the picture is frying of an egg. When you crack an egg, the egg white is primarily the protein ovalebumin that has a clear color to it, but as you expose that protein to an extreme environmental condition, very high temperature in the skillet, the ovalebumin protein will become misfolded, it will become denatured and that will lead to the opaque white color of the egg white when it cooks. When an enzyme is denatured, this will cause a change in the shape of the active site disrupting the function of the enzyme and so the structure of the enzyme is intimately connected to the function of the enzyme and a change in structure such as denaturation can disrupt the function. The concentration of hydrogen ions in the environment of an enzyme will also influence the enzyme's activity. Enzymes will have a highest activity at an optimal pH and if the environmental pH for that enzyme is lower or greater than the optimal pH, the enzyme activity will decrease. This is in part a result from hydrogen ions binding to the partial negative charges of polar covalent bonds and the negative charges from ionic side groups in the amino acid side chains of the polypeptide of the enzyme. As these hydrogen ions start to disrupt the interaction between charges that stabilize the secondary and tertiary structure of the enzyme, the enzyme can become misfolded and a misfolded or denatured enzyme will not be able to catalyze the chemical reaction. Enzymes function at an optimal pH that is typically the pH of the environment where they are functioning. For example, there are enzymes produced in our stomach that have an optimal pH of around two because the environment of the gastric juice in our stomach is a low pH whereas enzymes that function in our blood will have an optimal pH of around 7.4, the pH that's present in our blood and some enzymes will have an optimal pH that's much higher because they are operating in an environment with a relatively high pH. For example, the small intestines has a relatively high pH and there are many digestive enzymes secreted into the small intestine in order to facilitate digestion of food and these enzymes have an optimal pH of the higher pH typically found in the small intestines. Increasing the concentration of substrate will lead to an increased rate of the chemical reaction catalyzed by an enzyme until we reach saturation the maximum velocity or Vmax occurs when all of the enzyme in solution is saturated with substrate and therefore the chemical reaction will not accelerate if we increase the substrate concentration further as the enzymes are catalyzing the chemical reaction as rapidly as possible. The only way to create a further increase in the reaction rate would be to increase the concentration of enzyme inhibition of an enzyme is when a molecule known as an inhibitor binds to the enzyme and decreases the rate of the chemical reaction that is normally catalyzed by that enzyme. The graph here is showing us the relationship between substrate concentration and reaction rate of a normal solution containing enzyme with no inhibitor in the purple line compared to a competitive inhibitor in green and a non-competitive inhibitor in blue. A competitive inhibitor is a molecule that binds to the active site of the enzyme therefore as we increase the substrate concentration substrate will compete with the competitive inhibitor for the active site of the enzyme and at very high substrate concentration the substrate will out compete the inhibitor leading to the same Vmax as the solution with the normal enzyme that contains no inhibitor. In contrast a non-competitive inhibitor is a molecule that binds to a different location on the enzyme known as the allosteric site. Increasing the substrate concentration will increase the reaction rate of a solution that contains a non-competitive inhibitor however at very high substrate concentration a solution containing a non-competitive inhibitor will not reach the same Vmax as the solution that does not contain the non-competitive inhibitor. This is because the non-competitive inhibitor binding to an allosteric site will inactivate the enzyme preventing it from catalyzing the chemical reaction even though the active site may be able to bind to the substrate the enzyme will not catalyze the reaction. In some cases the non-competitive inhibitor binding to the allosteric site will change the shape of the enzyme so that the substrate cannot bind to the active site. Therefore increasing substrate concentration will only increase the activity of the enzymes that are not bound to a non-competitive inhibitor and all of the enzymes that have a non-competitive inhibitor bound are effectively removed from solution because they cannot catalyze the chemical reaction. So a non-competitive inhibitor can also be considered an allosteric inhibitor because a non-competitive inhibitor binds to a site that's different from the active site known as the allosteric site. In the illustration here you can see a non-competitive inhibitor binding to the allosteric site could change the structure of the enzyme preventing a substrate from binding to the active site. Some enzymes require allosteric activation where a molecule known as an activator binds to the allosteric site changing the structure of the enzyme which will enable the substrate to bind to the active site. Allosteric inhibition with a non-competitive inhibitor binding to an allosteric site is a common mechanism for feedback inhibition of a metabolic pathway where the end product functions as the non-competitive inhibitor binding to the allosteric site of the first enzyme in the metabolic pathway. This will help to control the concentration of the end product and prevent excessive amounts of substrate from entering the metabolic pathway. This will enable that substrate to enter other metabolic pathways or be saved until more end product is needed. Studying enzymes and enzyme inhibition has been useful clinically for the discovery of new medications. For example, aspirin is a medication that functions as an anti-inflammatory and pain reliever by inhibiting a cyclooxygenase enzyme involved in the pain and inflammation signaling pathways. However, medications often have side effects that can make them intolerable for some patients and they may work great for other patients. Studying the cyclooxygenase enzyme has led to the production of a variety of new non-steroidal anti-inflammatory medications that inhibit the cyclooxygenase enzyme. For example, ibuprofen and Advil and Aleve are non-steroidal anti-inflammatory medications that were discovered by looking for inhibitors of the cyclooxygenase enzymes.


What's going on everybody got Kyle here in late in sports cards and we are ripping 2023 leaf ultimate hockey This one is for Justin K Oh, man 2020 f1. Let's go rich. I'm in on that Pull some for staphons pull some rustles some Landos and 2020 flawless. All right guys stuff is being added in stock Um some extra stuff like he's like rich just said 2020 chrome f1 Those boxes are impossible to find and 2020 flawless football And added if anybody's interested in those 2020 f1. That is the first year they made it. Oh, that is some that is some high in stuff Stapping rookies Yeah, some serious stuff in there Some serious stuff in there. There's some serious stuff in here. Alrighty. Good luck. Justin. Let's see it Sean is right. Here's a quad relic to start us off. It's going to be chris pronger Al meccanus brethole and bernie faderco That's going to be a mount rushmore one of five on the quad relics I should all be game used Game used there have a stick relic and then a couple of jerseys Not rush more to four This one is going to be a mic gardener mic gardener 11 out of 25.  That's what I was confused about I thought it was a three at first but it's like backwards. I was like what's going on Nice one there for you mr. Justin a little triple auto to close us out to uh nine Awesome appreciate you sir Always love the ultimate ultimate hockey and grabs Justin will get those right out to you my man