So, we will continue our last session on the SOI MOSFETs and this is lecture number 4 in that series of SOI MOSFETs. We will discuss subterrestrial swing in SOI MOSFET and some short channel effects and the fin effect. Just recall what we did in the bulk MOSFET. This is the subterrestrial region, where you observe the current below the threshold voltage. So, we saw that current is exponential there given by an expression like this. Now, n is the factor which decides how fast it is you are able to turn off, how quickly the slope. So, if n is equal to 1 we know that it is 60 millivolts per decade. So, you would like to turn it off with the very small change in voltage. So, n should be as close to ideal as possible 60 millivolts per decade. So, we also saw that this n can be determined from this relationship delta VGS by delta psi of s. It tells us the how good is a coupling between the gate and the channel. If the delta psi s is delta VGS coupling is excellent. So, then n is equal to 1, but since there is a depletion layer here we saw that you can derive this delta VGS by delta psi of s using this equivalent circuit. So, that we have shown that that n is equal to delta VGS by delta psi of s using this equivalent circuit is 1 plus C d by C oxide. C d is the depletion layer, there is a depletion layer there that capacitance. This is a bulk MOSFET or partially repeated SOI MOSFET whatever both same C oxide per unit area C depletion per unit area that is the thing. Now, what we are trying to point out here is that n is the one which decides your sub threshold swing or sub threshold slope. You want to keep it as close to 1 as possible. Now, that n is decided by what is the capacitance between this point and the ground point. In this case it is C d. If there is another capacitor parallel to that C d like the d i t we saw that that will become larger. Effective capacitance becomes larger. So, this n will become larger that is d i d increase d i t increases the slope. Suppose there is a capacitance series with C d then the entire C effective will come down. Let us see how it works out in SOI MOSFET. In SOI MOSFET you can see that is the red colored or on the oxide thicknesses. I have deliberately shown different thicknesses it does not matter. So, you have got back oxide, you have got the front oxide and I am showing a situation where you apply voltage to the front gate and the back gate is grounded. I can extend it to both gates so bias. So, that means actually front gate will be inverted. So, if I want to find out the sub threshold slope see in this case since this is grounded it will be the front gate it will be conducting that is the channel. And if I choose the doping low and the thickness low small it will be a fully depleted case. So, when it is fully depleted between the gate and the ground you can see there is a capacitance front oxide. Then this capacitance between this point and this point silicon capacitance which is actually epsilon silicon divided by T silicon.  Now what we pointed out in our previous slide is whichever channel current you are observing from that point to ground point how much is the capacitance present. You can see that that is a channel where the surface potential is psi s f. So, if I want to find out that n I must have delta V g s by delta psi s f that you can get from this equivalent circuit front gate silicon back gate all three capacitance in series. So, from this point from the front channel to ground the total capacitance is a series combination of C s and C ox v. Particularly if the C ox is thicker this capacitance is smaller and this capacitance C effective what we are showing here that is shown here as C effective. So, between the channel and the sub ground you have got one effective capacitance which is actually C ox into C ox v by this series combination. So, if C ox v is small this is going to be small smaller than what you get in the usual MOSFET. So, the sub threshold slope n factor is 1 plus C effective by C ox v f. Sub threshold swing is KT by Q log 10 that is 60 millivolts into 1 plus this quantity that is n factor. Now, you can have the C effective very small compared to C ox v f particularly when the C ox v front gate ox v is thin. So, you can get sub threshold swing very very close to Y B T log 10 that is 60 millivolts. So, n is much closer to 1 in fully depleted F T fully depleted S I then partially depleted that is partially depleted or even bulk MOSFET. So, we will get less than that and bulk MOSFET also the less than bulk MOSFET. Thicker back oxide helps in reducing the sub threshold swing ok, but you may not have all the time thick oxide, but use it as a double gate MOSFET you will see how it works out. Then the coupling between the gate and the source would be excellent and you will get 60 millivolts per decade and go to double gate MOSFET operation. And when this whole thing is depleted we will see how it comes up and ok, but otherwise what you have to understand is when the whole thing is depleted whatever gate voltage you change beyond that point it goes into the junction we have discussed that. So, once this layer is depleted extra voltage at apply here between the two of them that goes into the junction. So, delta V G is equal to delta psi of S that is the ideal factor will be equal to 1 this factor will then be equal to 1. So, you get 60 millivolts in double gate MOSFET. Now, this is just some of the results which have even appeared in textbooks like college book. So, sub thresholds slope or sub thresholds swing both terms are used actually it is inverse slope because we are finding out that we are finding out delta I D by delta V G F, but use what you understand is for one decade current change how much is the voltage change. So, you can see sub thresholds swing or slope when the SOI layer is thick. If the doping is 8 into 10 to power 16 and twice SOF is there on the front gate, depletion layer width is 115 microns. So, if you are get SOF in thickness is thick 200 microns or here 400 microns 450 microns it is partially depleted. Depletion layer width is actually 115 microns nanometer and SOI layer thickness is 450 nanometers. So, it is not fully depleted. So, in that case the C effective C D which corresponds to that thickness. Now, if you reduce the thickness to about 100 nanometers, SOI layer if this is 400 nanometers it does not deplete by the time it has gone to 115 nanometer depletion layer does not widen, but if this is 100 nanometer it is fully depleted. So, you will have a capacitance will be series combination of these three and you will get the sub threshold swing very small very close to 60 millivolts per decade. In fact, this number is about 63 millivolts you can never get one because you can never get this factor equal to one unless you go to double gate operation. So, you have 63 millivolts per decade. So, what you are telling is if you are for a given doping if I keep on reducing the thickness, your sub threshold slope will fall and we also saw that threshold voltage also be smaller for a fully depleted case as compared to that. Now, these two cases you would see the I D versus gate voltage. This is above threshold voltage partially depleted gate case that is 200 nanometer thick film. So, this is the sub threshold swing of 102 millivolts, what we saw here in this region and you made it very thin 100 nanometers this case fully depleted. You have got C effective is C silicon in series with the back oxide which is very thick. So, you get that very close 63 millivolts per decade you get. So, benefits of fully depleted MOSFETs, SOI MOSFET low threshold voltage we have seen already last lecture. Sub threshold swing is very close to the ideal 50 millivolts per decade. What is the benefit of that? Benefit of that if you take here here the threshold voltage is lower. If the threshold voltage is lower it enables you to go to lower supply voltages and if the threshold voltage is lower and sub threshold swing is ideal to 50 millivolts per decade it can quickly be turned off. So, that is why you can use the SOI MOSFET very effectively for low voltages low supply voltages and that is that means low voltage and low power applications. So, mostly you will see application of this is for low power low voltage device and also there is no latch up we saw that already. Now, this is just reminding you that in the bulk MOSFET, depletion air width is wide this is in silicon peak electric field is larger because of that wider depletion air width and SOI electric field is like that this is be around with the back channel this is the front channel electric field is smaller all that we have seen already. To reemphasize that to so that you recall the diagram accumulation that get depleted both inverted lower and lower. So, when you have this particular situation you can see that the field in this direction transverse direction to the channel go back to that and show you what we are telling it the field in that direction from the gate towards the channel that is what we are plotting here that is small when you go to duplicate operation when both are inverted. If the field is small now you know that if the transfer field is small at the doping I am sorry the mobility will be high. If the field is higher here in this case accumulation case field is high and the bulk MOSFET field is high transfer field is high because of high doping case and as a result the mobility of the carriers will be reduced because of transfer field. In this case you can use very likely doped subsets and therefore the doping effect is reduced on mobility and double gate when you use the transfer field is reduced therefore effect of transfer field also is reduced. So, you can get the best mobility is using this type of device. This is one of those results which have been reported reported by some of our students when they made the MOSFET with here this was a SOI MOSFET with the doping of 10 to power of 14 into 5 percentage meter cube twice 5 is 0.54 volts now XT maximum is 1.2 micrometers, but your T silicon is T silicon is much smaller than that. So, in fact what you have got here is something like let me see where it is there it is just about 400 nanometers of the total let me see where it is there T ox speed W by L is there T ox front gate is 115 nanometer back gate is 400 nanometer and your chosen at is given about 87 nanometers much smaller compared to this one part of micrometers. So, that is the thickness of that. So, it is a fully depleted layer now what we are showing is that transconductance delta I D by delta V G which would also correspond to the current as a increase that back gate these are there are two curves the red one corresponding to one of them correspond to a smart cut SOI waveform made by smart cut we want to see whether it makes a difference if you use smart cut or SOI. So, the black one is the SOI waveform practically not much difference when you use the same thickness. So, I bias the back channel into accumulation where the back gate is minus accumulation front gate is actually inverted only one gate is conducting in fact threshold voltage will be high in those cases and you will get the current due to one channel and as you increase the back gate voltage from negative to more and more positive side or bring it to 0 back channel come to depletion your current increases your fields decrease threshold voltage decreases your current decreases now when you go to particular bias 0 voltage here we do not have to go to the details what we are doing is back channel accumulation back channel depleted back channel inverted in all the cases front channel is inverted in this portion you are talking of front channel inverted back channel taken from accumulation depletion and inverted. So, your current keep on increasing that I showed you some curve where the transfer characteristics were shown from that is derived you go back to the previous lecture you see those graphs. So, what we are trying to point out is the current is maximum both the channels are inverted now from here onwards you have a situation where you increase the back channel to plus. So, that back channel is inverted and front channel is going from inversion to depletion and accumulation. So, best results you get best transfer voltage and best current you get when the both the channels are inverted that is what I am trying to show from here. So, this is showing that there is not much difference between SOI and SOI there is a trans conductance that the maximum trans conductance that you get in each device operation. Now, from the trans conductance you extract the mobility you get this maximum current maximum trans conductance because of best mobility that you get. So, this is a situation where the both channels are inverted as I pointed out when the both channels are inverted the fields are small transfer field mobility are best. So, you get best mobility when the both channels are inverted they just as the information I have just put it across to you. So, that these are real and may be the location of best mobility point may have shifted from one device to other device. Now, this is the red is the mu n of the front channel for the SOI vapour and this is the mu n of the back channel. Here, this is mobility of both the channels combined if it because in this portion we are seeing the front channel inverted in this portion we are seeing back channel inverted because back voltage is very large. There is a good coupling is there when you do that the front channel goes through depletion and accumulation. Now, to sum up whatever you have said now fully depleted double gate MOSFET transfer cell field is low to read rate. Therefore, high mobility high trans conductance in the both channels are inverted. One more thing that you have we will have to realize is that the. So, what we say from here is you can use double gate in the sense both gates in a connect together and have both channels inverted simultaneously that should give you the best mobility because the fields are small in that case we saw it already in our previous discussion. So, thin oxide thin SOI layer leads to tight coupling. If you see I am sorry if I put a double gate MOSFET like this I do not know whether you are able to see that we see the SOI layer with the source channel drain front oxide yellow back oxide yellow these two slabs show you the gate the three dimensional picture. So, I can you connect both of them such that both channels are inverted. Now, you can see when will you get the short channel effects we have to imagine or we know that the short channel effects come into picture when the drain begins to effect the potential near the source end. But if the gate distance between the gate two gates the electrical distance between the two gates is much smaller than this channel length the drain has less control on the channel and near the source region. So, some of the authors like Mindel who are in stand forward at the time they give this type of analytical guideline you will have not have short channel effect if the half the channel length that is from drain to the middle that is half the channel length is greater than this electrical distance half. See when you have two gates you can say that this half is controlled by that this half is controlled by the bottom one. So, what you see is look at the center from the center to the top electrode what is the electrical distance. So, that electrical distance is T silicon by 2 T oxide we multiplied by epsilon s by epsilon oxide to get because of the permittivity difference equivalent to the silicon. So, three times T oxide T silicon by 2 if this were silicon of that particular thickness it is the three times T oxide. So, that is the equivalent. So, you can see if the channel length is 20 if the T silicon is 20 nanometers what we are telling is 20 by 2 10 and if T oxide is 1.5 nanometers what is epsilon s by epsilon oxide 3 3 times 1.5 that is 4.5 4.5 plus 10 that is 14.5 L must be more than twice that that is about 30 nanometers if L is much larger than 30 nanometers you will not have short xanopit. And when we are telling that short xanopit are not there is sub threshold swing is 15 nanometers. So, you can see for the 20 nanometer this is the numerical solution using a software called Medici they have done they saw that sub threshold is up to about 40 it is somewhere below 70 and it is below 60 nanometers 60 millivolts up to 60 what we are telling is it should be more than about 30 nanometers I would say that you must put this as L by 4. So, if you have a 40 nanometers channel length for this condition you will have sub threshold swing of more than 60 about may be about 70, but in bulk mass that you will have about 100 millivolts per decade it is much better than that, but if I reduce the thickness of the soil here 10 nanometers that is reduced you can see that you can go even right up to about 30 nanometers or 40 nanometers very comfortably 60 millivolts per decade you can easily go to 30 nanometers still it will be about 65 millivolts per decade. So, if you want to go even get down to shorter channel length what should you do reduce the thickness of the soil here even further go to 5 nanometers you can go even down. So, the analysis shows ultimately that you can go even down to about 15 nanometer channel length without seeing the short channel effect. What is the other short channel effect seen one is the sub threshold swing increasing that you can go down right up to what I said is about 20 or 15 if you reduce the thickness below 10 nanometer thickness of a soil here and oxide layer thickness 1 nanometer if you are not able to go up to 1 nanometer change it to the high k dielectric. Now, this is the delta with threshold the threshold voltage is about 0.5 millivolts 0.5 volts or 0.4 volts how much in the shift n threshold voltage if you reduce the channel length this is the simulation it closely matches this, it is not very you would have this much smaller than L.  So, silicon thickness is 5 nanometer t oxide is 1 nanometer you can operate it very comfortably up to about 20 nanometers without seeing a short channel effect which is very hard on bulk MOSFET because then your sub threshold swing everything will get affected because doping is high here you can go to very lightly doped material. So, this is the situation advantage is very clear. Now, one more thing point that you want to see is you can use very lightly doped case fully depleted undoped practically what will be threshold voltage. So, usually we define the threshold voltage as the gate voltage at which twice y f is the surface potential, but when you go to fully depleted case it will not be twice y f and if it is undoped there is no meaning in twice y f, by f is 0. So, what they have said is you look at the charge in the channel this are the potentials inversion that is the potential if it is undoped case what is the potential not vary across the channel there is no field there otherwise slightly varying. So, this ignore that this inversion the accumulation it will be close to 0 depletion there will be plus and, but what we are trying to point out is you assume certain charge. For example, if I say the total charge per square centimeter looking at the top from the gate is 3.2 into 10 to the power of 10 per centimeter square what does it mean an average into 3 silicon it is actually number it is not charge it is number average in fact if the potential is constant there charge will be constant over entire width. So, this total charge if it is about that is what mind will have shown you can assume this and say when this charge is reached in the channel that is the threshold voltage, but strictly speaking that will not be the case. So, it will amount to an average is equal to n i e to power of this this is the relations between the potential and the average carry concentration. So, for intrinsic case potential is related to charge by this relationship background opening multiplied by exponential constant potential phi s by b t. So, that phi s is given by this equation see an average by n i into logarithm of that into k t by q gives you phi of s. So, what you are telling is you find out the phi of s at which the carry concentration is reaching that value it is approximate, but if you strictly want to see what you have to do would be you have to I hope I remember this thing you have to go into a plot where the v g versus phi phi surface in fact phi surface will be almost same everywhere that means carry concentration is same everywhere that you consider it as volume inversion and there volume of silicon is inverted. So, if you start v g at 0 potential potential is surface potential is 0 it is shared between the oxide and the junction as you keep on increasing it goes like that. So, you define this voltage v g as a threshold voltage in fact in the bulk MOSFET this is actually equal to twice F. So, plot in a bulk MOSFET you have used twice F phi of s the threshold voltage condition by seeing that when you keep on increasing that in fact twice it does not flatten out it goes like that the bulk MOSFET slight increases where it deviates from this portion you take that thing, but in the case of a soil MOSFET it almost goes to that point it will not it this will not be twice twice F point. You take the phi s at which it saturates it will not be twice F it is different because you do not know what twice F is when the undoubbed case there is no twice F still you use this condition for that because beyond that what a point whatever voltage apply goes to the gate oxide and entire thing is used for inverting the channel. So, this is a point at which inversion takes place that is the correct definition. In fact, we have for students here has worked on the thing to define the threshold voltage and a detailed paper has been written on that which has just it is hot from the oven just yesterday we got the information that paper is accepted for a full paper in the journal of applied phase AC. So, that is that condition there are lot of details involved in that may be when it appears you can just see the thing. So, you can see that there is a difference in defining threshold voltage. Now, there is one very interesting result which people have observed some of the authors like Krishnilov you know whose paper I will give at the end of this lecture there is a reference which I have given you can see that source drain this is the channel which will be fully depleted and when you deplete fully I can operate it as a single gate. How do I operate it a single gate? Single gate mode VGP connected to 0 apply voltage to the gate till the surface front channel is inverted that channel will be in depletion because it is grounded. So, when you have that situation front gate inverted and back gate grounded single gate mode when you operate they get some transconductance like this. Keep on increase the voltage you know VG minus V3 so it keeps on increases and there is a maximum transconductance reaches you have discussed in when you discussed the MOSFET theory. So, transconductance reaches maximum that is about 2 microseconds MOSFET means is the value for single gate operation this is related to current delta I d by delta VG that is the value. Now, instead of operating with the front gate I operated the back gate this is a practical result that they observed back gate. How do you do that? Single gate mode front gate is grounded apply voltage to the gate with respect back gate with respect source VG of 0 you get this sort of characteristics. You know the maximum transconductance almost matching there is slight difference because there is slight difference in the gate oxides thicknesses 1 is 50 nanometer and 60 nanometer. Now, when you operate it as double gate both gates bias such that there is inversion at the front and back together what do you expect you get the current to be the sum of these two and the transconductance to be the sum of these two, but what you get is much more than that it is not sum of these two much higher than that you know this is 2 plus 2 4 you would expect it 4 you get about 8 this is a very interesting result they have observed. So, that means when you use it as a double gate it is not merely the channel current doubles it is much more than that because the entire volume is conducting not only entire volume is conducting the charges are confined to the center of the channel that portion is there we will see that. So, what is made out here is do not worry about all this number of lines which are drawn this is a front gate this is a back gate oxide this is explained this phenomena. Now, if the front gate is inverted the potential is plus here going down to 0 usually you support it from plus down like that, but now we are putting this way this is energy band diagram this is equivalent of energy band diagram electron energy plus here minus here potential is 0 there potential is plus here this we have this is that double gate operation single gate operation. Now, you can see when you make it thinner there will be quantization effects etcetera that is there will be splitting of energy levels more than that if you solve the Schrodinger equation and Poisson's equation together the and estimate the carrier concentration if I do not use the Schrodinger equation if I do not take the quantum effect this is the carrier distribution because potential is maximum here minimum here maximum here where it is potential is maximum carrier concentration is maximum dotted line here I hope you are able to see that maximum minimum maximum that is the carrier distribution electron concentration, but your quantum theory tells you that if there is a potential hill from here to there what is the potential hill you have the potential hill corresponding to that. So, you have the if I talk the channel this is oxide that is oxide band gap if you see you have of course, here you have got the band gap like this this is the conduction band of this is the E G of oxide this is E G of silicon. So, you have got this is like a potential well. So, electrons get confined to this middle because what is the probability of occupation at this point if the potential hill is very high I think I have just drawn that there is double line there is a matter if the potential hill is very high the probability occupation is 0, but this is a finite potential from here to here. So, the probability of finding the electron here the probability of finding the electron here is low compared to finding the l o compared to probability of finding it here. So, electrons will not be occupying it here. So, instead of electron distribution being like this instead of electron distribution being like this, it will go like that, that is classical. Now, what it will be? It will be 0 here, it will go like that. So, electrons are confined to the middle of the channel. If the electrons are confined to the middle of the channel, what is the advantage? I have shown this to a different scale. It may go beyond that. These electrons here in the middle do not get scattered by the surface. This is surface of silicon, surface of silicon. They do not get scattered. Therefore, the mobilities at the center get scattered less. Mobility is better because of that. Mobility is better when it is like this. The current is much more than the current when it is like this. See here, that is seen in the, that is what is shown here. The electrons are here. The other curves are all finding out for each wave function. This is the electron distribution like that. It is almost flat here. Here it is 0. So, electrons are confined here. I have shown it in a different scale there in the previous diagram. What I have drawn? This is the electron distribution. This is the classical solution. So, here electrons are getting more in the nearer surface. They get scattered. Here most of the electrons are at the middle. They are not scattering. Because of that, you get the transfer and retains much better when you connect them in a double gate operation. Much more than what only one is conducting there. So, this is again reemphasizing the same thing. Single gate, double gate and you have seen the electric fields here and this is the electron concentration here and electric field in the case of double gate, electric field in the case of single gate. This is reemphasizing that. Now, let us see further. What we saw was if we keep on reducing the channel thickness. In the previous slides, we saw that the threshold would be keeps on reducing. We saw in one of those slides that when we kept on reducing that it came from doped on doped, then threshold would be come down low value. Now, when you go to smaller and smaller channel length like 10 nanometers and below, threshold voltage begins to increase. It is not a good news because you want the threshold voltage to be low, so that you enable low voltage operation. Why is that threshold voltage increasing? Threshold voltage increases because I have shown this potential here. This is the oxide. This is the oxide and the silicon thickness is this much. Your, the conduction band edge will be like that or the energy level will be corresponding that. All the energy levels will get shifted up. See, if a quantum well is actually like this and if you reduce it, all the energy levels, even the ground level will be shifted up. The energy levels corresponding to a smaller well will be higher up. So, whatever energy level is there, ground level, E naught, the zero level, ground level will get shifted up. If the ground level is shifted up, it requires more energy for electrons to be raised to the conduction band. Therefore, the threshold voltage goes up because you have to have more energy. That means, more voltage must be applied to raise the electron to that higher level. So, that is why when you go to thicknesses like 10 nanometers or below, threshold voltage goes up. This is seen in single gate. Single gate also has some confinement. See here. There is a confinement here because there is oxide here. So, you get, even in single gate, you will get threshold voltage increase there. We are concerned about this double gate MOSFET and SOI, where threshold voltage go down, finally increase because of quantum confinement. So, now, we have worked out some theory on that, analyzed it using the quantum analysis. This delta E naught, how much is that delta E naught is a measure of how much is the shifting threshold voltage. So, the delta E naught, what they have seen is up to about 5 nanometers, not much change in delta E naught. It is there, but if I reduce this thickness, I have put it as A, it is T-silicon. This is oxide band gap. Conduction band of oxide is here. If I reduce this thickness, keep on reducing, bring it below 4, 3, 2, etcetera. Below 3 nanometers, that energy level keeps on going up. That means, your threshold voltage will keep on increasing by so many millivolts per nanometer. It will rise quite steeply.  So, volts per nanometer, reduction here. If it is 3 nanometer, 2 nanometer, it will reduce, it goes up drastically. Why should you worry about that? One thing is, you do not like that to increase. More than that, can you make, see what we said is, keep on reducing the thickness. Threshold voltage keeps on falling. That is good, but if you go to 3 nanometers, etcetera, because of this effect, threshold voltage will increase. You may not mind if it remains constant flat there, but it increases. It is bad news from two points of view. One, threshold voltage is high means your supply voltage must be high. Second one, you go to 3 nanometer thin S O L air. You know how hard it is to get 3 nanometers uniform only over the entire wafer thickness? 4 nano, 4 micro, 4 inch, that is 100 millimetre diameter S O L air or if you want to talk of 8 inch, across that entire wafer, it is really difficult to get uniformity of 3 nanometer. There may be 3 nanometer, 2.5, 2.8 like that at least. Then you can see it goes up like that. Threshold voltage goes up. If there is 2 nanometer of few choose, then if it becomes 1 nanometer, you can see tremendous amount of change in the threshold voltage. So, your entire digital circuit will be all functioning there. Analog circuit, no hope. So, the uniformity in the threshold voltage will be affected if you go to thinner. So, what you are telling is, we saw in the previous slide here, we saw if you go to thinner and thinner silicon, here in this case, this was giving 1.5 nanometer. The question is, we can go to very small channel length there, but the question is, where we can really get that thought of uniformity.  Smart cut, you implant the ions at exactly at the region where you want to cleave it. So, you can get that thing about that value you can get, but it becomes more difficult. So, you can get, go to shorter channel length, if you go to smaller thicknesses, but there is a limit up to which you can go to shorter channel length. So, that is what I am trying to give you the message that, do not think that you can go to 5 nanometer etcetera of this approach, because then your thickness of the silicon must be even going to 1 nanometer, which is very difficult to get uniformity. So, there are varieties of SOI devices that you can get. This is the bulk MOSFET, where you choose all these doping things are there. CMOS, if you have to do, you have to have trench, isolation etcetera. And this is the ultrathin body MOSFET. I can use single gate, it is from the top side itself. That is suitable for making, may be integrated circuit, but you can see the difficulty there, you have to go to this type of arrangement. Here if I have like this, see the difficulty. You say you can make ultrathin or double gate. Now, if I make a double gate like this, this is the SOI layer. I will have oxide everywhere. I must edge the gate from top and bottom like this. I leave not possible to realize the integrated circuit, but in one wafer, you have got from one end to the other end, you have got the wafer, whole thing is connected to one. This is one gate here, that entire thing will be one gate.  It is not a viable solution. So, the viable solution is go to this. That is the FinFET. In the FinFET, what you have is, I can show a bigger diagram. This is the one which you can integrate. In the FinFET, you have the buried oxide. Below that you have got the handle wafer. You have got this source region here, yellow and you have got some oxide layer on the top of that, but the yellow is the source region N plus. You have that shape here and by lithography, you define this region. The SOI is edge from this region that is shown by this here. Now, this is the region between the two. You make this pad big here so that you can contact, get contact to the source and ring by lithography etching the oxide from these portions. This layer is actually the fin, which I can show it like this. If I take the, go from this, this is the, this portion is between this blue and this blue. A thin fin there, maybe we can show it to you like this. If I have a fin like this, like that, there I have the source, here I have the source and this is the fin. I can make it very thin. See, I can make it very thin. How can I make it very thin? By lithography. I can have one nanometer lithography. Electron beam lithography I can do. I can make it very thin. So, your problem of thickness reduction is sorted out here by making that fin. Here it will be like that perpendicular. So, I can maybe, I do not know, I can draw it separately here. See here. What I have is a fin like this. That is the, that is the cross section when I take the area, you get it like this. This is the silicon layer, a soil layer. Across that, I have this oxide. Now, this thickness, this was the soil layer, thickness of the soil layer. Actually, the soil layer and this is equivalent of that thickness of the soil layer, which we are talking of, front gate, back gate. There is a gate also here. All around there is a gate. So, I think I have to go all around. I have got the gate here. So, you have got the metal oxide semiconductor, metal oxide semiconductor. If I take a cross section of the gate, so let us just see that. But it is going perpendicular to this particular plane like that. So, my source is here. So, if you go to the diagram, we will see that clearly. So, what I have shown is this. The gate is going around that. So, you can see here. From the source to drain, there is a fin, a thin layer here, perpendicular to that like that. So, it is like that. Now, surrounding that, you have got this gate. What is the W for this case? Channel width. The channel width is, channel width will be this whole thing, that is the width. Channel length is like that. It is going like this. Source is on here. Enthus is here. Enthus is on this side. So, your gate is going like this. Usually, you have the channel width like that going. Source is here. That is here. And your oxide here, that is the W. Now, this is not like this. Source is here, drain is here. And that is the W here. So, thickness, twice the thickness of the SOL here plus that width. And this width is equivalent of two gates on both sides, compressing it. So, electrons are confined to this portion completely. So, you get total volume inversion in this case. So, I hope that is clear. So, this is a gate. Red is a gate metal, which is surrounding this portion like this. Now, I have shown here one fin going like this. There are more than 1, 2, 3 fins parallelly. Between this source and this drain, this figure shows only one fin. I have more than one fin, 1, 2, 3, if I have there. Then, you can have, if I take the cross section here, cross section here. If I had only one fin, I would have seen this. This is a fin. One fin, I would have seen the gate going like that. The diagram, which I have shown before. If I have 1, 2, 3, you have got W is increased by that, because I think it is not clear, looks like. I will just have time enough to go through that. See, what we are talking of is, you have got between the source, between the source and the drain point. There is a small fin there. If I have, sorry, I have, I will just remove that, remove that also. I will go into that. That is the point. Now, I have got this. That is the one. I have got here like this. I have got one fin like this, another fin like this, number of them. If I take a gate is like this. Now, you can see that, this gate, which I have put as red there, crossing this, crossing that. I take a cross section here. Then, I will see one here, one like that. That is what I am trying to show here. So, I take more number of them and you get more than one fin there. So, if I have only one fin, W is corresponding to that. Now, it is 1, 2, 3 fins are there. You can increase the current by putting more number of, equal to more number of channels in parallel. So, that is the idea about that. In summary, what we have got is fully depleted MOS devices have several inherent advantages over the conventional bulk MOSFET. Now, like low threshold voltage, ideal subsurface load swing, improved low field mobility, etcetera. And, SOILM wafers are also being increasingly used for other applications. For example, MEMS. How can you use it for MEMS? Micro retro mechanical system, I can realize a membrane. That can be done like this. I can use it for MEMS by to realize a membrane. For example, I can use an SOIL here. There is a SOIL here. There is a silicon. And, if I have an oxide here, that is SOIL. I can etch silicon from backside by using, I think I can put this. I can etch it like this. Either like this or vertically. But, chemical etching if I use, it will go like that. Vertically I can etch. This is SO2. I can etch it. Means, actually what will happen after etching? You will have this gone. Oh, my God. So, what you will have will be the, this will be like this. You will get it like that. I can etch the whole thing like this. So, the advantage is by the time the SOIL layer is reached, etching stops. KOH etching if you are using, it would not attack silicon dioxide. If I am using DRI, you will get a shape like this vertically, deep react to etching. Then, you will have a silicon here, silicon here. It will stop etching here. What is the advantage? Whatever silicon thickness is here, serous as a membrane. This will be very thin, say 0.5 micrometers. This can be 10 micrometers. I will membrane created as a 10 micron. I can use it for sensing purposes. That is why I said you can use it for MEMS. Very lot, lot, more and more number of people are using this device for using it for MEMS. And for radiation, hydrogen device also they use it because when you have a layer like that, whatever radiation impinges, it will cross this layer and whatever electron hole pairs are generated will go to the substrate. It will not generate carriers here. So, that is why radiation hydrogen device also are used. You think that is why. Now, we also saw that you can use integration. You can have number of these devices isolated together to make integrated circuits. CMOS, I can have P-channel, N-channel, etcetera using this pin fit configuration. Now, there are number of papers which I have cited here like which I have appeared over several years. And I have just put here 2006 as the one that you know that some of those figures which I had given done by some of our students myself. And you can add to this one. Now, today onwards, journal of applied physics which were the threshold water definition is there. So, with that I think I will stop the SOI discussion. We will go into the metal source strain type of junctions. We will discuss that in next lecture.