Hello everyone welcome to the first lab of time-time in this lab I will focus on I will I have an example RTL on which I will demonstrate the use of timing acceptance mostly we will talk about false path then we will talk about case and it will be the use of virtual block in exceptions and so on and then we will look at some pre layout timing reports we will try and I will try and point out the most important things that we will take proper layout report going to post layout. So we talked about this example in the session with the last session this is an example where it is a completely combination of the there is another there is a select pin which selects which of the signal from A or A and B or C or D goes forward the first output is E the second output is F so this output is E this output is F and if S is 0 the positive that is F is 0 A and C go forward they get added together and the output goes to E F is 0 if S is 1 then B plus D go on to F and E is 0 so I have written the RTL and synthesize it so the RTL let us look at the RTL very simple so this is the RTL where module name is example inputs these are 4 bit inputs ADPD input select output ENF output is 1 bit higher to take care of the carry bit and I have declared 2 wires 10 0 and 10 1 represent the 2 modules so if cell is 1 it gets B otherwise it gets A if cell is 10 1 gets B if cell is 1 otherwise it gets C so these 2 temp wires represent the module these modules the module selects between A and B and B and then there is a adder here the temporary sum 10 0 plus 10 1 and then assign E based on if select is 1 then E gets 0 otherwise it gets the sum if F gets the sum if cell is 1 otherwise it gets 0 so these 2 assign statements in the end they represent this this ending logic so I have synthesized this now now this is a completely combination logic you could choose one of the two strategies to constrain it you could either set a max delay on this on so what I did was I set a max delay off to NS from all inputs to all outputs and I synthesized it completely you could also choose to declare virtual clock and give input and output delays with respect to that virtual clock it is exactly same as the max delay when it comes to synthesis. So I have written out the gate level netlifts we go to work so this is the gate level netlifts and this is the BDC so I will just instead we will just start PT shell PT shell is exactly I mean in terms of the user interface and the most of the commands PT and DPR screen so DC by default read version of this setup PT by default reads version of so if you want to put any default commands any default settings that you want prime time to load up right at the start you can put all of this into the version of this so we just invoke time time here the header tells us what all licenses are available prime time time time time si is cost signal integrated and time time PHS for power analysis you can do report power and do all sorts of power analysis. Now once again the link library the search path these all are seen the only thing so I will set the search path in the link library first and then see there is no although there is a variable called ok there is no concept of target library in time time because time time is not a simple tool so you just need to set the link library which means that all the library cells that are present in your design must be mapped to one of the cells present in the one of the libraries in the link library so we have set link library to memory and standard cell in this case there is no memory in a design but does not matter so I will read to read the netlist of prime time is not used for reading the RTL it should be very very clear design compiler reads RTL that is simple prime time works on netlist so whenever you read in your design into prime time it has to be a netlist or you can even read DDC it supports reading of DDC so once you read DDC you will get the constraints also if you read so let us let me read DDC first so I will read DDC example dot base dot DDC so any database you read into prime time has to be simplified for DDC right so please do not confuse and try to read RTL it is no use so I have read that just to make sure we check the current design example now I do a link now this link process will make sure will tell us that whether all the cells inside this design are whether they are found in the library or not so once it when you do when you do link to load these DB files and it gives some information that so many cells are unused in some library this is all right this is for information sake obviously we will be using a subset of all the cells that are present in the standard library so it also sets up so this is a very important it is setting some default operating condition and default operating condition analysis mode we will look into more detail in one of this lecture sessions about the the analysis mode and operating condition but just make a note that operating condition analysis mode is set to on chip variation this is very very important for ST we will see this in detail in the other lab and one of the session so by default what PT is doing it is setting it is issuing this command set operating conditions minus analysis type on chip variation minus library this so it is picking up some operating condition from you could use a report design command to check the stuff it will tell you that analysis type is on chip variation I will be more detail on that later operating condition min name and max name are same because there is only one library we have read it reads the operating condition from the library which is the process is 0.99 temperature is 125 voltage is 0.95 it tells us what is the wire load model used wire load model is is area based automatic area based selection the pre type is best case so we are with now we are talking about the layout I have not read any parasitic data parasitic data is read using this command we have to take I am not going to use that for this particular map we will see this in the next lab so now what we could now what we want to do is we want to see what type of constraints are so the DDC has both netlets and constraints now this DDC was written at the time of synthesis so if you contain only synthesis there are not much here we can we can do a report timing and see or we could do a report constraints minus all while we could do a report constraints so I do report constraints so in fact prime time by default so if you do not if you issue any command for which prime time needs to so we did we linked the design and that is all we did not do anything beyond that so you have to do a you have to set up a give a command called update timing just this command to make prime time do direct calculation if you do not give this command and the first command you give which needs timing data prime time will do a update timing implicitly so here we see that as a as soon as I give report constraint minus were both prime time starts doing update time these messages are from update time so any constraint change that will force prime time to calculate timing again prime time will then run this command update timing by itself and for this it is it was to be quick but for with design a delay calculation takes a lot of time so you have to be careful when to so you have to be careful while changing constraints for a big design for a big chip and you should be prepared to wait for that long right so let us say the chips I work on the update timing will be take somewhere around 3 to 4 hours easily so we try to make sure that we do only do update timing only after we are very sure that all of the constraints in this have been so now here we see that report constraint is telling us that it is giving us the it is giving us the worst timing path the can also report if there is any clock there is no clock in the design so the only constraint is a max delay so we will say report so the only constraint we have is the maximum delay constraint what I can do I can also write sdc sdc synopsis design constraint file and from the ddc we wrote out the sdc let us see what sdc contains sdc will contain all the constraints that are it does it speaking up from the ddc so these are the this is the sdc version this is this command came from the default this is the default operating command that time-time issue and we see that this was the constraint that is coming from set max delay to from all input ports to all output and then the vialode model which is so some of the commands we did not give during synthesis but they are part of ddc because we have default cases like vialode model operating condition and units so they are written in ddc so we see that we see that what are the constraints that I gave in synthesis I gave an actually constraint now what I will do I will remove this constraint I will remove all the constraints whatever so a simple command to remove all the constraints is ddc design so this this means that if I read verilog netlist on one hand and if I read ddc on other hand and do a ddc design both are same we have written the design and we have removed the constraint in one case there are no constraints in the first case when we read ddc constraints are part of ddc but I have now cleaned up cleaned up this is the design now let us do one thing let us try and report timing now so we know that timing from a to f is not correct because a to f path is not true it is a false path in the sense that there is no case where no functional case where there is the path exist from a to f c to f b to e and d to e but the end time being a static timing analysis does not assume any value on it so what I will do I will try to report timing from a a is a bus to f and see what happens so prime time awaited update timing it gives a message that no constraint path that means prime time does not find any constraint path in the design obviously it will not find we do not have any constraints now there is a variable which I said timing report unconstrained paths true now by default this is set to false and if this is set to false then prime time will not even report any unconstrained path but we still want to see the unconstrained path we want to see the path delay what fine constraint is not there but there are two paths delay calculation and timing constraint timing constraint not not there but I still want to see the path delay now I have cut this variable to prove and again do a report timing now I see a timing report so without assuming any delay on s any case on s select pin prime time will give me the I have not done anything now and it will give me the timing report from a to f right.  So, worst path ending at m starts from select now what I do I want to see 10 worst paths right. So, I want to see the path ending at f and top 10 paths top 10 in terms of order of decreasing path delay right. So, I do this and it gives me all 6 paths right give me number of paths now I want to see a path summary and not be full path so I will give minus path type summary. So, it gave me that this is a summary report start point end point slack start point is select end point is f slack is infinity because path is unconstrained right if the path is constraint it is report slack value here. So, I gave maximum 10 paths, but it is reporting only 5 let me see I can do minus from a ok now now see this now please note that let us consider f 0 now what I will do I will do specifically to f 0. Now, when I give max 10 max means that it is related to the end point that means max this max is a short form for max end points number of paths with unique end points in this case f 0 is just one end point. So, and there are a number of start points so there are paths from their timing paths from a to f, b to f, c to f, b to f, cell to f, but max path will report it will down the number of paths in terms of unique end points. So, in this case let us say I give f star there are 5 end points f 0, f 1, f 2, f 3 and f 4 and among all these start points it gave me the worst start point. So, the max controls the end points unique end points now I want to see that on f 0 for example, on f 0 so if I give f 0 and max any number greater than 1 does not matter because f 0 is one single end point right one single end point and it will give me it will from all these start points it will choose the worst start point. So, any number I give it will just report one path any number I give does not matter because there is only one end point ok. Now, I want to see multiple what if I want to see all these start points here I do not want I want all these start points that have paths to f 0 the option is called inverse. So, if I give inverse 5 now it will give me 5 paths this so this end point is fixed here it will give me the top 5 worst paths from all the group of start points in this case all the first 5 paths are from select. So, what I will do I will increase this number on new group stage ok still top 10 paths are from select I will increase this number to 50 and now I see this select to f b to f b to f what about a. So, there are there are so there are so many paths from I will say 100. So, we see that there is b there is cell there is a there is c. So, now we see all the path right. So, if you want to see you use max path if you want to see multiple if you want to see the worst path your particular end point use max and you want more than one end points in your tiny report use max path. However, if for a particular end point you want to see more than one start point use the option inverse please read the manual of report timing and read about the max path and the inverse path this is very very important to understand how report timing works right. So, max path it will for a particular end point if you choose the worst start point and show you if you give inverse more than one for a particular end point it will report let us say if you choose a inverse file it will report 5 start points ending at this end end point if those 5 start point exist. Now in this case consider this a is of 4 bits b is of 4 bits c is of 4 bits b is of 4 bits right 16 plus 1 select 17. So, each bit of f and e has 17 start points. So, there will be minimum 17 start points, but we see that select has so many paths why because because of a good amount of combination logic here you will have rise path you will have falls path for example, let me now report a detail timing report and do just inverse 2. I want to see the worst two timing start points to f b. Now here we see that introduction is 0 because report we have not done anything path group is 1. Now we see that select in this calling it goes to u 26 y 28 y 29 23. So, both time timing reports look same, but there will be some difference let me just. So, here it is only reporting the output print. So, what I will do I will make it report the input prints also. So, here a 3 a 2 a 5 and fall fall fall fall for rise rise rise 26 a 2 y fall to rise 26 a 2 y fall to rise 28 80 to y 28 a 3 to y rise rise 29 a 2 to y 29 a 2 to y rise fall 23 a 5 to y fall and fall both timing reports you look same let me just expand it a bit. So, it looks like it is reporting multiple for there should be some difference what if I report next and now it will report next also. So, this is where you can expand this, but so, there will be a fall path all these are fall paths there will be also be a rise path somewhere in if you do more. So, there are so many paths from select you do a to y 15. So, once you start experience doing more experiments report timing in on the path the paths they are certainly differences in in terms of the transitions in terms of the which pin if the different timing path is going through. So, in the in the earlier case we saw that the timing report was same for all the path, but when we do unit pin now when we do unit pin time time will report it for the paths to paths let us say if then all the pins are same it will not report the other path. So, unique pins it will not report the data for you. So, now in this case let us see this let be the last two timing reports.  So, these two path are different although the delay is same, but the path is different and when it goes to post layout they will become still more different depending on what is the load on each of the pin what is the routing and so on. You could still expand you could still expand the significant digit number you could make it 15 and then it will expand it for you right. So, this is the way you work with report timing you have lot many options still you can choose through points and so on right. But important points now we saw here that prime time is reporting paths between A and F C and F D and E and D and E. Now, we do not want that now let us say this is part of a bigger design and we want to route out all the pulse paths like this. So, first we will try out a command called set case analysis. So, what we will do now we will work we will try and report time for both the cases individually. For the first case we have selected 0 for selected 0 F will be disabled there will be path from A and C. So, the path will be from A and C to E F will be 0 and obviously B and D will be blocked. So, what we will do we will set case analysis 0 on get quotes cell. Since we have constraints we will do update timing and prime time will give the message because it calculates update timing you can do a report case analysis to tell us what is the case analysis we said. So, we have set select to be 0 and now we report timing on F report timing minus 2 F and we see that nothing there is nothing since F any. So, so this is the AND gate. So, this is the AND gate controlling F if we set S to 0 this AND gate is disabled automatically right because AND gate the functionality such that if 1 is 0 the output is 0. Now prime time although it is not synthesis tool, but it understands the functionality because it reads the dot loop. So, it read the dot loop it knows the AND gate and it shows shows us that there is no pin internal pin or net feeding to F 0 it starts it as 0 and ends it as 0 that is it. What about E? So, E we see there is a path from A which is what we expect. So, what we will do we will say path type summary and we will start we will do a max path pipe and inverse of pipe to see a lot many paths. So, inverse is pipe is okay we will increase this tool it is 20 only E okay. So, we will still increase the inverse to see. So, there are all the paths looks like from A it should be path from C okay we see the path from A and C. So, we see that okay there are at any quick pin any E pin in this case it is E 3 there are paths from both A and C, but you can you can try now let us see what happens to the path from we saw that okay S is disabled there is no path to F. So, we will start prior report path from B I just start because B is a pass now we see that path starts from B 0 it goes to some cell, but now it stops. So, it would have happened somewhere here. So, now this marks might not be it is it is not represented as a marks in the gate level it is a logical description. So, looks like design compiler picked then AO22 cell and B is going to the AO22 cell and the path is stopping here which is expected because select setting select to 0 would disable this path again it would be same with D I guess it is same with D. So, in the net list a marks is represented by a group of combinational cells right. So, now I want to see the other keys I want to set the case analysis to one I do update timing and I will report timing from B and I see that B is going to F which is good I will do a report timing from B B is going to F which is good I will report try and report timing to E, but there is no time the there is no path from E because start point to B end point to B. So, no path to E E is disabled again I check from A and from B from C both the same they go to AO cell and stop there they do not go to the output. So, case analysis is a very nice way to analyze timing in two different modes by selecting some value on the selection. Now, what about the selection? We have set the selection to 0 in one case and we try to report timing from cell. There is no time there is no timing from cell because cell is not fixed value. Static timing analysis by default will assume no value on any pin once you set the value on any pin on any pin or report there with the timing through that and from that would be false why because that pin is set to a particular value it does not change right. So, this is how you you use set case analysis now what I will do I will show you a set a second way of doing thing which is using false path. In this particular example the disadvantage of setting case is that you need to set you need to do update timing after changing the value on set case analysis. In a single session with the case analysis in particular example you cannot see all the path that is A C to E and B D to F. So, what I will do? I will do a reset design again we will remove all the constraints and now what I will do is I use false paths now I know that path from A to F is false C to F is false B to E is false and D to F is false sorry D to E is false. So, I will set appropriate case analysis and appropriate false path I will say set false path minus from get quotes A all A minus 2 get quotes F this is one false path command A to F second I do C to F third I do B to E fourth I do B to E right. So, and I do update time. So, it will do update it will give some messages okay. Now I can see what expressions I have placed by the report expressions command. So, report exception tells me that there are false path from A to F C to F B to E and D to E it tells us whether the path is false for setup or hold it is since we did not give minus setup minus hold it is assuming the path is false for both right. So, report exception is one way of telling us what exceptions are applied. Now let us do a report timing minus 2 let us say F 0 and a very big inverse number of 50 let us say and I do a path type summary and see that the path is from cell B and D you cannot find a path from if I try to report timing minus from A let us say minus 2 F. So, in this case it is reporting this path A to F, but in this C what false path will do if you remember from the next example false path will remove any timing constraint on the false path and there was no timing constraint in the first place in this case why because there is no flaw there is no max delay what I can do is I can set max delay again that is to make it interesting minus from all inputs to all outputs. So, we see that the paths were unconstrained in the first place right A to F is already unconstrained and you applied a false path so it did not actually do anything. Case analysis on the other hand it allowed prime time to do some logic analysis and switch off both paths right, but false path is like telling trying time ok please do delay calculation, but do not worry taking and it was happening in the first case the same thing was happening in the first place there was no constraint. So, prime time did not actually do anything so what we will do we set a max delay constraint what about use for synthesis report false path is already in place we do a great timing and now we report timing from A to F. Now, the path is unconstrained which is ok, but path from what happened to path from B to F path from B to F is not unconstrained it is constrained path because we applied a max delay of 2 path starts from the end set as data arrival time is 0.62 max delay constraint is 2. So, it calculated it calculated the slack and now if you do a path type summary it will also give slack this will also give slack right. So, false path is when you have a constrained path and it is violating or it is not through even if it commit you can use false path right. So, I hope the distinction is clear between false path on case analysis I will do a reset design again and now I will tell you detail about how to use virtual clocks in this case and why virtual clocks are good right. Now, let us let us do one thing which we could have done for synthesis also. Now, what I know from this design is that path from path from A to E this particular path from A to E and C to E I say they block where they both belong to let us say I have assumed that they will belong to a clock domain called CLK 1 right CLK 1 and B to F and B to F belong to a clock domain called CLK 2. So, I will define two virtual clocks the reason will become very clear why. So, let me define two virtual clocks. So, I k set create clock minus period any any period I can give with the method work any period. So, I will just give a period 10 and I gave a name CLK 1. Now, I again create a clock called CLK 2 this. So, I create two virtual clock. Now, what I do is that how do I associate a clock with a port I define an input delay. So, what I will do I will define an input delay of 0 minus clock CLK 1 and I do this for the ports. So, this is how you give a list of ports A star C star because we we said that we said that A and C and E belong to same. So, I will set input delay on A and C using clock clock 1 input delay 0 and I using clock clock 2 on B on sorry B and B. So, A and C belong to the clock domain clock 1 B and D belong to the clock domain clock 2 then what I do is I set. So, I set I will set appropriate output delays. So, I set output delay now I will set a very tight value I want to see some violation in this case I see that the parts are usually in the range of 0.3 to 0.6. So, what I will do is let me set the output delay to be 10 minus clock clock 1 get both this is just because I want to see some violations I want to make things a little bit clear. List now output port I will So, I have set that A C and E belong to clock 1. So, there will be E here and I will give on clock 2 I will give B port F and do update time. So, now let us report timing now we have defined a clock clock 1 and on it we have defined input delay for A C and output delay for E. Similarly B D and F belong to the clock domain clock 2 I have not done anything else I will do report time now C. So, first of all it will report it will have 2 clock 2 path group now CLK 1 and CLK 2 CLK 1 E is associated with CLK 1 F is associated with CLK 2. So, let us see the first path first path path starts from input external delay 0 this is how we define path starts to cells 10 it goes through combination logic data arrival time is 0.66 clock 1 rise edge setup setup take the rise edge would be 1 period apart the capture edge. So, it is at 10 output external delay is 10. So, in what it means is that we did not use any time for the combination delay the input delay is 0 output delay is 10 the clock period is 10. So, there is nothing left for the combination delay. So, whatever is the path delay here it will violate by the same amount there is a since there is a sequential element involved. So, there is no setup margin. So, path delay is 0.66 slack is 0.66 clock group path group is clock 1 path group clock 2 10 and again path delay is 0.67 it violates by 0.67. Now, let us see some interesting timing report where we will see we will now report timing from now let us try to report the timing from A to F and see what happens. Now, we see that launches by clock 1 which is ok by a why because A has input delay with respect to clock 1 the capture is on clock 2 why because F is on clock 2 and we may report timing from way to F. So, again input external delay is 0 output external delay is 10 and the violation is there. So, now we see that path is getting reported from we can also try B to E again we see the path is from B to E which is fine this is what we expected. So, we just created clocks and by virtual clock we could constraint it. So, if we let us say keep the input delay to be 0 and make the output delay 9. So, it will give 1 nanosecond for the combination we can use this particular constraint for synthesis also, but now it becomes clear that A is on clock 1 C is on clock 1 B is on clock 2. So, A to F is false we know that. So, now if you apply a false path you will see that you will you can apply a false path here and you will not see now in this case the all the paths are constrained. So, what I will do I will apply this false path from A to F and I will report time from A to F now it will do update timing implicitly. So, it will do some update timing and now A to F is unconstrained. In the first phase it was constrained A to F I constrained this path and now I am setting a false path. So, now it shows me that this is unconstrained although it reports it reports the path delay, but tells me that path is unconstrained why because I have set a false path I will remove the false. So, this is the way you can use false path for constraint path if you if the path is already unconstrained false path is not of any use right and do a reset path reset path will remove any constraint from whatever option I give. So, I use the same options and I just report again to make sure that this is on. So, now what I will do I will do a more sophisticated analysis what I will do I will set false path minus from net flow. So, the advantage of creating two components here is that I can now do a false path between the clock. So, this command tells me in time that any path launching from clock clock 1 and capturing at clock 2 is false what are these kind of paths these are clock 1 launch A and C clock 2 capture is F. So, A to A and C to F is the false path this is what we are doing in one single command and we need to do the other way around all B and D to E. So, this is what we do wrong clock 2 to clock 1 is false. Now, let us try and report time from little path is unconstrained B to E path is unconstrained right what about we need to make sure that whatever accurate path whatever real group paths are there are getting reported for the try and report B to F we are good. So, earlier we had to give a false path for each set of inputs to each set of corresponding outputs. We had to give four set false path commands and let us say if you are designing want to expand your design you have multiple cases like this then you need to add so many other false path right. But in case of watch a clock what we have to do is just give two false path from it to other clock domain and this is this can easily scale up let us say you add more inputs here the number of inputs you add number of number of similar functionality you add you can again segregate this into virtual clock domains. This application of false path also applies to design who have real clocks and multiple clock. If you have real and multiple clocks if they are asynchronous you need to specify false path or use a set clock group command whatever both are both are fine. So, this so this was the focus of this particular part of the lab to get you acquainted with the exceptions. So, we saw case analysis use of case analysis use of false paths use of virtual clocks and again false paths to declare asynchronous path between two clock. What I will do is now I will show you an example of a disabled timing but it is disabled timing is comparatively less used when it goes to when we compare it against false path and multi cycle path I do not have any example of multi cycle path. So, let us first see try and analyze what is the fan out of selection report. So, what I will do is all the command called transitive form of minus from get quotes. So, this tells me what is the fan out of select. So, select goes to so many so many places why because it is expected by because select goes to this B sum of topics it goes to this where I am here and so on. Let us see from a 0 how many goes ok a 0 goes to so these are different levels of a 0 goes to U 28 from U 28 it stands out. So, a 0 goes to so any timing we do through report timing report timing minus from a 0 0 we can also know it from the timing report how this be. So, report timing from a 0 tells us this we can expand it we can do a minus if you want to see the transition in capacitance you can do the transition in capacitance again. So, we see transition in capacitance and if we do next we can also see a fan out now we see this is the fan out now this is very impressive. So, this tells me that a 0 port goes to a 0 net and the fan out is just one. So, a 0 goes to only this cell we also expand with a bit further by being in preference this is a more descriptive report a 0 goes to one cell it goes to the a 4 pin off U 28 it goes to a 2 and again further the fan out this fan out is 3 this fan out is 3. Now, let us say for some reason I do not want any path to a 0 any path for for me I for let us say in now the designer comes to me and says that the 0 is the term a is always grounded term I do not use this ever. So, one option is to set case 0 on a 0 which is good second thing you could do is you can set disabled time set disabled timing now set disabled timing the syntax is like this slightly different from other command set disabled timing we give minus from the pin name. So, here I give the pin name a 4 and so I want disabled timing from a 4 to 1. So, a 4 minus 2 y and off with cell of this particular cell which is U 28 now I will try and report timing from a and there is. So, it goes to a 4 U 28 a 4 and stops here why because path from a 4 to y is disabled. Now, this has one more consequence what happens is that now let us. So, a 0 2 to x 1 is a let us open a net list and look at the example 0.8.3 we will go to U 28 U 28 is this one it has 3 pins. So, it has 4 input pins A 1, A 2, A 3, and A 4 and one output in why A 0 is going to report as we saw. Now, this is a has 4 inputs. So, what prime time we will do in doing transition calculation in default case when the no exception is right the transition on n 5 will depend on the worst case transition among all the 4 input pins. So, prime time will only keep 2 values here right transition and fault transition for maximum inputs with the output 4 value, but if you remember wise transition depends on the transition on the load on y and transition on all A 1, A 2, A 3, and A 4, but time will not keep individual values for A 1, A 2, A 3, and A 4 for calculation of y.  Now, if you do false path through A 0 this does not change the transition at y, but if you do a disabled timing this change this transition at y. Why? Because for any disabled dot prime time will not use it for timing calculation. In this case we disabled timing off from A 4 to y. It means that now A 4 is out of question prime time will use the worst value among A 1, A 2, and A 3. So, this is the difference between false path and disabled timing affects delay calculation, false path does not affect delay calculation. False path only affects the timing checking the constraint checking the slack calculation. Disabled timing affects a lot more. Disabled timing affects the delay calculation as well. So, you need to be carefully you need to carefully understand the difference between disabled timing and false path from this point of view. So, use only when use disabled timing put in this in that sense disabled timing is much more dangerous. Saying set false path from A 0 and saying set disabled timing in the way we applied from A 4 to y of this particular cell. In both these cases the delay calculation changes. So, that is why disabled timing is a very very dangerous command. So, please use it carefully and before that first try and understand very clearly the difference between false path and disabled timing right ok. This was now let us I will exit prime time now for any for any command any output you can ok. Let me show you a couple of command any command if you want to report the you want to store this output you can store it in some by doing the output redirection you can store it in some file. You can open up temp.rpt and see that there then there is one command called report analysis coverage. Report analysis coverage will let us just give this and see what happens. So, report analysis coverage will give us a summary of the type of check total number of checks that are present in the design of such nature. How many are well met? How many are validated? How many are understood? So, this gives a very nice summary of your design how many checks are there? In this case in this case the only there are only two types of check output set up and output hold this out set up means this is checking is generally output via output delay. So, there is an out out out set up check means set up check for output delay out hold means set up hold check for output delay. They are total 10 by they are 10 5 pins of E and 5 pins of F total 10. So, there are 10 places where set up is check all set up is violated all hold is met how many are untested 0. So, this if you have lot of untested here you need to be very very sure about it what is untested and why is it untested. So, this gives a very good measure of what all checks are being done in your session and how many are tested how many are met let us look at one time in report of hold also. So, I will just review what I did in design compiler also when I do a report timing by default it will give me the worst violating path in each path group where it gives me two paths because they are two path group first is clock 1 second is clock 2 if by default path type is nice that means the set up check how do you know if the set up check because launches at 0 captures at 10 they are 1 clock period apart it is a set up check. If I want to report hold I do a delay mean again it gives me two reports one for each clock group path group clock 1 path type mean mean mean with the hold report the launch and capture edges are same exactly same we will worry about this as output external layer later do not worry about the negative value I will talk about this later in the other lab. So, this is the hold timing report and yeah so please make sure that you understand the difference between set up report and hold timing report in terms of launch and capture it right okay we already we all know what is the report with what is the come out the report clock same command like report port works here also we do a report port minus verbose and it will tell us at each port what is the output delay what is the input transition what is the input delay and so on. So, it gives us detail about all this now when you are working on a big design or a big chip you have applied you have read in the necklace you have applied the constraints you have done update timing and you are doing some analysis now you want to continue this work the next thing but you want to quit time time and you know that your update timing takes few hours right. So, you do not want to again come back tomorrow do everything wait for few hours right. So, you can save a session so I can save us to the command call save session I can save a session and I have to just give so it it has an option of including noise data also in this case we are not worrying worried about the noise data and it can also save libraries but we I am at this point of time I do not want to save library because library is not changing for me. So, if the library is not changing for me I can choose not to write out the library to reduce the. So, this this file can be produced the session file can be produced. So, you need to make sure you need to be very sure about what data you want to create. So, in my case I just want to save the timing data. So, what I will do I do a save session and I do I give a name called my session it will save netlist information environmental conditions, timing information and all those right. Now I exit it again open time time and now I can do a restore session on my session it will and now update timing is already done because it saved all the data right. So, it does not need to calculate the timing values again. Now I can simply go ahead and do a restore timing without any delay right. So, obviously it is not apparent in such a small state but when you have a big design and a big chip you are working on this personality is very very useful we make use of it all the time right in save the session. So, you can even save the session and point out to some other engineer you can load the session. So, on a big chip at one time on full chip SCA there are more than one people working right. So, all of them you can save a session you can give it to other engineer and you can use that restore that and do analysis in time right. So, this was about the lab one where we concentrated on the timing acceptance. I am assuming that you still remember your create talk concepts from design compiler where remain in time time. In the next lab we will look at how to do post-sale timing analysis which is very very important right. It is the most important thing of the SCA. So, we will look at how do we read the post-sale of netlist, how do we read the parasitic, what checks do we do. So, we did lab one of design compiler we had a design we will use the same design, but now in this case it will be a post-sale of netlist and we will also use the parasitic right. Thank you.