So, welcome to this lecture on digital system design with PLDs and FPGA. In the last lecture we have seen a case study what we have seen is and we have seen the design of an 8 bit unsigned integer multiplier. I said you can extend that design. So, we have seen the algorithm, we have modified the basic algorithm, we have seen resources, we have seen the data path design at the top level, then each block we have expanded. And we have also parallely seen the VHDL code for it. We have designed the state diagram, then we have put together everything together in a VHDL code and some kind of you know concise way of writing the VHDL code and all that. Today and that has you know kind of winding up everything in the course you can extend that. And today I want to show you the FPGA tool and the same exercise on FPGA kit or FPGA board on a Spartan 6 board. But at the beginning I will show you the Xilinx ICE or ISC integrated you know system environment where we can do everything. You know we can do synthesis, bison route simulation, the programming of the FPGA timing simulation, timing analysis all that. I want to straight away go to the tool and show you with some simple example one combinational and one sequential. Then we will go to the real design wherein I will not simulate it because it is cumbersome to simulate it. I will just show you the program on the board.  So when you take when you install this program on the computer and you will have some you know the Xilinx ICE design suite 14.7 click on it. It is available in the program menu also maybe I will minimize it a bit ok. So that you can see it little bit full screen ok. I will make it resize it so that it is visible ok. So this is the tool and the latest tool from the Xilinx is called the Vivado which is only used for the 7 series, vertex 7 series devices. Since we are using some older devices we will use this particular Xilinx ICE and see this is the area where all the files and the related process will be shown. This is the area where all the opened you know files, waveforms, statistics everything will be shown and this area is a console where all the messages you know the process messages, errors, warning everything comes ok. So first thing is to start a project ok. Every problem is associated with a project. So we will open a project say new project. So let us you choose a directory to put that and I will choose some predefined directory. Say let us take a very simple example the equality comparator we have developed. So let us call it eq comp this was the first exercise we have looked at the VHDL. So this is the name, this is the location and all that and you say next and here very important is to choose the device family, device name and the package. You know that you have to choose very properly and this is the synthesis tool, simulator, what is the preferred language and all that and all that can be chosen you say next and you say finish. Now you can see that this is the project area where all the files will be shown. Now depending on what you choose here what all you can do the processes will be shown here ok. So first thing is to create a VHDL program and there are two ways of doing it. If you already have it you can right click and add source or you can create one say let us create one you know let a simple one let us create. Say new source and it opens up a menu for you and there are different files you can create like test bench, VHDL design, verilog design and all that.  Let us call it eq.com again ok and say that is the file name of the VHDL ok we say add to project should be ticked we say next and now this gives a template instead of creating your file from you know from the beginning you can create it with a template. So it is already giving the entity name as eq.com architecture name as behavioral and it allows you to kind of generate ports. So let us call this port as a ok and that is a bus which is you know if you remember this is a 3 down to 0 ok it is 3 down to 0. Similarly we create a B which is input mode and this is also a 3 down to 0 ok. So and we have an output which is called let us call eq which is you select it is an out and it is a single bit. So do not do anything that is it and you set finish. See now you see that it has created for you a template code library and the use declaration the entity with all the ports a, b is a 4 bit vectors input port equal is out architecture is written here with a begin just write here the code you know say eq get shift 1 when a equal to b ok else 0 ok. So that is how ok that is a code ok so that is what is written here ok and now maybe I hope you can see that I have zoomed in if this is visible ok. So I hope you can see that now. So this is you see the entity architecture we say eq which is a output port gets 1 when a equal to b maybe you can give some space for readability. Now you say save ok it is saved. Now you select that the file now you see we have 2 option one is implementation one is simulation when you do implementation it will show the synthesis place and route all that you know the programming and all that. So here you see the moment I have selected that you know there are various you know you can specify the constraint you can synthesize you can implement and all that. Let us click open the synthesize and if you right click on it then there are lot of properties which you can go through there are synthesis option, HDL option, siling specific option. So there are lot of options you have you can choose it whether you can optimize for area, optimize for speed or you can kind of certain inferences like automatically whether the maxes are to be inferred all that can be chosen. Now the first thing to do is that you have to check the syntax ok. So let us introduce an error saying like this you know I will write like this double equal and I will save it and I say check so you can see that already it is flagging an error here which say that a syntax error near equal and I just click on the light and it shows what is the place where it is error. So I just delete that and save it and it automatically checks and it say that it is the parsing is completed. So if you want to double check you can say check syntax use a run so it takes a while to do that and it will show a lot of messages here ok.  So it will synthesize the following code ok that is what it is going to do and while it is doing it will show messages here. It is already showing a delay of 6.5 nanoseconds. So while synthesizing itself it knows that what are the resources used in FPGA so it estimate the delay and show it here ok. So here what you can do is that you can say in the process say if you click the sigma it shows the design summary ok. So it shows that number of lookup table used are 2 and the number of IO pins used are 9 because we have a 4 bit equality comparator there will be 2 lookup tables used we will see that and the number of pins because there are 2, 4 inputs and 1 bit output ok. So that makes it 9 and one way of seeing what is synthesized is viewing this RTL schematic. So if you click it you say start with the top level block you can say ok and that is the schematic of the what is inferred and you can just so it is detected as a comparator. So it is showing say A3 down to 0, B3 down to 0 it is an equal operator and the equal comes out because it is recognized so it is showing as a block ok. So another thing is that you can check the technology schematic wherein it will show how it is implemented within FPGA ok. So you go here and you say zoom to the thing and now you can see that these all are input buffers like A this is the signal like let me see what is the signal there that is A and this is B. So there are this is A is buffered and given to a lookup table B is buffered and given to a lookup table we can zoom in on that you know you can just so this is the lookup table which is going and you can click on that and you see you can see the internal the circuitry. And if you see the equation it will be a kind of XOR which is comparison and you can see the truth table say when it is you see it is 1 when it is you know when some pattern is there you can analyze that it depends and shows the kernel map of the optimization all that detail can be seen it is very useful learning exercise also. So once you have done that you know you have done the synthesis they can then you can go for implement the design so you just say run. So it will do something called translate map and the place and route ok. So it takes a while lot of things are done and that messages come here in the console and mind you this the utilization everything is updated in a quite a lot. So you can watch that what is going on here. So it is done now all that is done and you can see very elaborate statistics are written here. So there is nothing much because it is a simple design say registers 0 there we are not using any flip flop lookup table is 2 all that you know there is nothing much other than that is available here. A lot of resources none of like PLL DSP blogs nothing is used we have very simple example and I have chosen a ok this is a Spartan 6 device which I have chosen maybe I can change it to maybe Spartan 3 ok that because say I will change it to Spartan 3 let me see Spartan 3e because that is similar to the vertex we have discussed in the class so that we get some when we see inside we will have some familiarity with the lookup table and all that. So I have chosen now the Spartan 3e which is similar to the vertex we have learned in the class. So earlier what was default was Spartan 6 so I have changed it so that we can when we see the resources when we see look into the router design we become kind of you are comfortable ok that is done the first thing to do is that we can open this place and route and let us go and see the static timing analysis ok this shows the analyze post place route static timing. So click on it and you can see this one ok maybe I will magnify it so you can see that it is reporting the delay say source pad it is a pad to pad it is a combinational circuit so input pad to output pad so A02 equal it is 6.476 nanosecond similarly A1, A2, A3, B0, B1, B2, B3 all the paths are chosen I mean shown and the maximum delay reported here is 6.98 nanosecond which is somewhat similar to what is reported during the synthesis so that is quite correct. Another useful thing you can do is that you can look at the router design within the FPGA. So you click this particular menu view edit router design so if you click that ok this window shows the whole FPGA ok this is the whole FPGA with the IO pins around all the slices and the DSP blogs the memory everything you know special resources so you see some gaps and all that ok that is that so and it shows you know where are the where are the signals suppose I click on that it shows where is that IO pad is coming ok so you click on that that is the picture of the IO block of this particular device and which is ok so that shows IO block ok and one can zoom where is zoom ok so this one shows that IO block ok this is the pad these are the buffers and all that you know input it is an input so it input is coming. And now sorry I will open that again ok let us look at this particular so there are two slices used so let me click on that so you can see that this is the look table used there are say this particular slice is used because we need two lookup table and this is a slice used so you click on that and now you can see that particular picture we have seen the detail view of the slice so you see here so this is the one lookup table which is used you can see let us magnify it so you see B3 and A3 A2 and B2 are going. So this is a comparison of A2 B2 A3 B3 and you know combining them two so this is this implements say A3 XOR B3 A2 XOR or A3 XNOR B3 and A2 XNOR B2 so that is the logic implemented here in this particular thing similarly you can you know so this shows you know the various the architecture of the slice and if you remember if you care to remember these are the two lookup table two flip flops this is the carry chain so all that can be kind of you know looked at and you can clear your doubt it is very useful it is not only designing you can see very detailed picture of what is going on within FPGA. So let us now do a simulation okay now for simulation you can write a create a test bench as I have shown earlier like maybe you can say a new source okay and you can select a VHDL test bench okay and you say give some name say let us call it EQTB test bench it will show which is the entity to be assigned so it is showing EQCOM because there is only one entity there are multiple entity architecture you have to choose whichever one you are trying to simulate mostly the top level component say next say finish okay. Now what good thing is that again this tool will create a template code for you that I will magnify it okay so that is the library function this is the empty entity this is the equality comparator instantiated these are the sorry declared signal declaration this is the kind of instantiation. So it involves a clock which we will command it which we do not require so this is a clock process again this is not required so we will command it okay and there is a wait for clock period that also we will command it and here we can insert the stimulus okay. So I will just show a very simple thing A gets a say 0, 0, 1, 0 okay now both are 0 at the beginning and I will say wait for some time okay I will say wait for wait for 50 nanosecond and I will change maybe A back to 0 again so that you get equality okay and so on okay you can give delay sorry that has not come what happened okay fine okay. So just save it now the test bench is ready now what we do is that you have to select the simulation select this test bench and you see now you see this is the simulator isim simulator click open do a syntax tech okay. Now you can right click on the simulate behavioral you can see there are a lot of properties it in the default it runs only for 1000 nanosecond you can extend it if you want but our thing it is okay and also most simulation will have a whole state for 100 nanosecond to simulate the FPGA programming time so you should assign only the input signal after a 100 nanosecond delay. So now you click simulate behavioral model so it shows a window waveform window so that you can click open and you can zoom to this thing and you can see this you can select the radix as a unsigned decimal. So initially both were 00 and you can we can zoom in okay let us zoom in say here both inputs were 0 so the equality output was 1 that we made something for 2 the one of the input as 2 then the equality goes low then again we made it 0 it goes up okay. And this is a marker which shows the timing suppose you want to latch this on to the to this edge you click on this it latches you want to insert another marker say you say markers and add marker so you get another marker and you can move that any number of marker and it shows the you can measure the time in between and you can choose lot of things I think you can play with it that is what is this symbol combinational circuit I want to stop here. So let me close this and I will show you a sequential circuit a symbol counter which again we have discussed in the class what we have done was a 8-bit counter with a synchronous load okay when the load signal is high it gets loaded with some value so I just want to bring that thing and show you that okay. So let me close this project I close this project and I will open a new project okay again I will call it count okay same thing spot in 3 it remembers that will be in your profile and we say finish now what I am going to do is I am not going to create a file I just add the source so I will add the source which I have it ready so say which is a count 8 which I opened so this is the file you know I will magnify it okay. So this is the library 11 package 1164 and unsigned this is the input clock reset load is input D in is the data input which is 8-bit count is output which is 8-bit so we have a Q because we have to use Q is Q plus 1 count is assigned with the Q this is a process where the counter is there if reset is 1 Q is others 0 else if clock event clock is equal to 1 then we introduce a synchronous load if load is 1 Q gets D in else Q gets Q plus 1 okay I have shown you everything this particular thing how it is in the size you refer back to the earlier lectures you get the picture okay. So I just want to show you synthesize so I want to synthesize this so I run that so that shows an quite a bit now this will have you see a sequential timing so register to register delay it will show all that let us look at the technology RTL schematic and okay now this has identified as a counter so it is not showing so it is inferred the counter maybe we can look at the technology schematic so that shows the whole scenario. So there are a lot of lookup tables because you know that we have when we learned FPGA we have said that an 8-bit counter will occupy 8 lookup the carry chain and this is a lookup table if you look at let us magnify that okay. So okay so this is the lookup table for this is for D in 0 so this is the lookup table for Q0 and this is a flip flop for the 0th bit and also you will have this is the XOR combining with the carry outside XOR and if you look at you will see the carry chain mux and all that okay here okay. So there will be this is for the 5th bit this is for the 6th bit and if you can find it all over you know this is for the 0th bit so all that is shown here and if you click on this lookup table it shows the truth table with that addition okay this is shown here so you can analyse that so I will not spend time with this now we can implement it okay. So now it is doing the place and route initially it does some process called map and translate map and now it is doing the static timing analysis and you can see the summary and you see there are number of flip flops used are 8 okay and number of lookup tables used are 8 and you know that there will be carry chain used so 8 lookup table 8 flip flop and it occupies 4 slices what I want to show is static timing analysis. So let us look at the static timing analysis okay now here you see there are various different things which I think is of some importance so first thing is called setup and hold to the clock okay. So this shows the data input and the load signal it shows what is the setup and hold time of each of the external input up to the flip flop because data in is going through some kind of combinational logic to the flip flop and it shows that the data in 0 as a setup time with respect to the pad 1.469 second and the hold time is 0.8 nanosecond. Similarly there is a clock to pad which we have discussed this shows that given the counter output it is like equal to Tcq but all the way up to a pin because the counter output is going to a pin so from the clock edge what is the delay all the way up to the pin not just at the output of the flip flop so that say count 0 is 7.2 nanosecond. Similarly this is a setup time of the input all the way with respect to the pin okay and this shows the clock to output with respect to the output pin okay. And the lastly what it shows is that it is the clock to setup that is nothing but a register to register delay so this shows the minimum clock period okay the minimum clock period is 2.97 nanosecond. So basically our counter will work with the 3 nanosecond clock period but you see the since it is placed within FPGA for the count out to come on the pin it takes 7 nanosecond okay. So even if you simulate at 3 nanosecond though the counter internally works properly the input will not reach in 3 nanosecond to the output so you will be forced to kind of simulate it at 7 nanosecond or run the design at 7 nanosecond or 8 nanosecond. Similarly setup time is not a big problem because it is only taking 1.5 nanosecond that can be setup you know the load as 2 nanosecond so still it is within the 3 clock period but there could be some all that combination delay is accommodated here. So this is something which you have to realize though the clock frequency can be high because of the delay to the pin you will be forced to choose the slowest of this as the clock period when you simulate it. But nevertheless that does not shows the your designs performance because many a times you are designing an IP where these outputs are not taken to a FPGA pin that is going to a nearby another circuit okay or you know for an advanced user this can be these pins can be assigned very close to the location where this logic is placed all that is possible. So in when you do the static timing analysis of sequential circuit you will have the setup time with respect to the pin which is called setup to clock and clock to pad tcq with respect to the clock and register to register delay okay. So I am not trying to since I have shown you the simulation I am not going to simulate that because we have to complete that our case study on this particular tool. So let us look at maybe you can you know you can look at the editor doubted design which you know say here you see you come down and you pick up a slice for the q0 then that slice come and you can see this is it and you can very clearly see the q0 coming here the q0 data in load which we have discussed how a single lookup table can accommodate the data in q0 and load you refer back to the class that is the lookup table and that is coming with the XOR gate and this is a carry chain wires maybe I will zoom out a bit to be able to see that so this is a carry input and this is the carry marks which is going to the next stage here to the lookup table okay. So this can be very well analyzed whatever I have shown in the earlier lectures that you can try it out and verify what I have shown is correct or your own ideas are correct. So at this point I will close this project and I will come back to the slides we have the case study we have done briefly to remind you. So what we have done was a multiplier and we had implemented you know the data path multiplicand result add a marks then a counter to keep track of the count controller then we have it expanded multiplicand register, multiplier register, counter the FSM and we have seen the state diagram and this was a code you know this was the big code and the multiplicand register multiplier, the multiplexer, higher product register, counter, decoder then the next side logic and output logic of FSM adder and the FSM flip flop that was a code okay. Now what I am going to do is that I am going to program this in an FPGA okay. Now this is a state diagram okay. Now the particular FPGA board I am going to use is this particular Xilinx okay sorry for this mistake it is X okay Xilinx Spartan 6 at least board and this board as a Spartan 6 FPGA which is 6x Lx45 which the package is CST 324 pin you know the board grid chip scale you know the grid. That means there is concentric squares beneath the chip with the pin and it has lot of things you know it is a very powerful board you have a clock we require everything something clock. You have some LEDs connected to some pins you have some buttons so that we can give some reset start there are slide switches all that and there is Ethernet, memory, USB, HDMI, audio codec and all that. But essentially we are going to use the clock source because we are going to do something with the clock and because the state machine need the clock then the LEDs to display the multiplier output button to give a start to the multiplier we have discussed that what is a start, start comes from the external thing. So that is how the FPGA board looks this is where the FPGA is this is the FPGA and you see lot of ports this is the audio port, USBs, this is the Ethernet ports and this is a flash memory and maybe these are the the HDMI port, this is a program port these are the slide switches where you can give 1 and 0s and these are surface mount LEDs 8 LEDs okay and these are the buttons you know there is a reset button and 5 buttons like cross where you can give a push button okay. Now we have to show the result of the multiplier so what I am going to do is that I am going to give the multiplicand fixed okay so within the program I am going to assign hard assign the multiplicand and within the program upper 4 bits of the multiplier is assigned hard but the lower bits I am taking from the slide switches okay. So I can choose the lower bit say up to say 0000 all the 402 all the 4 ones okay 002 ff in hex okay that can be changed and see the result because we are implementing we have implemented an 8 by 8 multiplication which is 16 bit. So these are sorry these are once again there are 8 LEDs okay not the 7 LEDs 8 LEDs what we are going to do is that we are going to multiplex the 16 bit onto this LED with the 0.125 hertz that means say once in 4 seconds it will show the most significant byte then the least significant byte okay. So we are using there is a inbuilt clock oscillator which is 50 megahertz we will implement a clock divider okay and that will generate a 0.125 hertz and that is used to multiplex this LEDs and this 50 megahertz can be used for the state machine of the controller and one other thing I am going to do is that I want to give a start signal okay. So I can use a push button there is a push button on the board say these buttons okay. Now the problem with the push button is that when you press it it is it does not make a clean contact okay it just goes and bounds you know like that is a picture shown initially it is 0. So when you press it kind of goes up and down and make a 1 okay. Now we need to debounce okay we need to remove this glitches otherwise it will start many times okay. So what we do is that we will sample so what we are trying to do is that we will sample with a clock period which is which has a period which is higher than this burst okay. So we have to have some sense how long this burst can occur but for the most good switches it will occur say around 20 millisecond like that okay even less. So sometime it can very bad switches big switches can have more chatter but we assume that it is around 20 millisecond. So we sample at two points and if there is a 0 and 1 clean 1 then we will you know make it as a start. So that is what is done by this is a flip flop you see here the input is going and we are giving a 20 millisecond clock and I am tapping one of the cues of the clock divider with appropriate you know waveform it need not be very correct because this will kind of it is a mode counter after sometime it is going to become 0. So the waveform will be little bit distorted but does not matter not a very serious thing. So what we are going to do is we are shifting that to the output and the earlier one comes here the current one is here. So we are looking if it is 0 and that is 1 then we get a pulse here okay which is of the duration of the clock period because when it is 0 and 1 this is happening with every kind of so you get a pulse here that is used as a start and this pulse is kind of little big of the 20 millisecond duration if you want to make it narrow we can resynchronize it but this is this pulse is of 20 millisecond duration that could be a problem because if it is very long our multiplier will you know complete it and restart again because the multiplier works very fast and there are when you sample you know strain things can happen suppose one edge comes here and one edge is here. So if you are lucky it is both are 0 if it is this is 0 this is anyway 0 this is 1 we got a 0 1 transition it may happen that is very clean you know we sample here 0 and 1 then it is a clean thing may be that you know we you sample it here if it is 0 then this will catch 1 if it is 1 the previous one would have been 0 so that will catch it. So anyway it works this de-clitching work decently but only thing is that it duration is 20 millisecond maybe you can put another flip flop with a 50 megahertz clock to get an aero pulse that is possible I am not shown that. So I have done a little change to the to the state diagram I know that the start is going to be long so what I did is that when we come to the final stage I remain there till the start goes low and come back here. So that is how I take care just to demonstrate but in real design you better put one more flip flop here with the same fashion same circuit which is clocked by 50 megahertz and you will on the transition you will get a single pulse of 20 nanosecond duration that should be enough for our controller because the controller also work with the 50 megahertz clock and that is the additional the code required for multiplexing. So I have some start signal start signal debouncing clock like this particular clock I am naming as ST clock and you see this is the hard assignment MC is assigned A5 the ML most significant 4 bits are assigned 4 and this is the ML 3 round 0 which is coming from the input pin and this is a constant which is representing the 50 megahertz or 50 megahertz into 4 to generate 0.125 and you can see how that counter works the divider upon the reset that huge 27 down to 0 is made 0 upon the clock it is incremented but if it reaches this particular number it is reset and to make a square wave we make a d clock which is 0 at the terminal count it is kind of toggle not d clock. So you get a divide by 2 out of that you know that is the counter and this is the LED multiplexing. So we are using this d clock when it is 1 r7 down to 0 goes to the display and else r15 down to 0 goes to the display and this is the d count 15 is for debouncing and you see that debouncing here if reset is 1 that is dst is 0 upon the clock dst get so that is representing this flip flop and this AND gate is written here say start is nothing but st and not dst okay and that start goes to the state machine and I have told you about the state machine change. So let us go to the program okay and let us move it and let us come here and open this thing I will open a new project let us call it multiplication mult okay. Now it is very important that you select the correct device as it is on that board which is part 6 the correct package should be chosen then only it will work because the pin numbers change depending on the package xc6 as lx45 now this is a package cst324 I will say next finish now I will add the source file let me add it I go up I will pick it up from okay I will cancel it I will copy add copy of the source I will go here that is the VHD file open and done okay. So that is a huge file it is quite a bit huge so you can see the library package multiplier then the architecture with signal and this is the constant for the counter and this is the various multiplicand register, multiplier register, multiplexer, higher product register, counter then decoder this is a counter for multiplier adder this is a next aid logic and the output logic of FSM and this is the FSM flip flops this is a multiplexing counter LED multiplexing this is a LED multiplexing and this is the start pulse generator okay. So old thing is there and now very important thing now is that when we do this kind of thing you have to assign the pin because we are going to now you see put this program into FPGA. This FPGA some of the pins are connected one of the pin is connected to the clock some pins are connected to LED so your signal should be mapped correctly to this and there is a way of doing it graphically but there is also a way of doing it to the by a file called UCF file. So that file you know you can say you can go to user constraint and you can say IO pin planning pre synthesis you can click it and you can assign it manually and will create that UCF file. But for convenience I will I have prepared that UCF file so I will pick it up from what is pre-prepared okay. I will copy that UCF file here so and that if you see the UCF file this is the syntax I will maybe you see that it shows that net clock location is L15 that means the signal clock for us is connected to the pin L15 because on the board this particular clock oscillator is connected to the pin L15. So we are tapping that clock similarly you see display is mapped to some pins this is where the LEDs are connected similarly the multiplier input is connected to some pins that is where the slide switches program and the start coming from a button reset coming from a button. So this is very important now I am not going to simulate I am just straight away going to generate the programming file. So it will do synthesis, place and route programming I mean generate the programming file everything is done it might give you some warning but it does not matter because I have done some kind of assignment which is may not be most optimum. So that is doing the place and route the translate, synthesize, translate, map place and route all that okay and it will show the design summary it is using the 53 registers okay and the lookup table is 96 because it is quite a big design and we are using lot of counters you know counter huge counter to generate that debound multiplexing signal the counter 8 bit counters lot of registers. So it is 53 registers and 96 lookup table it is using so it is done complete the static timing analysis but I would not go through the other part like all that let us try to program that. So before that I just want to show you what I have assigned the inputs say come here you see the multiplier, multiplicand is assigned a 5 hex number multiplier higher bit is assigned 4 okay. Now I want to show you the board so this is the particular board okay. So this is what the picture I have shown so this is the FPGA with the heat sink this is the power supply these are the slight switch. So I will keep this 4 bit at 0 these are the LEDs okay. Now what I am going to do I am going to program it so let us go back to the tool okay. So let us come back to the software so how do you program is that you click this and open that thing and you say configure target device and you say manage configuration project you click on it and make sure that the board is switched on you connect the power the programming is done through a USB cable okay and make sure that this is powered on.  So it is detected the FPGA now it asks whether you want to assign a configuration file you say yes and it will open up the correct bit file in the project you click on it you say open. I will ask another question for flash prompt say no say okay now right click and you say program and you can see that it is programming the board. Now let us look at this particular program is succeeded when that happens you can see there is an LED which is a green LED which is called a done that LED is glowing okay this particular LED is glowing now.  So now you can see that these LEDs are not lighted okay so I give a start pulse now you can see that LEDs are blinking which is A5 into 40 actually it is the real result is 2940. So maybe it is so small you cannot see from the camera but then it just shows the 2940 and if I can change the value say A5 and 4F and I give a start signal you can see these LEDs which is showing 32 and EB 32 is less lights and EB is more lights more lights now. So that is how you use the FPGA board by programming a lot more can be done I just want to show a quick kind of run through the tool. So we have seen today a simple combinational like thing we have seen the synthesis we have seen RTL schematic technology schematic static timing analysis inside the lookup table all that you know the all that detail we have seen as counter design a sequential design against static timing analysis. The whole case study we have with an additional some addition we have put the result on to the LED okay important thing to remember is that you have to do a PIN assignment and you can do something called a IO you have to do IO constraint maybe one thing which is reminding maybe come back to the tool you can do something called the timing constraints okay that I will quickly I will point out then you can play with it. So it is possible that you can specify the right timing. So here you see the create timing constraints and you can see that you can specify the clock period say the clock domains various clock the inputs outputs what is the setup time required what is the clock to output and you can group some pins and you can specify the setup time clock you know the period all that. So it is quite elaborate and when you do GUI this will be converted to the entries in the UCF file as timing constraint. So wherein you can achieve some timing performance you know you can say that your design should work at 5 nanosecond or 10 nanosecond or part of the design should work with 5 nanosecond another part by say 7 nanosecond all flexibilities are there that you can play with it but that is more to do the tool I suggest you go through a tutorial and get acquainted with that. So with this I am kind of completing the course I have covered you know the digital design very detailed how to design top down controller design issues then the VHDL for synthesis and the FPGA in detail how given a code how it maps to the RTL code how that really gets implemented within FPGA and we have wound up with a case study showing the tool showing it on FPGA board. So I hope that has been a good learning experience you can build on this you know I normally cover quite a lot in my course in the university I teach but I do not have time to cover all that and this was something committed at the beginning of the contract so I stuck to the syllabus. So please study well go through the material go through reference book work out lot of examples in the line I have suggested then you can master it you think you try to understand and then you can build on this basic which I have given I hope whoever as watching this watch this course will become an expert VLSI designer. So I wish you all the best and thank you.


Welcome to the Metal Voice and first time on the show, it's Buck. It's Buck Dharma from Blue Oyster Cult, so nice to have you. Not looking very metal today, but that's me. It's all good, my friend. The good news is, a Blue Oyster Cult coming out with a new album, Ghost Story is going to come out on April the 12th on Frontier's Music, a reimagined, newly completed songs that span from 1978 to 2016. That's pretty incredible. I mean, who's idea was this to take all the tracks from the past and sort of twist them and turn them and AI them and make them into songs today? Yeah. Well, BOC historically didn't record a lot of extra material that didn't fit on vinyl LP, which had a run time of about 40 minutes maximum. If CDs had been around at the time, all these songs would have gone on the CD, but they were fallow. Most of the source material were pre-production recordings done by our live sound mixer, George Durranius. A lot of them were eight track analog, some were direct to stereo, but some of the source tapes had deteriorated as the tape formulations of that time were famous for and had to be resurrected or in some cases re-recorded. Frontier's was clamoring for some more product. We just had the three night Sony Hall live performances of the first three records and bonus tracks and with original drummer Albert Bouchard on the stage too. But they wanted more stuff, so we got this idea to do it. So you used AI to reconstruct the songs or to fix the quality? Yeah, the AI actually demixes a stereo recording and lets you have more control over the individual elements, the drums, the bass, and the vocals specifically.  I think what it does is it separates the tracks. It gives you a little more individual control as if you were dealing with a multi-track sound. Which song from this new album did you have the most difficulty recreating or re-imaging? I don't know because it was done by Richie Castellano in Staten Island. And he did most of the tech work on this with Steve Shank as producer. Which song, then, I'll ask you, are you happy that it's been sort of rebuilt and brought out for today? I like the one that I sing. Well, there you go. Yeah, the only thing. I like that because that was Albert Bouchard's song that he asked me to do the vocal on. And it didn't make the record. And now when I hear it, I said, oh, I wish that it made the record. And a cool thing is kick out the jams, which is a cover that you did back when you play live. And now you have finally a studio version of it. How did that come about? Yeah. I don't know if we were playing that for fun or do we actually consider putting it on the record, but I think it's a really good version. And especially now that the MC5 are gone, it's just I feel really sort of affectionate and nostalgic for the whole MC5 thing. Wayne Kramer just passed away. Yeah, actually, it's a great version. And I'm happy that it's included on this. I think we could be proud of what we did. What was it like working with Albert, the Bouchard brothers, Joe and Albert all these years?  I mean, yeah, yeah, yeah. You know, we've had some collaboration over the years since they left the band, but it's fine. We've done quite a lot with Albert. And this is the first time we've done stuff with Joe in a long time. Do you see this as the last album by Bluestar Cult or you think you got another one left in you? As far as promises, it's the last one. But you know, in reality, I don't know, perhaps there'll be more stuff. I guess Richie reinvigorates you. If we stop recording, we might get restless. What can I say? I don't know. How many dates a year do you do on tour? We did 75 in the 50th anniversary, which is 22. And then last year we did about 30. And we're going to do less this year. And, you know, we may we may want to tour again, but I'm thinking I'd like to just not tour for a while. So is that like a pause or retirement? What's that? Is that a pause or a retirement? As long as I can play and sing, I'll probably want to, you know, be out there somewhere, you know? But as far as the grind of making a living at it, you know, I don't have to. So we'll see what happens. Yeah. Let me ask you, like we started off with, hey, I'm not looking very heavy metal today. What's the connection between Bluestar Cult and heavy metal? There's always been that connection. Yeah. Well, I think the term was coined right about the time that we got started.  And I always thought of the underbelly as the last of the East Coast psychedelic bands, you know? So, you know, we're sort of a jam band, you know, more than a metal band. Certainly what metal has become is nothing like what BOC is, of course. Did you at one time consider yourselves a metal band back in the day in the early 70s? Only before the term was really defined by the bands that followed us. It's interesting because the movie Heavy Metal, which actually had nothing to do with Heavy Metal, but it sort of inspired everybody.  Yeah. And when you look back now at that movie and your contributions, do you think it was the right song or the right, or maybe the movie didn't hold up well over time? Yeah. Well, I think Veteran of the Psychic Wars is actually a great song, and I think it fit in the movie, you know, fine. And we had actually all written songs for submission to that movie, and some of them came out on other BOC records. So. Yeah. Even the song Heavy Metal was in the movie, right? Right. On the same album, right? Yeah. Yeah. Actually, I don't know if that was part of the effort. I guess it was, yeah. Yeah. I mean, you would think Heavy Metal would be with Heavy Metal. Strange enough, that magazine inspired the movie in that magazine. Yeah. Well, that was a Sandy Perlman lyric, you know, Heavy Metal of Black and Silver, and he might have coined the phrase, you know, I don't know. I'd never heard it before he said it, you know, and applied it to us as a defining descriptor, you know. So did anybody say Heavy Metal before us? I don't know if that did, you know. I think we were the first Umla band.  I know you've spoken about these songs so many times. But do you think that sort of fractured the band because you were the big hitmaker of the band, you had that voice, your songs were the ones that sort of took the band over the top. Did that cause sort of friction in the band at the time? Well, we all sang in Blue Oyster Cult, you know, and Eric Bloom is the prime singer and he was the, he was the, you know, the the the shouter and the growler, you know, putting across the heavy stuff. I'm more of a crooner myself, but it's just the way it worked. Once the Reaper was a hit, the whole band wanted to write hits, you know, and I think that that actually, you know, was was not the best strategy for the band, but you can't blame everybody for wanting to hits and the record company certainly wanted hits, you know, so we became a lot more pop oriented, I think, in in response to having a pop hit. When you came to the band and you said, I got a song called Godzilla, what did they say to you? Yeah, okay, let's hear it. If there was any song that was close to metal, that would be it.  Any plans to re-release the the Black and Blue show that everybody is always talking about on, I guess it was released in 2000, but and, you know, I don't know who has the rights to that. We don't, you know, so. All right, so you haven't heard anything about anyone? I had heard that that Ozzie and his camp didn't want that out, although, you know, Ozzie's not on that, it's Ronnie Dio, but, you know, who's ever suppressing that is not us. Okay, I remember my friends in Milwaukee at the time, you know, everything was being torn up. If you remember what happened there, there was like 160 arrests, I think, something like that. Yeah, yeah, we, you know, we had played our show, you know, we were supporting sabs at the time and when the hell started to break loose, you know, we got out of the building, so I didn't even, I just saw it on television basically after the afterward of that. Any thoughts on Ronnie James Dio, you know, seeing him perform at the time? That was his heyday, you know? Yeah, yeah, I saw Ronnie play a fraternity house in Cortland, you know, actually was in Geneva, New York. He was from Cortland, yeah, because I went to college upstate New York with Albert, and that's where I met Albert Bouchard and Eric Bloom went to Hobart in Geneva, and we went to Geneva and saw him play Tommy in a fraternity house.   Going back to the album, like I hear late night street fight kind of reminds me of the revenge of your Gemini, is that, were there like little aspects of these these unfinished or now finished songs that sort of made their way onto other albums? I don't know, both those songs have the Bouchard Brothers shuffle groove, you know. Like Albert and Joe, when they're doing that Vera Gemini and street fight shuffle beat, you know, it's really infectious. Like, we've got to get out of this place, you know, that sounds like classic B.O.C., probably in the mid-70s. Yeah.  So, you know, I'm glad that that version exists. How much is Richie, he seems to be like the conductor today, right? He's sort of like bringing it all together. What's his role today? Well, Richie, he's got a big talent stack, you know, he's a great player, he's very tech oriented, he's a good recordist, he's a good video guy. He's collaborating with John Anderson now on a new post-Yes, Anderson material. Yeah, yeah, yeah. And, you know, he's worth his weight in platinum or diamonds or whatever you want to say. Newtonian he's with. You know, he's touring with John Anderson, I think he's going to tour with him as well, correct? Yeah. Yeah, he did a tour last year and then went over like gangbusters. The Yes fans just couldn't believe what they were hearing, you know, with the band geeks and with John. So, they're doing more. Tell me about Cultosaurus and working with Martin Birch, you know, on those two albums after the one album. Yeah, yeah, I feel very affectionate toward Martin and said he's gone, you know, he was the most open and with his knowledge, you know, as far as teaching, you know, me how to how to record at home and stuff like that, you know, he was just, he was a great guy. Yeah, he was interesting, great. You know, for Cultosaurus erectus and far of unknown origin, when you put those two albums on, they seem to be the most consistent from start to finish. Is that like, would you agree with that compared to? I think, yeah, I mean, I think a lot of that's Martin in terms of, you know, he engineered and produced and he, you know, he didn't have a heavy hand as a producer, but he would really, you know, if he thought something was important, he would, he would, you know, stand up for it, you know, so I think the coherence of his records are basically his doing. And tell me about Sandy Perlman, another great talent, you know, and his legacy in regards to always these obscure lyrics. Did you, when he came with you with these lyrics, did you sometimes know where it was going or you just, would he explain them to you before you kind of made them into songs? Not really, no. But, you know, they're just, they inspire your imagination, you know, he would not want to really give you a literal description of what he meant, you know, but, but the story aspect was just left off the pages, basically, you know. And Sandy's the reason why I'm a professional musician and a recording artist, you know, before meeting him, I was never self-motivated enough to consider doing it, you know, but he, he recognized my guitar talent and with the synergy of the elements of all the original guys' insanity, it's, it made sense to really give professional music a, a shot, you know, it's, we, we felt like we could do it with all of us together. Tell me about what Metallica covering astronomy did to, to Blue Oyster Cult's credibility, I guess, that didn't change it. Yeah, it gave us some cred with the, with the younger generation behind us. And of course, we were very flattered when they did it, you know, it's nice to get some, some recognition like that. I mean, I, I love all the covers of our songs that, that I, that people do, and there's a lot of them out there. You know, it's interesting about astronomy. It's a song that I always knew, but when Metallica covered it, then it just became that much bigger, right?  It did. It's a great song. Do you think you'll ever live down the cowbell? No. No, the cowbell is like a ball and chain around Blue Oyster Cult's ankle. You know, and it's okay. You know, I've, I've long since, you know, not for given whatever, you know, connection we have, you know, it's, I just accept it. Don't fear the Reaper. How many times a day has it played worldwide? Do you have any statistics? I don't know, but it's, it's still, it's almost, it's probably a bigger hit these days than it was in 1976. It's incredible, isn't it? What does the song mean to you today?  A lot of artists say once a song's so big, they feel that it's not theirs. It belongs to the world in a way. Well, it certainly has rippled out into the culture, you know, and at this point, it's, it's, it's, it's a eulogy and a tribute to the people that are passing away. That's the way we, you know, we dedicate, we dedicate it to the people that have gone, you know, on a regular basis. I want to play it at my funeral, you know, have it on loop. I think I want to play Godzilla at mine. That's okay. Yeah, you're welcome to it.  Yeah. Okay. Well, we get ghost stories. We are touring the, the, the dates are fewer. So if you want to see us, I would recommend coming, you know, and I've got a solo tune that's coming out later this year. And it's the first thing I've done solo since the 80s. And going forward to the future, I would be surprised if you'd never heard anything more from us. You know, they'll probably will be something at some point, but we are content to present what we have out right now. And we, we still like what we do. All right. On that note, ghost stories coming out April the 12th, Frontier Records, I think you guys like ghost stories. I'm sorry? It's creepy. Well, you look good, man. You look good. You look good. You look good. And I'm, you know, I'm, I'm hoping one day you guys will come back to the eastern part of Canada. Yeah. Your last show or something. Right. It just takes a lot of money to get us up across the border. That's Yeah. We got it. We got to figure something out. On that note, Buck, thank you for so much for your time. And yeah, I wish you all the best. Okay.


Item number SCP-1340-RU Object Class, Euclid Special Containment Procedures No methods of anomaly capture and containment have been developed as of yet. Research efforts are currently ongoing. Anomaly witness identification and capture is to be performed according to Standard Foundation search protocols. All circumstances of contact with the anomaly are to be ascertained on successful capture. If the first contact with SCP-1340 has been broken prematurely, it is required to perform a second test contact attempt. If the test proves negative, the subject is to be administered Class B amnestics and released, with a week-long period of observation. All other subjects are to undergo comprehensive treatment procedures and be administered Class D amnestics. If the treatment fail, false memories of a personality and a dislike to television technologies should be implanted as per the Second Life Protocol. Such subjects are then to be relocated to closed communes under Foundation control, in particular those liking access to televisions, where they can be used in covert safe research experiments amid routine tasks. Description SCP-1340 is a phenomenon consisting of spontaneous appearances of an image of a human eye on CRT-based TV screens. Set image takes up the majority of the kinescope's visible area. Despite apparent lack of consistency between cases of the phenomenon's appearance, certain patterns have been deduced as intrinsic, such as SCP-1340 appears exclusively on cathode-ray tube-based devices, though implementation of this technology may vary, connected to analog television antennas. SCP-1340's period of activity falls between 2300 and 0200 on local time. All registered incidents involving SCP-1340 are localized to the Northern Hemisphere, between 45° and 75° latitude. Each particular registered incident has involved only a single witness, hereafter referred to as observer. Possibly a concurrent observation of different locations has been confirmed by experiment. As such, the anomaly cannot be contained through observer isolation. General analysis of anomaly witness reports, as well as replicated contact efforts, have permitted to pinpoint the course of SCP-1340's activity. During first contact, the anomaly manifests on active television screens that have been showing white noise for extended periods of time. During subsequent contact events, the anomaly is capable of overriding low-quality transmissions. Presence or absence of audio transmission has no effect on contact probability. Upon manifestation, the device begins showing an image of a human eye which takes it to the majority of the screen. Said eye is blue and belongs to a man. The image is clear and free of any effects that hamper overall perception of the contents. Analysis of the eye sclera has confirmed that all instances of the anomaly transmit the image of the same man. The eye is always wide open, slowed and the frequent blinking is present, the pupil is dilated, and the eye often reacts with delay to the observer's movement, tracking them. If the affected device is audio-enabled, upon manifestation the sound volume will be reduced to 25 decibels and will consist of weak white noise static along with intact and fragmented words, distorted and pronounced with apparent difficulty.  Otherwise, the anomaly will continue manifesting itself under the device every time under the described requirements, even without the observer present. Under continued observation, SCP-1340 expands its sphere of influence and begins to appear not only in the location of first contact, but also in other places where the observer is present. It has been noted that in 65% of registered cases during repeated contacts, the anomaly brings into existence an unlimited number of CRT television devices of various kinds and models, exclusively within the locale of first contact, which seems to operate without any apparent power sources. The TVs are placed on the floor, on various furniture present and on each other, and vary in size substantially. During the anomaly's active periods, all devices transmit the same image of SCP-1340, and the anomaly's eye is not able to track the observer, instead chaotically looking from side to side, while the sound's volume, despite a considerable number of additional speakers, increases by only up to 10 decibels. The TV devices are off while the anomaly's inactive. Observers rarely disclose the occasion, and usually consider it a sign of psychological illness. In rare cases, the subject has been able to get rid of SCP-1340's presence through prolonged medical treatment. In addition, the observers develop phobias towards watching television, which prevent further contact with the anomaly. Due to the circumstances above, the Foundation is currently unable to discern the periodicity of manifestations, or the overall amount of contact cases. All experiments with SCP-1340 have been classified by the Ethics Committee. The Foundation has successfully recovered several documents that explain the anomaly's appearance, from internal GOI archive records. The addendums are available with clearance level 4. Addendums to the SCP-1340 document. Add letter belonging to ██████████, January 11th, 1969. My name is ██████████. I am an accountant at ████████, and this will be my suicide note. I have no relatives or loved ones, so I write to you, prosecutors and officers. I am haunted by hallucinations related to TVs. It must be because of my trauma and several months of coma. It happened first when I fell asleep after the show ended. I woke up to the sound of my cat screaming, and saw an enormous eye staring directly at me from the screen. I was half asleep and didn't understand what was going on, but then realized that the broadcast had long since ended. It was about one hour past midnight on the clock. The eye was just staring at me, and then blinked. I screamed, threw something at it, and ran to the bathroom. When I caught my breath and calm myself enough, I looked back. The eye was still there, and it only turned to stare at me again. I couldn't muster the courage to shut it off, and as such stayed awake in the bathroom, shutting it down when sunrise came and there was only static on the screen. I witnessed that eye time and time again after that. I stopped panicking in front of it and learned to withstand its gaze. At some point I thought it was my own eye. It looked scary, but it didn't want to scare. I brought myself closer to it and tried to hear what it was speaking to me. It was quiet, even on full volume, and I decided to buy another TV for it. Then another. I wanted to hear what it was saying. I wanted to help it. I started stealing, and for that I am sincerely sorry. All the money I got that way I spent on traveling around the Soviet cities and buying out old TVs. I have collected 18 in total, different ones, small and big. Maybe that was me hyper-compensating for the fear, and maybe my attempts to find the truth of justifications. I don't know. Every night I closed the blinds to prevent my neighbors from seeing this bright blue light and listened. It didn't get much louder, but I managed to discern some of the words. I didn't understand much, but what I did finally did me in. I'm insane. I recorded all my steelings on the back side of this note and requested to repay them through selling off my car. I will break the TVs. There is no other way. I bequeath my brain to scientific purposes so they can help those like me. I request not to blame anyone for my death. January 11, 1969 Classified, Krivapolov Research Institute Progress Internal Report, August 14, 1967 2. Progress Research Institute Director Kovalov V.G. From Bureau No. 4 Director, Binding Consciousness, Krivapolov, A.C. Per Bureau No. 4's current directives, I am informing you of a suggestion to use the developments of the Mine-64 project, to study transmission methods for discrete thought forms, and, further on, main cerebrum portion impulse flows through inclusion and info code arrays designed to adapt the technology to television methods of information playback. As you know, the Mine-64 project has advanced significantly since integration of ████████. Currently, we are able to record and seamlessly transmit neural impulses, but the Institute still does not possess a suitable storage device for such vast quantities of information. The only currently known storage sufficient for human mind conversation is the info spirit itself. There are other difficulties as well. Out transmission capabilities significantly outpace our recording capabilities. The speed of processes running within a human brain is too high, far higher than our current speed of impulse recording, which means that we cannot adequately record and transmit the full thought form of a person without disrupting its connection, and, as such, without degrading their consciousness and memory. Unfortunately, this lag does not allow us to experiment with copying a healthy person's personality. However, the Bureau members have found an alternative method. It has been proposed that we use a comatose source in the experiment. I have taken responsibility and have found a suitable candidate for such a role. Under medical attention in municipal hospital number ██████ currently lies patient ██████ in a state of coma after a tragic accident. We hereby request your assistance in arranging a classified experiment on transmitting their personality into the info sphere through our Bureau's newest antenna and receiving the resulting signal on the Chukot station. The process will take approximately two hours. Chemical treatments developed by Bureau number ████ are proposed to be used to slow the brain's activity as much as possible. Yes, we will be unable to halt the cerebral processes completely, but the estimated damage to the consciousness thought form is expected to be minimal. Now onto the practical side of this research project. We expect the Chukchi Peninsula radio station personnel to receive the information of this person in format close to television standards. At this point, we can only guess what it will look like, and whether such a transmission will bear any significance for further research. In overall, however, I foresee use of this technology applied to being able to transmit a speaker or presenter directly into every house, every particular receiver. The viewers will gain access to actual talk partners competent in various topics, who will be able to convey useful information more concretely to every particular listener. Just imagine, you turn on the TV, and the athletic show hosts not only show you the exercises and keep count, but also points out mistakes and gets professional advice. Professional shows for children and adults, news reports, sports shows, travel and history documentaries, etc., will grow to a new level. Open the path to fully-fledged connection and feedback. I would like to specifically address any possible concerns about the experiment's ethical side. The operations involved will cause no physical consequences or even discomfort to the test subject. All records of this intervention will be kept secret. I would also like to point out the fact that the resulting information model of a human – phantom, thought-form, or mind-mold – is not human in the word's common meaning and exists only as an idea, a information current, which puts it closer to a solar's computer. Bureau No. 4 Director, Mind and Consciousness, Krivapalav, AC. Transcription of SCP-1340 Speech Pattern Analysis The following transcript has been procured through the Foundation's speech recognition software from registered occurrences of the anomaly. The object transmits words and phonemes in a chaotic manner. The following texts have been generated based on possible meaning, registered intonation and other factors, though it remains distorted. Italics denote portions that differ in pronunciation and intonation, but that are still considered valid based on the machine's output. The uppercase text denotes more expressively pronounced phrases. Note that the level of volume remains within the 25-35 decimal range.


This commentary examines the role of primary health care, PHC, in reducing noncommunicable diseases and CDs. It emphasizes the need to go beyond the health care system and focus on the social determinants of health in order to achieve health equity. The commentary also stresses the importance of a wider biopsychosocial approach to health, acknowledging the influence of social determinants of health and inequities in health. Universal access to care and public funding are essential, but regulations must be put in place to ensure equitable access in practice. An example of a PHC reform in Sweden demonstrates how introducing market solutions into a publicly funded PHC system can have negative consequences for those with greater needs and can reduce the impact of PHC on population health. This article was authored by Bo Birstrom.


Now we'll see what is intermolecular forces and what are the different types we have? Intermolecular forces. So theoretical just to know the definitions and all that is it, nothing much. So intermolecular forces are generally very weak forces. OK. And total we have four types of intermolecular forces. Right. So there are, write down, there are four types of intermolecular forces known. There are four types of intermolecular forces, intermolecular forces known in the neutral molecules, neutral molecules. OK.  First we have dipole-dipole interaction. Dipole-dipole interaction. The second one we have dipole and induced dipole. Dipole and induced dipole interaction. One second, guys. Yeah. Dipole-dipole interaction, dipole-induced dipole interaction. And the third type we have, that is London dispersion forces, London dispersion forces. And the last one is hydrogen bonding, which we had already discussed. Correct. So these are the four types of intermolecular forces we have. So we'll discuss this one by one. See, dipole-dipole interaction means what? Let me just explain you first what is a dipole. OK. Dipole means what we have, you know, two poles here. One is supposed positive charge, so otherwise negatively charged, right? OK. So this we call it as a dipole. You have a rod. One side of the rod, suppose positive charge is there, and another side is negative charge. Small length. Length should not be too big. OK. So this rod, then it behaves as a dipole because there's two poles, correct? So if any electric field is there, so this electric field, if it acts on this charge in this direction, so on the positive charge, it will be in opposite direction, right? So in presence of an electric field, it has a tendency to rotate like this because of force acting in the opposite direction. Torque basically happens over here. So all these things are not required here in chemistry. These things you will study in physics. OK. But this is what the dipole is. Two poles we have there at the two end. One side we have positive charge, one pole. Other side negative charge, another pole, right? In chemistry, what happens when you talk about the dipole? So we have, suppose, a molecule, correct? Like, for example, if I talk about this NH3, OK? Or I'll take the NH3. NH3 will have, right? So how do we think of a dipole in a molecule like this? OK. So dipole in a molecule like this we can understand because the electronegativity difference between the atoms which are bonded. Like you see, nitrogen is highly electronegative. So it is delta negative, delta positive, delta positive, and delta positive. Each bond here, it is behaving as a dipole because, again, the length is small and positive negative charge at the two end, right? So it is behaving as a dipole here, correct? And that is what the meaning of dipole-dipole interaction we have. It is basically exist in polar molecules. Because of this electronegativity difference, the mu of this, the dipole moment, is not equals to 0, right? And hence, it is polar molecule. If dipole moment is 0, then the molecule is said to be non-polar, correct? So dipole-dipole interaction, like I said, it is possible in two polar molecules, OK? I'll just take this separately also. Let me just two points, if we just write down here, two polar molecules. It exists between polar and polar molecules. When we talk about dipole and induced dipole, so induced dipole means because of one of the dipole, that one dipole has been induced or introduced into the another molecule. So this is for dipoles with polar molecule and induced dipole is with non-polar molecule. So when a polar molecule comes closer to a non-polar molecule, then this negative charge, OK, also attracts this towards the side. The electron pair will be on the other side. So this was non-polar. But when it comes closer to a polar molecule, this also induced some charge into this. And hence, it is acting as an instant dipole, we say. An instant dipole creates in this neutral molecule, which was non-polar initially, right? So this kind of dipole-dipole interaction that we have, we call it as dipole-induced dipole interaction. So basically, dipole-induced dipole interaction is possible in one molecule, which is polar, other one other molecule is non-polar, correct? Let's discuss this one by one. Had in morning, we're not going to discuss because we have done this already in chemical morning chapter. Let's discuss these three one by one. So write down the first point, dipole-dipole interaction. Dipole-dipole interaction. Write down this force exists between two polar molecules. In short, I'll write down here. Between two polar molecules into polar molecules, it is weaker than ion dipole forces and effective when polar molecules are very close. It increases with the molecular size dipole moment. If molecular size is more, molecular weight is also more, correct? So sometimes we also say molecular weight. So molecular size and dipole moment we have. More dipole moment, more will be the interaction because the two bonds, you see this, the two bonds are close enough, positive, negative. And one more we have here, negative, positive, positive, negative. So this is the interaction we have between the opposite charge. This interaction is dipole-dipole interaction we have. So for this, dipole-dipole, the two molecule must be polar. Then only we have charge separation like this. The second one you write down. The second one we have dipole-induced dipole. Induced dipole. Next, see dipole-induced dipole. For dipole-induced dipole, it is possible between a polar molecule and a non-polar molecule. Polar and non-polar molecule. If you look at this molecule, which is polar, so it has positive and negative charge like this dipole. If the another molecule comes, which is non-polar, comes closer to this, then this positive charge will attract the electron. So this electron will come closer to this side because the positive charge is attracting electron. And another side, this side becomes relatively positive. So this side of dipole creates into this. This we call it as induced dipole. You keep it away. You remove this particle from this point. Other side, right. This dipole won't be there. Again, you come closer to this. We'll have a dipole, closer to this molecule. So this molecule we call it as here. It is an induced dipole. Induced dipole interaction. That is induced dipole. This is dipole and induced dipole interaction. We have polar and non-polar molecules. This kind of forces, we also call it as Debye forces. Dipole-induced dipole. We also call it as Debye forces. This is also very weak. Even it is weaker than dipole-dipole forces. Next, it increases with first one, the dipole moment of polar molecule. Dipole moment of polar molecule. And second is polarizing power, polarizing power of non-polar molecule. It means how easily this non-polar molecule is generated. Polarizing power of non-polar molecule. It means how easily this non-polar molecule can polarize. Polarizing power of non-polar molecule. The third one is London dispersal forces. It exists between non-polar molecules. Two non-polar molecules. It is due to the random motion of electrons in one atom of one atom, an instant dipole creates in the second atom, which influences the motion of electron in another molecule or atom. It is mainly for noble gases. For example, if I take the example of helium, this is the helium molecule we have. Helium has two electrons. For any instant, two electrons are residing on this side. This side will be delta negative partially and this side will be delta positive. This positive charge creates a dipole here. This positive charge will attract this electron towards this side. These electrons will be here then, delta negative and delta positive. Both molecules, you can say, the dipole is being induced here in both the molecules. It is not like that this will be there always. It is because of the motion of the electron. The electron is continuously moving. For any fraction of a second, or for any fraction we can say, you cannot even imagine the time over here because position of electron we cannot define. But for example, or for any instant, if the two electrons resides here, for suppose one-tenth of a fraction of a second, for that time also if the electron resides this part, this side here, then this side becomes partial negative charge that is delta negative, so this side will be delta positive. Now at this moment, this positive charge will attract the electrons of the other molecule. Hence, it influences the motion of electrons in the other molecule. This attracts this electron towards this side and hence here also a dipole creates. This kind of force of attraction that we have here is London dispersion force. It will be there for, you know, you can say one by thousand times of a fraction of seconds. You cannot even imagine for how small, for how long, you know, time obviously because electron is continuously moving, right? It has wave property. So it will be very, you know, for a very small time, you cannot even imagine that time. Plus it is very weak also since the electron is continuously moving. So if you talk about the strength of these kind of, you know, intermolecular forces, all are weak forces, but among this, among all these, you know, intermolecular forces, dipole-dipole is the strongest one and then, you know, this one, dipole-induced dipole and then London dispersion forces, okay? London dispersion forces increases with, with first of all the number of electrons, if more number of electrons in the, than the strength will be more, number of electrons, molecular size and then polarizability is the three condition we have. Hydrogen bonding we have already done, so I'm not doing it here again. So this is the intermolecular forces we have, different types of intermolecular forces, right? Diffusion, diffusion we have done already. Yes.


What's up everybody, Jason here for JazzBaseCaseBrates.com. This was our last filler, guys, to give away the last 10 spots in the hip parade baseball dual case break with this 2022 Top Scrone Jumbo Pack number 49 random teams. So the way these work, guys, is we'll do the break, we'll randomize the customer names, teams will strip the hits out of the pack, just remember, no VAC commonship out of there, just everything else. And then at the end, we'll have a new Dice Roller Randomizer with the original list. Top 10 names at the end of the randomizer, we'll get spots in the hip parade dual case break, which is this one, and we'll be coming up next, guys. So let's do the break, roll 6 out of 4, 10 times, good luck. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 6, 4, 10. Steve Bert to the top, now Steve Bert to the bottom. Now guys, this is just a pack filler list. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10. All right, 10 times, mats down to the A's. All right, again, guys, just think what you got, of course, just a quick pack filler.  Rip this pack, Lizardo, and we got an autograph. Heliot Ramos for the Giants, 28 out of 99, a little Goldie there. And Giants is going to Steve Burch. All right, guys, there you go. Now let's switch scenes and let's give away the 10 spots. There's the customer names, 10, and the snake eyes, just two times. Well, OK, two times, top 10. 1, 2, boom, two times, two times, top 10. Steve Burch, 10, you're in. Nester, 9, Steve Burch, 8, Steve Burch, 7, Port, David, Steve, Steve, Kev, and D, low. There you go, top 10 are in. Appreciate you guys coming up next. It is the break itself, thank you.