The second part of this talk is about some of the data quality issues researchers should keep in mind when they're analyzing biosocial data. And I'll be talking about two kinds of issues in particular. One is about the mode or collection condition, whether that's important and whether that should be taken into account when analyzing biomarkers. And I'll also be talking about some of the quality control or QC processes that should be looked at at least by science researchers when they're looking at biological data sets. A number of biosocial studies tend to use two kinds of methods to collect biomarker data. The gold standard is the clinic collection. That's because it's a very standardized process. Participants are invited to come to the clinic and so the blood samples are collected and stored and processed immediately. So because that's a very controlled environment the biomarkers that are obtained are thought to be of a very high quality standard. And that's the way how a number of studies in the UK have collected their biomarkers. The Avon longitudinal study for example, the 1946 birth cohort study. When the participants were age 63, the Hartfordshire cohort study went to civil servant study. The other way of collecting biomarkers or blood based biomarkers are when participants are visited at home and their blood samples are collected and then posted to a laboratory. And that's the case with understanding society, the Southampton women's study, the 1946 birth cohort study when the participants were age 53, the health survey for England, and the English longitudinal study of aging. Now when people are invited into a clinic condition, as I said, it's a very standardized environment. So the temperature is standardized. For example the collection conditions are standardized. And the blood samples are usually drawn through a vene puncture. So they draw blood through a person's veins and that blood sample is immediately processed and then either stored in a freezer or the blood analytes are measured then and there. In contrast, in population surveys what happens is that there's a delay in the processing of that blood sample and the storage of that sample. And here we've got some examples of the different conditions in which blood samples are taken and stored in the top left-hand corner. We've got a nurse in a clinic setting and as I said that is a very controlled environment. And so the blood that the nurse draws is immediately stored and processed in very high quality ways. Whereas in the top right-hand corner we've got a nurse taking blood pressure but could be taking blood as well from a participant at home. And there the environmental factors are much more variable. For example the room temperature could be highly variable from one home visit to the next. The time of day is particularly important as well. So in a home visit the nurse may not have complete control on what the participant did just prior to their visit. So the person could for example have smoked or had a lot of food which could influence their levels of biomarkers. Whereas in a clinic visit there's to some extent some control over the person's activity, the respondent's activities just before the samples are taken. The blood samples that are taken by the nurse in a home visit are usually stored in particular ways and they can be sent by post. For example in the Jiffy bag and the process of posting the blood samples, the environmental conditions in which these blood samples are then exposed to are as you might imagine quite different from the setting in a clinic situation where the blood samples are stored immediately in freezers. And in the bottom right hand condition part of the slide you see some pictures of other conditions that affect both home visits as well as clinic blood sample collections which is that whether it's a weekday or weekend or what month of the year all of these factors do tend to affect some of the blood based biomarkers. So it's important to keep these in mind, these considerations in mind when analyzing biosocial data. In the top graph I've shown you some the distribution of the times in which nurses visit the people at home in understanding society and we see that it's a bimodal distribution. We see that nurses tend to visit people just after 10 o'clock or if people are working they tend to visit people at home around 6 or 7 p.m. at night. So you can imagine that if these are the times in which blood samples are taken and time of day has an effect on particular analytes then we really need to be considering what time people took their biological samples. In the bottom picture we've got a diurnal distribution of the stress hormone cortisol and in general people have a very marked diurnal pattern so as people get up their cortisol levels shoot up and then over the rest of the day the cortisol levels come down. So you can imagine a nurse visiting somebody at home collecting cortisol data in the morning it's likely to have very different levels of the stress hormone cortisol compared to a nurse visiting somebody else later in the evening. I'd also like to talk about some of the quality control issues that researchers should be aware of when looking at the biomarker data and that is largely down to the labs that process these blood based biomarkers. They're divided into internal and external quality control processes some of the biomarkers have impossible values so for example some biomarkers like height and weight they're likely you can imagine some if you have somebody in your data set that is 10 meters tall or 1,000 kilograms in weight you can imagine it's going to be hard to anonymize that person because they're going to be a completely unique individual. So you can pretty much rule out that there are impossible values so it's good to look at the distribution of your biomarkers to see whether there are some impossible values and treat them as outliers. But independently of that when the blood based biomarkers are processed in a laboratory what the laboratory does is that it tests when it goes through the procedures that derives the blood based analytes it repeats this on another day and hopefully there's a very strong correlation between the analytes that they get on one day compared to another day. So that's called the intra-acid coefficient of variation and ideally we want that we want there to be a very small amount of variation so less than 5% is within acceptable limits. So that's comparing how one particular biomarker within a lab compares to the same biomarker when it's processed on another day. But the external quality control measures are comparing how the lab does in relation to other labs in processing the same analyte and that's measured through the standard deviation index. So it's a measure of total error in analyzing a particular biomarker in comparison with all the range of labs that have analyzed that particular analyte. And so once again we're trying to get at low values of the standard deviation index we want to have the analyte that is measured by this particular lab to be close to the overall levels that are measured by all the labs. So a score between below one standard deviation index is generally very good. And also I'd like to talk about specific biomarkers. So far I've been talking about biomarkers in general but when we get at sort of specific blood-based biomarker analytes we should be keeping in mind that each one of them has a different meaning has a different significance. So this slide and the next slide looks at one particular measure called C-reactive protein CRP for short and it's a measure of systemic inflammation and usually somebody that has values of CRP between 3 and 10 milligrams per liter is denoted to have systemic inflammation however somebody could have greater than 10 mg per liter CRP values which denotes current or recent infection. So the meaning of high levels of CRP is completely different when it's over 10 as compared to when it's between 3 and 10. So when it's between 3 and 10 it's considered a measure of cardiovascular risk. When it's over 10 it's a measure of infection so very often people when they're analyzing CRP in relation to cardiovascular risk they delete values greater than 10 because they're not interested in whether or not somebody has been recently infected. CRP is also very strongly influenced by people's medication and their anti-inflammatory medications statins, contraception and hormone replacement therapy. In this slide I show the distribution of CRP for men and women and one thing you'll notice immediately is that the distribution is highly skewed. So when we're measuring, when we're analyzing CRP as a dependent model in a regression model for example as a dependent variable in a regression model you might want to think of ways to try and normalize this distribution in order to make the assumptions underlying regression models more plausible. So to sum up about data quality issues to keep in mind when analyzing biological data sets we need to consider the normal ranges of the biological variables. If they are available we need to be able to identify outliers and do something about the outliers. We need to hopefully identify whether the respondent has taken any relevant medication and either control for it or maybe delete people with particular medications from the analysis if that is not central to your research question. We need to consider some of the statistical transformations for highly skewed biological dependent variables if we're looking at that in a regression modeling context. We definitely need to keep in mind the context of the blood sampling like the time of day, the room temperature, whether or not somebody had a recent operation if the person had recently smoked or had food or alcohol and also keep in mind the laboratory based quality control processes in producing the biological data. Is it a good lab that has produced these biomarkers?


Welcome to this lecture on field programmable gate arrays in the course digital system design with PLDs and FPGAs. In the last lecture we have looked at the carry logic in the vertex. Then we have looked at basically the routing resources and how the combinational circuit and sequence circuit or the data path maps into this FPGA resources. We have looked at the dual port RAM and the few fitting examples you know we have looked at given some state machine and given some kind of circuit how much resources it uses within FPGA and also we have looked at a VHDL code and given that code what is the circuit it is synthesized and how is really the signal paths trace within the logic block or the slice of vertex FPGA. We will have a quick run through those lecture slides before we get into today's portion. So let us move on to those slides. So what we have told about the carry logic is that when you the basic operation in arithmetic is addition which is used for subtraction, multiplication, division everything. So to make the arithmetic faster the addition has to be faster. But if you do implement and you know that for each stage you need two outputs one as a sum output and another as a carry output and if you implement this in two logic lookup tables then you need to interconnect them with the wires and all that. That will make all the kind of when you cascade the full adders the total delay will be very high. So there will be advantages if this part is kind of hardwired or put it into dedicated logic and that is what is the carry chain is all about and we have seen that essentially AI like for a particular stage I the input AIB is given to lookup table and an XOR is performed and that XOR select a MUX so which when it is one the carry output is a carry input or if both are one the carry is generated if that is not the case okay. So essentially that implement this equation AI exclusive of BI is this path and AI BI is this path and to generate the sum we use this particular AI exclusive of BI and an external XOR gate you know XOR with the carry input to generate the sum. So you can imagine this goes to the next stage where AI plus 1 BI plus 1 is input to the lookup table and that combine and generate the SI plus 1 and this logic there generate CI plus 2 and so on okay. So that is how it goes and this is dedicated this is dedicated built in and we have seen that in the real the logic diagram of the slice where you can see all these you know this part and this part which forms a carry logic and this is exclusive or gate external to it and that is when that can be you know you can take it out or you can register through this particular flip flop okay. And the advice is that if you use a plus operator the tool will pick up this carry chain and use it you do not have to worry you do not have to write the kind of equation for the ripple adder or anything like that. In fact if you do that it will not get mapped into the carry chain it will use you know two lookup tables so whenever you want an adder use the plus operator and also some FPGAs this carry chain can be used as a cascade chain that is this particular output can be kind of ANDed with this particular output and so on okay or odd with it really depends you know whether it is kind of positive logic or negative logic. And we also have seen in a sequence circuit or FSM controls a register or a counter and in our CPU example we have seen that that can kind of enable the data path through a recirculating MUX. So when they enable signal from the FSM is 1 something input goes to the flip flop otherwise it is recirculated. Now in FPGA this recirculating MUX is built into the flip flop and the select line of the recirculating MUX is available as clock enabled or some vendors call it EC enabled clock okay. These are this is all same you know some call it CE and some call it EC. So if you write a VHDL code like this upon the clock if some condo signal is 1 Q gets D then automatically that condo signal is connected to clock enabled because one level of recirculating MUX is all already available. But definitely if you have an you know you have an else condo signal then another MUX has to come outside which will be implemented in the lookup table than in the flip flop. So this normally may on average you will have mostly one control and that is built into the FPGA it is quite good because otherwise for a 2 to 1 MUX unnecessarily the lookup table will get used and by building that into the flip flop the lookup table is saved otherwise a 4 input lookup table will be kind of wasted for a 3 input logic because 2 to 1 MUX will have 2 input and 1 select line as input. So it is a 3 input logic but a 4 input lookup table will be used to implement that okay. And when you have some combinational circuit in an FPGA it will be mapped to one or more lookup tables you know maybe 2 lookup tables will be cascaded or both will be combined whichever way or 4 of them is combined using F5, F6 MUX which is cascaded with something else and so on okay that you can kind of work it out. And when you have a sequential circuit mapping you will have some flip flop combinational circuit flip flop be it the sequential circuit or data path it is all same. Like in the case of sequential circuit the flip flops are kind of you know the source and destination can be in one place and in the case of a data path it is some source register and a separate destination register but the path itself is different in sequential circuit. So the flip flops get implemented in one or more flip flops combinational circuit will get implemented in the lookup tables. And again the flip flop will go to the flip flops of the slices okay and will be good the best we can hope is that this combinational circuit follow with the flip flop can get this thing can get implemented in you know the same slice okay depending on the number you know depending on the number of flip flops it might occupy multiple slices and this would require some extra flip flops from a slice you know it all depends on the complexity we unless we see the circuit we cannot say how it gets fitted. Same thing with the sequential circuit or finite state machine you have flip flops and the next state logic. So this you can imagine that coming in a kind of you know if you go back to this diagram sorry here you have the lookup table followed with the flip flop. Lookup table followed with flip flop so definitely so you have the combinational circuit the lookup table followed with flip flop so that can get implemented and that output can go to the lookup next slice and so on. So that is how the real sequential circuit get mapped into FPGA. This we have seen the IO block essentially it is a tri-state buffer which allows an output path an input path and a tri-state path okay and this can be combinational. So as I said there are FPGA wires here so the output can come directly or through a flip flop so it can get synchronised and go out. So that is a good idea because otherwise already if it is coming through some combinational circuit there will be lot of delay from the clock edge and you know it is going out of the chip it can suffer further delays. So it will be useful to synchronise it with the clock because it appears with minimum delay after the clock then maybe it can be re-synchronised at the receiving end or go through some combinational circuit and get re-synchronised. Similarly input path can be directly taken or it can be synchronised and all these flip flop has clock enable and the clocks and the clock can be chosen from multiple clocks they have reset and set and this programmable delay can be added to make the whole time 0 because sometime the signal is coming from external source it could be synchronised signal but then the whole time can create problem because meeting the whole time is tough so we can add some delay to make the whole time 0 once it is synchronised the whole time will not be much of a worry okay. And similarly the tri-state path you have the combinational path or the registered path and as we said that you know it can be pulled up or pulled down because when you are tri-stating a signal it is floating the noise can get picked up all the inputs can switch. So that can be avoided through the large pull up and large pull down or you can programme a whole circuit which weakly holds on to the last value and so to avoid the noise pick up and it support various IO standards and this is a whole circuit it is a flip flop which latches the input part you can see the output is driven through a large resistance so really does not matter even though it is holding driven by a flip flop the other circuit can kind of pull it down or pull it up with a low resistance there is no kind of VCC to ground short circuit because of this resistance but it avoids the switching you know used due to noise. And this is the main you know the wiring diagram we have main switches and this is the logic block and this is the input to the logic block output from the logic block. As the picture shows there are direct wires running from this switch to the CLB and the adjacent CLBs are connected with dedicated wires that means this CLB output can go to the input of this CLB and this CLB receives input from the CLB output without going through the wires. So that can be very fast and there are some statistics of the number of wires which is available then we have seen the bus lines to tri-state gate per CLB to form the bus which is not available in the kind of current FPGAs. So you want to do maxing you have to do the and or maxing then the tri-state gate maxing then we have looked at an FSM example with 2 input 3 state 2 mille output we have worked out how much CLB it requires to occupy I mean to implement this and we have you know come out with basically 1 CLB-2 flip flop we can kind of refer to the last lectures discussion to get into the detail. And we have looked at so that is how kind of it implements and we have looked at the 8 bit counter with the parallel load feature. So this is the counter you have the 8 flip flops with the plus 1 implemented and we said that this lookup table with the carry chain can implement plus 1 and the flip flop. So it will be 8 flip flops and 8 lookup table with the carry chain that requires so basically it requires 2 CLBs. And we also have looked at a code with kind of A to H input and we said it is a process A is reset B is the clock C is the control signal and Z is B and E and F and E and X or H we have discussed this will be a 2 4 input lookup table cascaded. C go to the enable clock of the flip flop B is the clock A is the reset ok. So we have shown that you know you have taken this flip flop and we need 5 input lookup tables so D, E, F, D goes to same 2 lookup table H is the 5th variable that selects this F5 MUX. So that is combined and that output is routed out to the flip flop and the flip flop gets you can see the clock which is B reset which is A this blue line and the clock enable which is EC which is C. So that is how it get mapped as I said you can write this code select a vertex FPGA or as part in 3 FPGA and synthesize it implement it go to the floor planner open up then you can see the zoom into the CLB which is implementing. Then you can see this wiring connection inside there so you can verify that it is working if the time permits I will show that in the tool this exercise I will show in the tool. And we have looked at the dual port RAM and true dual port RAMs are available because it is a RAM block RAM with 2 ports with input and output separated. So you could write through the one port and read from another port or you can write using both port does not matter but only thing is that there should not be conflict you know both should not try to access the same location. So if somebody is writing and you are reading through another port okay this port then if it is same location then the read value may be wrong and if you try to write to the same location we are not sure which one will succeed. So there is a conflict so that should be avoided but otherwise it is a true dual port and we have discussed little bit about the multi port memories it is not very difficult to implement that but these are kind of hard coded and this can be combined you know this basic blocks are available this can be combined in various ways to implement say different width different depth like you know this will be supposing to 8 then you can combine 2 of them in parallel to implement into 16 both of them can be combined to implement double the size which will involve some maxing as we have seen the lookup table that is all part of the block RAM but you should know that there is a basic granularity with which is the size of the width and the depth. So if you choose some arbitrary width and arbitrary size some block RAM get wasted so you would see that though the you might look into the FPGA data sheet and find what is the total size of the memory available but if you choose arbitrary depth and width you will see that some memory is wasted okay. So that you need to take care you should find what is the basic granularity basic size in terms of the depth and the width. So if you choose an integer multiple of the depth and the width then everything there will be no wastage but if it is kind of fractional on that then some gets wasted there is because these are kind of cascaded or ganged together at a block level not at a very small area I mean small size level. So the basic blocks are combined together to build that so that should be kept in mind So this is true dual port memory each port can be read or write or either you know one is read one is write it is all synchronous read and synchronous write everything gets written on the clock edge and down the clock edge and it can be combined for larger width and depth and it can be instantiated through core generated tool. So when you want to use that you have to invoke core generated tool that will give the instantiation template which can be cut and pasted in your code and this is the conflict and basically this memory when you use you can initialize it with some data and that initialization can be specified in the VHDL code okay. So that is what we have seen in the last class maybe I have gone little fast. So I have repeated that part you please look at the last lecture and this lecture. Now let us come to another part we have discussed this the topic metastability like for a flip flop to latch or to register the input data to the output the input has to specify some timing with respect to the clock edge. That means when the clock edge comes the data has to be set up sometime before it and after the clock edge it should be held on for some more time. So that the value at this point gets you know faithfully copied or transferred to the output okay. So there is a window around the clock edge where in the data has to be stable okay. The time before the clock edge is called setup time time after the clock edge is called the whole time. Then if that is met with a propagation delay TCO the output appears after the clock edge. And if it does not you know if you do not meet that then there is a chance that this could be wrong this would not be a faithful copy of the input. In the worst case it can get stuck in between and we have discussed this phenomena and we have seen how to avoid that by synchronization. We have looked at the single stage synchronization, double stage, multi stage and all lot of techniques and we have also looked at little bit you know how that probability changes and all that. So that is a essence of the timing of the input of the flip-flop. Now when you take a data path and this timing plays to find out what is the maximum clock and basically to avoid whole time and all that. So take a data path where there is a source register the output of which is going through a combinational circuit and reaches the destination register and we know that when a clock comes here at the same time the destination also get a clock. So but the data like whatever may be the data at that point in there is get captured but the input like because of with respect to this clock the output changes and it propagates through combinational circuit and reaches here by the time the same clock edge is gone already and now we know that the next clock edge come and we have to have some setup time before it for it to be captured. So we always in this case analyse the timing with respect to one clock coming here and the data get transferred here go through the combinational circuit and it is setup before the next clock edge. So a clock edge to clock edge timing is analysed to find the clock period okay the minimum clock period which is should be greater than TCO plus TCOM plus T setup. We also know that when a clock edge comes the input has to remain there after the clock edge okay so we should make sure that the input when a clock comes here both at the same time the input changes after TCO plus TCOM that should be greater than the whole time okay because that is with respect to same edge because the same edge is coming there and there is a whole time after the clock edge. So but the data is changing here going to change here after TCO and TCOM so that TCO min plus TCOM min should be greater than the whole time otherwise the whole time is violated with respect to the same clock edge. So basically from the setup and whole time we are you know kind of coming out with this the setup time decide this clock period the whole time decide this whole time violation condition okay in the data path same thing is true for a sequential circuit and FSM where the critical path is from some source register through a combinational circuit which is next side logic to the destination register okay. So the situation is same okay when you look at the individual flip-flop the situation is same from a source register through a combinational circuit to the destination register the clock period should be TCO plus TCOM plus T setup similarly the whole time violation the TCO min plus TCOM min should be greater than the whole time and when we mind you should remember that in all this analysis the clock period is analyzed from one clock edge to the next clock edge and the whole time is analyzed for the same clock edge okay like when the clock comes the data changes with the TCO TCOM here and the same clock there is a whole time window. So this change should happen after the clock edge that is the basic what is basically expressed in this inequality. Now one thing you should remember that we are assuming one we are making a very kind of simplistic assumption in all these analysis in the minimum clock period and the whole time violation you know you can think what is this assumption we are making. Assumption which is not very realistic which we are making is that the clock reaches at the same time to the source and destination flip-flop okay. In a picture it may not be very obvious because you know you are writing a block diagram and it looks near but you should remember that in a chip you know in a huge chip area maybe the source register is in one corner and the destination register is in another corner and the clock has to travel through various path to reach there and that can suffer delay all along. So the clock there could be skew between the clock okay the skew is the relative delay between the clock arrival that means the clock arrives here at 100 nanosecond and the clock arrives is here at 102 nanosecond due to the wire delay then there is a skew between them 2 nanoseconds skew between them okay that can affect because so we have to bring in that skew into analysis of the clock period as well as the whole time violation okay that is important for realistic analysis. So that is what is stated here so in the all analysis we have initially assumed that the clock reaches the flip-flops at the same time but we have to consider the relative delays due to the wiring and that is called skew which is the difference in arrival time of the clock at the flip-flops and we will see what happens when there is a skew between the flip-flop and take assume that there is a chip and there are flip-flops kind of scattered around and assume which is not very realistic that the clock is coming from a pin which is going to the flip-flop okay like that you know like a chain okay which is not a very good strategy but to highlight the problems I am just putting some kind of fictitious case and you see there are two scenarios say take this flip-flop source and this destination where the clock is going from the source to the destination like that and the data is also going from the source to destination and this problem is called min path problem which we are going to analyse the timing and there is another situation where you see this is a source register where the clock gets faulty when it reaches the destination register so but the data is going back from the destination to the source okay so or you can say this is as far as the data is concerned this is a source register and this is the destination register. So here the scenario is that the data and the clock are in the opposite direction which is called max path okay this is called max path problem and here in this case the data and the clock is kind of travelling in the same direction so that is called a min path problem. So we will analyse both of this and see what happens so let us first choose the max path problem where the data goes from the source register to the destination register but the destination register clock comes earlier to the source register okay so this is a little bit of a opposite case the source register drives the destination register with the data but as far as the clock is concerned the destination register gets the clock fast and the source register gets the data I mean the clock later okay. So let us put that picture for analysis so this is the case we have a source register as far as data is concerned the output of which is going through a combinational circuit and reaches the destination register and the clock of the source is called clock 1 source of the destination is called clock 2 and you see that the data is moving this way and the clock is moving in the opposite direction. And now the fallout is that the clock 1 is the delayed version of the clock 2 okay. So let us put that picture so you have a clock 2 which is reaching here and clock 1 is delayed version of the clock 2 and that delay is called skew okay for whatever reason there could be wiring delay buffer delay and all that in the clock. So there is a skew between the clock 1 and clock 2 and mind you the clock 2 clock 1 is a delayed version of the clock 2 so the clock 1 comes later. Now you assume that there is a clock coming to the clock 1 and clock 2 so by the time the same clock we need not worry because the tcq plus tcom is greater than the same clock so by the time this first clock comes at both places there is no time to latch whatever is propagated because it is already gone and the data comes later. So the analysis is from the this clock to the next clock wherein the tcq plus tcom plus tsetup should be greater than this the clock period okay. But you see here the clock 1 is here and the clock 2 is here clock 2 comes early by an amount skew and skew is the delay in this wire okay. So the clock 2 comes early to the clock 1 so basically the timing analysis is from this clock edge to this particular clock edge here okay. Now that clock edge so the analysis is that so the time for time from this clock edge to this clock edge is tclock the period minus t skew. Now that has to accommodate this tco plus tcom plus tsetup so you get an expression tclock minus t skew should be greater than tco max plus tcom max plus tsetup and so the tclock is greater than tco max plus tcom plus tsetup and t skew. So what happens is that the clock period is increasing because of this skew and the frequency of operation goes down. If there was no skew we say tclock is greater than tco plus tcom plus tsetup when there is a skew that gets added up so that the tclock has to accommodate that skew and the fallout is that the clock period goes down the frequency of operation goes low than without this skew. So that is one disadvantage of this skew in a max path because of this skew the clock period goes down or the clock period goes up and the frequency of operation comes down because of this skew the frequency of operation of the data path comes down which is not a good idea. If there is a because of this skew you are forced to choose the clock period which is larger which reduces the frequency of operation. So one need to analyze all the path and what is the maximum skew in a max path situation and choose add that to the clock period so that you get the corrected clock period. And we know that the whole time also will kind of change because the tco plus tcom now should have the skew should bring into the to come into the whole time violation. So that should be analyzed. So let us choose the other problem where the data path and the clock is going in the same direction okay. So here you see the clock 2 is a delayed version of the clock 1. So you have the clock 1 here clock 2 with a skew okay. So the clock 2 comes later now we are in a better position because if you analyze from one clock edge to the next clock edge you have tclock plus t skew because we are going from this edge to this edge. Tclock plus t skew should be greater than tco plus tcom plus tsetup okay. So which is good because now the tclock then the t skew goes to the other end tclock will be tco plus tcom plus tsetup minus t skew. So the clock period requirement comes down the frequency of operation goes out okay. But this is not a great concern because there could be max path which reduces the frequency. So one need to choose the critical condition which is the max path not the mean path as far as the clock frequency is concerned. But the greatest danger when you look at the diagram is not with respect to you know one clock edge to the next clock edge say there is because of this clock 2 is getting delayed. So normally we assume that it is coming at the same time and by the time because of this clock edge the data will change here at tcq plus tcom and we are assuming it is greater than the whole time. So by the time the whole time window is gone and nothing happens to this. But you see here the situation is that the clock 2 is getting delayed. So maybe the tcq plus tcom can catch up with the whole time window of this clock 2 okay. So that is what is shown here maybe because of this delay the whole time window comes here if this is minimal tco plus tcom is minimal maybe it can violate the whole time okay. So the whole time violation condition is that tco mean plus tcom mean should be greater than tq max plus t whole max okay. So that is the issue with the clock skew it can create the whole time violation and if it happens you see there is no point there is no way in changing the clock period and solving the problem. Because if you increase the clock period is not going to solve the problem because the problem is with respect to the same clock edge okay. So it does not like when you go from one edge to other edge the clock period come into picture. But here we are talking about the same edge reaching you know the one of the destination register later and which can cause the whole time violation. So here the tco plus tcom should be kind of greater than tq plus t whole there is a violation happens and because this tcom gets into the whole time window changing the clock period would not help it. But what you can do is that you can add additional delay so that the data at this point comes after the whole time. So this is the issue with the clock skew it creates max path and min path and max path you can bring down the clock frequency in min path you can have the whole time violation. So essentially when you route the clock in a VLSI chip one has to make sure that the clock reaches every flip-flop without much relative delay between them okay. If there is a relative delay between them then all these issues crop up. So it will be advantageous to route the clock because the clock reaches all the flip-flops which is all spread within a chip. Do the routing such that the relative delays at the flip-flop clock is minimal okay. So that is the basic requirement of a clock tree routing. So the requirement is at the minimum relative delay between any two flip-flops at least between flip-flop and where there is a delay data path okay. So if you have two flip-flops we should make sure that there is minimum delay between the arrival time of the clock at least between the registers where there is a data path if there is no data path there is no cause of worry so that is the requirement. So the trick is to balance the number of buffers so assume that there is an input where the clock gets buffered and reaches the flip-flop. So we have to assume that the number of buffers in reaching from the input pin to edge of a flip-flop should match across a flip-flop and the number of wires you know the number of wire segment number of buffers are identical in each segment and one solution this need not be the solution there is one solution is called edge clock tree where the clock is routed like an edge okay. So in a VLSI chip when you do the clock routing you have to make sure that the clock tree is like an edge shaped clock tree but in an FPGA it is built into the FPGA fabric. So that is what is the clock tree and we can see that suppose there is a clock pin which is buffered at the beginning and it comes vertically down then it goes horizontally like an edge and when you branch you put the buffers then you go in the horizontal line you go vertically okay and whenever you take a branch you put buffers and now from the vertical line to each flip-flop can branch out with a buffering okay. Now the advantage is that suppose there is a flip-flop here and a flip-flop here. So you from the input pin you look at the number of buffers say 1, 2, 3 and 4 in reaching here you say 1, 2, 3 and 4. So the flip-flop here and the flip-flop here has the same number of buffers from input pin and similarly you see the wire segment length 1, then 2 and 3 but here it is 1, 2 and 3. So the wire segment are also somewhat identical so essentially we can assume that this queue between the end points are less than that is what is required. There could be a delay between the input pin and the end which we are not worried what we are worried is that relative delay between the flip-flop that should be minimal. So that is where the clock tree is used in an FPGA it is built in and there are dedicated pin which is driving these clock trees. So you should connect the clock oscillator or the clock input to those particular pins and this is about the vertex the clock tree but in the recent FPGA there could be clock trees which is kind of handling one part of an FPGA because the FPGA fabric is quite big may not be able to clock by a single clock or in such complex FPGA there could be multiple clock domains. So sometime you need to clock by the user clock and or there is a clock which is limited to an area of the slice or the CLB of the flip-flop. I mean of the FPGA so that should be kept in mind so whenever you want to use the dedicated clock pins use the dedicated clock tree and so on. And we should look at the delay loop log loop which is available in an FPGA which is used to remove this queue between the input clock and output clock assume that there is an input pin like that and there is a clock tree which we are using to kind of clock lot of flip-flops. Now because of this the buffer delay and all that there could be skew between like you put a because of loading you know there are lot of flip-flops and from the input to the output there could be lot of delayed due to loading and that can be avoided by the delay log loop where the input is connected to the input of the delay log loop. Output is going to the clock tree which is fed back to a feedback. So what does the DLL do is that you have a clock input and assume that the clock output is skewed by some amount. So what it does is that it cannot anyway cannot bring anything back but what it can do is that suppose this is a clock period and there is a skew what it does is that the input is further delayed by the clock period minus skew. So that this edge you know get you know synchronized with this edge. So that skew relative skew is removed. So the DLL is used for desqueuing an input clock with output clock. So you can remove the skew between them using the DLL. So that is the idea of the DLL which kind of add delays to remove the skew. You do not need a PLL because DLL is much simpler to implement than a PLL. But in a PLL you know that the block diagram of the PLL you must have learned and basically in a DLL input clock is delayed but in a PLL always you find the phase difference between the input and output and that is filtered and that is given to a voltage control oscillator to synthesize a clock which is synchronized to the input. So in a PLL the VCO voltage control oscillator synthesize a new clock okay of the same phase and frequency as after the input clock. The only problem with the PLL is that it will lock on to only a range of frequency at the input depending on the filter you are using inside. And also it takes some time to you know get the locking or get the output to in phase. It takes a while but DLL is much more quick in doing the desqueuing. But one advantage with the PLL is that PLL kind of newly generating the output. So even if the input has some jitter that would not be available at the output. So for very serious frequency synthesis we should consider PLL than DLL and like in the current FPGAs you have PLL blocks in addition to DLL in the digital clock manager. So like current FPGAs as PLL and digital clock manager and digital clock manager contains DLL for desqueuing. It has a phase shifter so the input clock can be phase shifter by 90 degree, 180 degree and so on. It has frequency multiplication and division which is available within the DCM digital clock manager. And there are clock buffers, muxes which is glitchless that means there are two to one mux where you can switch between the clock and that should create in not any glitch because depending on when you are switching there could be additional edges at the output. So the glitchless switching which essentially means that those clock inputs should be kind of the switched output should rise to the corresponding clock. So there will be two flip-flops which is synchronizing, crisscrossing and all that. So you can imagine the circuit so the muxes are available and all these devices you know the PLL, DLL, clock buffers, muxes everything can be connected in the clock tree path like between the clock pin and the clock tree and depending on where you require that ok. So that is the basic resources available with respect to the clock management, the PLL, the DCM digital clock manager which contains the DLL and which does phase shifting frequencies and this is de-squeuing and all that it has clock buffers, muxes and all that and this works with the fixed clock pin and you can insert this between the clock pin and the clock tree. So this is little bit about the special resources so you have buffers, DLL, PLL, DCM, block RAM, DSP blocks all this can be you know instantiated with the vendor library components or in the case of silings you know you have the core gen tool which can generate this the template code for instantiating it. And sometime you write a code and synthesis tool infers saying that it is a memory and will put it in the block memory or this computation can go into a DSP block all that is decided by the synthesis tool. And sometime what you can write is that instead of using the vendor library component you can write the VHDL code for a memory and you can attribute use attributes in VHDL code to say that use block RAM for that particular code of the memory. Writing such a code will be you know you will be kind of implementing portable codes you know if you use the vendor library components you translate this FPGA design to another FPGA from another vendor you have to change those components or if you are taking this FPGA based design to ASIC which is usually the case because the ASIC designers will do the prototyping in FPGA and move to the ASIC. So if you use vendor library component all that has to be changed in the ASIC design domain so that can be avoided by using the VHDL and attribute and so that is it. And we are going to have a look at the configuration of the vertex FPGA. So previously we had a look at essentially we looked at the metastability, the clock period analysis and the whole time violation analysis for a data path and sequential circuit and we said we analyse the clock reaches at the same time which is not the case in real life. So we have put a real life case we have put max path and min path we introduce Q between them and analyse and we have seen that it is troublesome. In the max path if there is a problem then you have to reduce the clock frequency in min path whole time violation is that we have to increase the combination delay. And we have looked at the H clock rate routing which gives the minimal kind of relative delay between the flip flop clocks. And we have looked at the DLL which is used for de-squeuing and we have seen what is the difference between PLL and DLL. And we have also looked at what current FPGAs has in terms of the for clock management, the resources for clock management. So let us look at and how these resources are instantiated in the VHDL that is what we have seen. So let us look at the configuration of FPGA briefly I am limiting myself to the vertex and briefly tell you about the current FPGA which has more option than the vertex FPGA which is available. So to be in kind of current I will talk a little bit about the Spartan 6 with respect to configuration. So basically when you are doing the prototyping you can use a port called JTAG which has different name you know it is a committees name which has come out with this particular port which is called joint test action group. That is also called TAP which is text you know test access port. That is also called boundary scan because that was developed that port was developed for the continuity check on PCB with very complex packages like BGA. You know that in a PCB when you mount chips earlier you know you had DIP packages or PLCC package and you want to check the continuity you can probe the source pin and the destination pin. There are two probes one of the source one of the destination. Now in a package like BGA or flip chip the pads come underneath the chip and because of the multi layer PCB this goes maybe one pad output goes deep in within the layers and through the inside layers of the PCB goes to the destination pad and reaches the IC and when you have a bare PCB there is no way to kind of probate because mostly when you manufacture PCB after the PCB manufacturing the chip gets mounted then comes to the testing site you know it is not that the PCB is manufactured then it comes back for continuity check and goes again for you know the component mount. Because that gets delayed because unnecessary you know transport is involved so PCB gets fabricated and chips get mounted on it and so the boundary scan is a test port which has come for the continuity check through the boundary of the chip you know electrically not by probing. So you can call it say kind of inbuilt probing inside the boundary of the chip through the test access port so that is used for even FPGA programming. So basically this port is a serial port with minimum number of line not to waste number of pins so it has a clock pin data input data output and you have a mode select to kind of control a small FSM inside and when you are prototyping you can program an SRAM based FPGA from a PC to a small dongle.  So normally you have a USB dongle where the output goes to the board and you can program reprogram. So this is very useful at the time of prototyping because you are working you know for the various iteration so you do not want to permanently program that into an FPGA so you just program it test it then rework on the design reprogram and all that that is where the JTAG is used and it is possible to program multiple FPGAs through JTAG because the multiple devices can be cascaded because there is a data input and data output data output of the first FPGA can be connected to the data input of the second and so on. So JTAG can you know program a single device or multiple devices which are cascaded. Then there is master serial mode which is like JTAG, JTAG is a standard with respect to boundary scan but master serial is a kind of proprietary port from the silings which has a clock very simple port which has a clock and data input ok. The case of the master the clock is given by the FPGA to a serial prom ok. So literally FPGA is clocking the data out of the prom it is a serial prom which gets and the FPGA gets programmed ok. And this is very useful for deploying an FPGA based embedded board in a field because in the field you cannot insist that program the FPGA through from a PC. So the configuration is stored in a prom which is connected with a serial mode to the FPGA. So the power on FPGA gives the clock and program itself ok.  If the FPGA is giving the clock it is called master but in a slave serial what happens is that the FPGA get the clock from outside ok. That is it is not that the prom gives the clock but you can think of a serial mode where the FPGAs are cascaded. So one FPGA acts as a master clocking the prom also clocking the slave FPGA that is why this slave serial is you know used and there is and these all are serial modes which are slow. There is a parallel mode where may be a CPU a microprocessor can program an FPGA through an 8 bit or 16 bit wide path which is synchronous. So this is the case when you have a processor board and you have an FPGA. So you do not need an additional prom the processor will have some flash memory to store its embedded software or the firmware. So along with that you know in the same memory you can store the configuration for FPGA and through an 8 bit or 16 bit wide path you know you can program this CPU can program the FPGA. And in the vertex FPGA there is only the master mode kind of you know FPGA and the select this particular parallel path but in the current FPGA there is a slave mode. So I think I will show one at least one or two example of at least one select map and this two together I will show this is pretty simple and we also will look at in the next lecture what are the current FPGAs supporting in a nutshell and little bit detail about the configuration. So that is about the configuration one for prototyping 2, 3, 4 kind of in the field how to deploy this in the field. And the select map is a you know parallel programming or parallel configuration which is faster much faster than the serial configuration ok. So I would like to wind it up and we are coming to the kind of end of this lecture set on the FPGA lecture module on the FPGA what is left is maybe little bit about the configuration and bit about debugging and a slight brief look at other FPGAs then we will wind up the FPGA lecture. So please go through the lecture on the FPGA try to understand try to grasp it so that you can when we wind up when we put it together you are very clear what is happening when I show the tool and so on. So I wish you all the best and thank you.


What's up everybody? I'm evil rabbit here on a set of Corsa on the PC getting ready for the shido series round four at autodrome Chica, I don't even know if I said that right, but that is a track We're going to be at and realize you guys can't see it because well I my camera was covering so autodrome Chica Chica Ukraine if I said it wrong and you know how to say prayer Let me know down in the comments because I'm pretty sure I butchered that name But we're here to test the vet here for round four of the shido series Definitely a very interesting track pretty high-speed entry Very little room for error with the walls and you gotta give me your tune has to be pretty much on point So very today test the Corvette. I also if you guys notice the cameras a little different We have a tablet now here that's got some buttons on it But that is for a leader video on I did make the tablet set up to have button controls for our factor 2 And also a set of course of which I will be getting a little bit more into and showing you guys how to do it And a bit of a tutorial video here on the channel So that's how it's there for the button box so the handbrake is now down here So the handbrake to get moved back down so instead of me grabbing up here I'm gonna be grabbing down here So it is taking me a smidge to get used to to notice my handbrake is down here, so I'm gonna be getting used to that and getting used to this track So we're gonna go test this out make sure you follow me in the script So all the show in the description box below let's go smoke some tires and have a little fun All right, so we got our car We're gonna run the basic tune that we ran out of basic to the tune we ran in the last round And we're gonna give this course a shot So I still gotta remember get that my handbrake is here So we're gonna give this course a shot It is definitely very different and very quick on entry like I said there's no room for error So we're gonna give this a first go out here. I've ran it once or twice So I kind of remember where the track kind of sits Handbrake in Too much angle there have to feather out Big correction. Oh, yeah, that's a very big correction. It definitely be a zero So that gives you the just idea of what the track is. It's definitely very different than the tracks we've been running it's quite quick and You have to be very smooth on your transitions because if you are choppy like I was there you straighten up You have all kinds of issues. So don't definitely want to do that in qualifying or anything like that. So we're gonna try Get this a little smoother We're kind of straight enough there oh I was not wanting to rotate what I wanted to yeah, not a good run at all either This track is definitely gonna be a lot of practice involved to get this down to where I'm Comfortable and qualifying runs. So gonna definitely be working with some of the other Prisheed Asteris style drivers to Get a tune dialed in for this car and you know get some practice Because it I feel like this track is very dependent on a tune the car's got to be dialed in otherwise It's not really gonna work right for you Better oh That's much better Okay, so that was a much better run Now you're gonna lie that run was pretty decent the replay angles on this track kind of suck, but unfortunately We can't go back and look from ahead unless I used free cam But unfortunately they can't get my free cam to work right for some reason never wants to seem to work for me I just don't think I have the settings or anything right. So that room is actually halfway decent. So The tune is definitely not perfect. I definitely need to change the tune up and do some work on this tune because it is nowhere near Qualifying or competitive Ready at all. So we may go hop into the Bushido series server and see if anybody's out there trying to do some tandems But this car on this track is gonna need a little bit of work Try to enter without having a break No Would have saved that but that was a much much Unwanted angle stall we're gonna reset our tires here a very unwanted angle stall I gotta get a break the habit of tapping the brakes when I initiate with a handbrake because this track I don't need to hit the brakes and I feel like that will definitely be a problem in my initiation points rocking him Entering in with the brakes and handbrake same time a little less for break was not a problem Well, technically right for break was not that much of a problem because you needed to slow down You couldn't really use angles for the off-gear or off the position. So this track is more than just chuck it in Don't touch the brakes Don't do that. Oh, I can see a lot of cars Smacking that wall here on this track So this track is it's gonna take a lot of practice and a lot of finesse to get it going Rightly, so you guys don't are subscribed to the channel Make sure you do that and tap that bell notification when part of the notification green would appreciate all the support so let's Give this a go Chuck it in Too much too much that's gonna be the wall. Oh, man This track is now forgiving and I have a lot of work to do for this around if I want anywhere near to be competitive enough to qualify I mean last time I didn't qualify, you know in the 40s Or at 40th 47 position. So I was pretty happy with my scores 70 and 75 Dang a little shallow on that one hard rotation there That's not good So let's try to go back to pits Change up the view I need to go into the right screen there we go now now I can change up views Having a set out in a while apparently This is not the view. I wanted This is not the view. I wanted so I don't have My hood view really set up because I think I uninstalled my game. So unfortunately, we're just gonna run in this one Don't have head motion turned on or the act goes on. So I'm not gonna go first person that well Better managed to fill those So for sake of Just trying it. We're gonna send it in Cockpit view without head motion is gonna be very interesting I'm feeling we are gonna smack the wall hard I have if I had my oculus plugged in I would run this in oculus But competing in the oculus is definitely not the easiest thing to do right now Too much and there's no restaurant like I bet we decided to bring out the BRZ to see Maybe I made the mistake and chose the wrong car To register with what we're gonna try this car on see cuz some cars are better at certain tracks and others But unfortunately registration closed for the track showed up.  So I decided to pick the car that I'm most comfortable in This car doesn't handle too bad Honestly didn't handle that bad. I feel like with a good tune this car will I'll be Be very dominant in this series for this track now. I'm going to try one more time. Maybe try another car But like I said in the beginning, I'm gonna need a lot of practice at this track in order to Be super comfortable in order to even think about, you know being good in qualifying That was a massive angle throw. Oh Little wall grace so BRZ not my forte So let us let us go try the other car that I used that I was gonna register in but I decided not to and that is The 180 so this car is definitely one of my favorite body style cars S13 chassis and these body styles definitely one of my favorite ones So we're gonna give this one a shot here To end this episode off all the boost All the turbo lag But I feel like this track is mostly on power. So heavy boost cars will probably be very good Because most of the track is mostly on throttle Should downshift in the third The lack of the boost control in this falling out of boost is not very Presence because you're mostly on throttle with this course. It's a quick change over riding probably should go into third With this car. So we're gonna give it one more shot here before we end this episode off First look at round four of the sheet of practice more to come here for you guys Oh, oh, no, yeah, we lost it definitely not comfortable in these cars so as always I thank you guys for watching hope you guys enjoy this episode first look and you can see the progression of my Driving in the next episode while I practice for Bushido series round four here on a set of course So as always I thank you guys for watching. I'm your rabbit. I'll see you guys on the track


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And so he was walking towards us like we got a distance though He was walking towards us and for whatever God showed me that he he did something with his hand And I seen that he ain't have nothing in his hand. So I start busting out Oh You what were you from carp? Was it the carp screw? I was born in a town called Tav, Texas. Okay, right? I lived in a small town called Aransas past Texas I went to kindergarten First grade Second grade and then moved to a town called Bay City, Texas And went to third grade and then moved to a town called vanver leg, Texas And went from fourth grade to 11th grade And this my senior year I left vanver leg, Texas and moved to houston And went to north shore and channel view for my senior year and I quit school My 12th grade year the second semester So but when you're dealing with all when you're dealing with all of these small towns No, y'all want to know it all right?  So did you experience it racism? Yes, I've experienced racism. Yeah Tell me about an instance where it was blatant in your face. I was driving me and my kind of folk I'm the oldest one.  Hey y'all stand behind this door because I'm strapped And there wasn't I don't know if there was or not But the one of the white dudes got out with his hand behind his back The other dudes was getting out too, but I'm just paying attention to him really because it's him because his hand behind his back And so he was walking towards us like we had a distance though He was walking towards us And for whatever God showed me that he he did something with his hand and I seen that he didn't have nothing in his hand So I started busting at him And didn't hear them. I don't know That's the way it be like we you know, uh, yeah that really and and and that ain't nothing but uh a part of what Happens when you get out of line With some real, you know, we young so I get where you come from because I've been there So, you know, you don't wait to see When you when something like that go on either most of the time you move around And you move around quick because you know, these white boys in the first play But you say you don't know but then I don't think when you start shooting at somebody They go you go either see them fall or you're gonna see some not necessarily because I'm at a we had a distance at a distance Right. So I'm shooting and it's multiple and he didn't shoot back because he didn't have a gun. It's multiple of them Right. I'm no wonder. Did anybody shoot back? You could hear anything? No They was portraying like they had something. Did you jump in a car and drive off after that? Yeah, I told my cudd like man, we I we I didn't have time to study the situation. Okay Just asking And I've seen them get to one of them could have got here. I don't know Man, it wasn't reported on the news. No homicide. No, none of that wasn't no It was just happening in the broad day with us and some white dudes But you know, that's a part of what goes on sometimes in the south, man You know a lot of times in those days it was going down now They're not as blatant with it, but it still goes on, you know Uh in a precipitated fashion


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So today, we have Mr. Tony Bell joining us as Senior Director, Office of Program Administration with the National University, and we are so thrilled to have you here with us, Tony. Again, this is our fifth and final episode during this Power Week, and we've been doing the hashtag Power Week each and every day, Tony, thanks to you and thanks to Fundraising Academy for joining us for this dedicated episode. You know, again, we had mentioned in our Chitty Chat Chat or our Green Room Chatter, there's so many wonderful, wonderful elements from the call-selling education model that many of you can use into your day-to-day operating systems, processes. I have done that recently and it's just been wonderful. Thank you, of course, to Fundraising Academy for not only being a Power Week sponsor but also for being a presenting sponsor with us each and every episode. We are the only national nonprofit broadcast, and we could not be where we are today without the continued support from our sponsors, each and every one of them. So please take the time to check them out, not now, but in about 29 minutes. We don't want you to miss today's episode because, Tony, we always say that Friday is one of our favorite episodes of the week because this is when we have dedicated each and every question that comes in from our viewers, from our sponsors, from individuals on social media, and they send in their questions in a variety of ways and we answer them. And that is exactly what you've joined me to do today, so welcome back and thank you. Thank you so much. And congratulations again on the success of the Power Week concept. I remember when you were floating the idea and just to see it happen and to see the success of it and to see the added value that it brings to the audience and to the sector. So I just wanted to wish you congratulations on the success of the concept. Well, thank you. Yes, absolutely. And thanks for jumping right in. We named it Something Similar to I Think What Comes on the Discovery Channel. It might rhyme with... Well, I probably shouldn't rhyme it right. Shark Week, kind of a mentality.  And so we've been able to do that again thanks to you, Tony, and the team. Absolutely. So this question is for Tony. We're diving right into your expertise here. So Leah in Denver, Colorado asked this question of you, Tony. Leah says, I'm quite impressed with the cause selling cycle program, but I cannot get my other development team members on board with the process. What should I do? And can I do this by myself without my team? It's a great question, Leah. And the snarky answer is leave them in the dust. But that's not the best, most collaborative partner kind of way to, you know, team player kind of way to approach this. So first of all, yes, you can implement it on your own. It's certainly, you know, more effective if an entire team is kind of leaning into the same process. But yes, you could be highly successful, you know, leaning into the cause selling cycle, because it's going to enhance your relationship skills and the success that you have in building relationships with, you know, potential investors and donors for the organization. One of the ways that you might consider getting them on board, and I think about Julia when I answer this way, because Julia and I both have talked about, and Jared, you've leaned into this as well, how we wish we had this tool early on in our career. And now that we have it, we can lead into it and embrace it. But what we're kind of learning to is that we were already doing some of these things, right? We were already actively engaged in some of these strategies. But we didn't consider them part of a full and complete and successful process. So I think that if you were to share some of the clips of the nonprofit show with your team members around cause selling, that they too might say, especially some of the ones that have been in the sector for a while, may too realize that they've been doing some of this all along. And here's how it fits into a larger process. And oh my goodness, here's a strategy that I knew about and somehow it just totally escaped my toolbox. And I haven't stepped in and looked for that tool in a long time. So that would be my response to that question. That is a great response, Toni. And as I think about the variety of organizations in which I've had the great honor to work with, some organizations have very robust systems. And that means they're donor database, others not so much, right? And so there really is, I believe, a way to integrate many of these cause selling, I want to say methodologies or elements, whether you have something super robust or not. I think, as you said, there's so many ways how we can incorporate the use of this. So Leah, I love your question. Maybe you should leave them in the dust, but I have a feeling when you do the cycle, they're going to be left in the dust anyway because everything works better with a plan. Everything works better with knowing what the next step is. So lead by example, I think is a great way to say, this is what I've been using and see how it makes a difference in your efforts. Absolutely. Yeah. And let us know how it goes. Because I think this would be really interesting. I know the whole lead by example is a great way in many lifestyles and structures. But it might just be, Leah, that your team recognizes the value and will say, tell us more. Absolutely. Tell us more. Okay. I think, too, just before we go off of that completely, and I think that's the importance, too, in team meetings is sharing your successes and the little successes along the way. And cause selling certainly allows you plenty of opportunities to celebrate the small successes along the way. So in those conversations and as you're sharing those small successes, you can relate them to the cause selling cycle. So folks aren't just seeing the benefits of the cycle when you get the gift, but the benefits of the process. Yeah. That's a great tip, too, because we all want to celebrate success. Absolutely. For sure. So Robert, in Los Angeles, California, Robert asked the question, I would like to reset our development team goals according to fundraising academies cause selling cycle, specifically tracking the action items from the different phases. And I usually refer to this as moves management. And so I know that that's, you know, when I use that vernacular to me, it's kind of the same. So it's tracking those actions in the phases. What would be the top three to five things that we should track in our CRM? Well, Robert, it's a great question. And I love how you're, you know, you're taking the opportunity to, to marry these strategies with your technology. I just, you know, I really celebrate how you, how you view the value of, of the combination of the two. And, and Jared and I were talking about this earlier before we, before we started. And we are also seeing clients and other organizations doing the same thing. So the first thing I would recommend is taking a look at the steps and determining what's best for your organization in terms of how you measure success.  But there are ways that, that you, you know, some ways that you can consider doing it that you could recommend. So one would be just in the three phases. And that was something that Jared and I talked about, simply phase one, phase two, phase three, and, and using that another way. And one of the ways that, that we are looking at integrating it into our donor management system within our organization, we're looking at prospecting approach, the ask and stewardship. So those are, are the four steps that we're looking at. So with prospecting, we're including the pre approach within that prospecting category. And then with approach, we're including the needs discovery, the presentation, and the handling objections would all fit there. And then of course, the ask and stewardship. So, so that's just kind of a quick answer, Jared, from me around what I think in, in ways that folks can integrate the cycles or the actual steps into their CRM. I think that's great. And I'm curious, Tony, if you have any insight, this is a, you know, off the cuff question here, how we might be able to look at our CRM or our donor database, customer relationship management system, and see what already exists by way of acknowledging these action steps per Robert's question. So do you have any insight to say, okay, let's look at our database, let's see what functionality exists. And now let's couple that with our cycle. Yes. Yeah, but I think it's a really good question. I'm not an expert in, in this particular space, but this is what, this is what first comes to mind is making sure you have clear definitions around what you're seeing in, in your CRM. So, and it's a, that's a great exercise for, for anyone, pardon me, some of us still have landlines that we forget to turn off. You're very busy. We get it.  So, so, and I think it's something good for organizations to do on an ongoing basis anyway, is to take a look at, you know, at your CRM and, and these areas and make sure that everyone's still in agreement with the definitions of, you know, of that. So with your existing CRM, that would be my, my recommendation. Look at the data, look at, at your categories, make sure that they're clearly defined and that there's consensus on the definitions of what you have. And then you could see how, how they may or may not just organically fit with either a site, either one of the steps or, you know, one of the phases of the cause selling cycle. So that's what, that's how I, that's my initial thought and approach. I like that. No, I think that's great. And, and so Robert, good luck with this. You know, there is lots of nuggets of information that Tony just shared when it comes to tracking those top three to five things in your CRM. So you're off to a great start and I can't wait to hear how it progresses. Ooh, this is a dual Judy and Matt in Kansas City. Judy and Matt write in and they ask, we are putting our entire fund development group into the cause selling process. Congratulations, by the way. Yeah, I love it. That's great. Yeah. Should we do a training for our board members as well? They are a large part of our fund development. This is such a good juicy question. I love, love this question. So yeah, so, so one really excited to hear that the entire team is going to be leaning in and to cause selling that, that of course makes us feel really good about the product and the curriculum. So I always feel like fundraising is a team sport and that board members are definitely a vital player on, on that team and an important player on the team. So just from that particular lens, I would absolutely support the board going through cause selling training as well. If you think that they would be overwhelmed by the entire process, then you might want to give them an opportunity to lean in and be trained on a particular phase that they're interested in, maybe survey them and say, you know, we're, we're, we're doing training on the cause selling cycle. The cause selling cycle is in three phases and eight steps. We'd like to invite the board to join us. Here are the phases or the steps. Which of these are you interested in? Please select all or, or the, or any, right? So, so giving them an opportunity to select what they feel like they're most interested in, in learning might be one way to go, to go about it. So one, I think just from the lens of fundraising being a team sport and board members being, you know, critical players on the team, absolutely. Then there's the other side of board development. And what I feel like is important for board members to engage in some type of professional development or professional learning that is connected to the nonprofit sector. As they would in their for-profit sectors and wanting to know what's the latest and the greatest, they should have that same understanding at some level of what's going on in the nonprofit sector. So cause selling I think fulfills two of my missions or visions for boards. And that is one that they are an active player in fundraising, but also that they lean into some type of professional development or professional learning, you know, connected with the nonprofit sector. You know, I agree. And I think this is a wonderful opportunity. There are many videos that fundraising Academy has produced several with us here with the nonprofit show. So there's an entire YouTube channel and that is a great tool to share. You know, and I'm thinking too, on a sheer educational informational point, this should absolutely be shared, I believe with your board and in particular your fund development committee, so that they understand your process, right? So when you have a breakfast that, you know, really speaks to, okay, these are the individuals that we want to bring into our breakfast. This is where they fit into our cause selling model, right? Perhaps they're in phase one. And perhaps we've already done the Madden test with them. And for those of you that question, what is the Madden test, right? I encourage you to go back, take a look at the video that we've done with Tony. It is a wonderful step and resource to identify who are the individuals that we think we should invite. So I think really having that education as you're speaking to Tony is phenomenal. And as you move through your year and your various campaigns, relate that back to the model, relate that back to say, this is where we are with this particular project as it relates to the model. And you brought up, yeah, that's so good, Jared. And you brought up, I think, a good point too, around just the library of pre-recorded, you know, just the library of digital content that's available around cause selling. And so you can think creatively around how to engage your board, you know, in that. So perhaps they are asked to review a specific episode of the nonprofit show and then you convene them and you have a conversation around what they saw and heard and learned and how they can, you know, actively implement that or how that ties to your development department's strategies and how that supports the goals of the organization. So you can get really creative in the way that you engage them in the curriculum because we continue to build a really robust digital library of content. Yes, absolutely.  So I'm still a fan of it. I like it, but that speaks to my personality and to my Thesbian degree. Sure. So anyway, if that works for you, Judy and Matt, hopefully, hopefully that will bring value. Well, and there is tremendous value.  And there's just, there's just no denying that. Right, right. Oh, I know. I mean, it's kind of the same with an icebreaker, right? People are like, no, I don't want to do that either. Okay, so Chandra has sent in our question. I believe this might be our final one of the episode, Tony. Okay, okay. Chandra asks our states, I would like to have our internal newsletter to our staff, which is about 75 individuals include a culture of philanthropy point or culture of philanthropy tip. And I feel that we need to get all of our team members thinking about fundraising. Is this too pushy? I, well, I don't think it's pushy at all. I think that including a culture of philanthropy point or tip in a newsletter is pretty soft, actually. I think it's, it's kind of a soft approach and a, you know, a good way to inform folks. But I don't think it's pushy at all. I would also consider if it doesn't already exist as part, you know, within your culture of philanthropy point or tip, some type of mission moment as well that, that celebrates a success, you know, for the organization and outcome of a program or a success, you know, around the fundraising strategy. But no, absolutely. Yes, all day, every day, every newsletter, that's not pushy at all. Not pushy. And I, and I think, you know, as we just talked about, our board members understanding the cycle, our fund development committee understanding the cycle, why not the team, right?  And I just believe the more people that are informed and understand the process or at least the intention behind the process, right? It seeks a win-win end goal, and that's what we're here for. And I do really appreciate the approach because the question was about building a culture of philanthropy. So it isn't so honed in on tools to fundraise, right? And it really is around building a culture. And that allows for so many topics within the newsletter. So some that, like, like I was saying, some that can be very specific to your mission. But it really does open up just a wider lane for themes and subjects that could exist in the newsletter, if your goal is to build a culture of philanthropy. And I heard recently, culture of generosity. And I loved that. I was thinking, you know, it's quite synonymous. Philanthropy is the act of giving. Generosity is, you know, being generous, perhaps in what you provide and give. And so I liked that culture of generosity phrase as well. Well, what I like about that is I think it sounds more welcoming. I think it implies that there's room for lots of people at the table to be generous. You know, philanthropy can often be perceived as something not obtainable by folks who want to be generous. And let's be honest, it's kind of hard to say and spell. I'll tell you, sometimes I would rather, it's funny you say that, but I'd rather, you know, spell philanthropy than entrepreneur sometimes. Well, and I think that's because we are in it. We hear it most often and frequently, but you're right. I think philanthropy comes with this grandiose title, and it's really not the amount of zeros that you put behind your donation. It is that simple act of giving. That is the definition of philanthropy. However, as you were saying, Tony, I do believe that it kind of, you know, comes across as hard to achieve. It's hard to get to that philanthropic level. And let's just say philanthropy as many times as we can right now. But it really is that culture of generosity and that culture of giving. It really is. But so I do, I love that culture of generosity because philanthropy, especially in today's environment, is valued in many different ways. It's valued in, what do we say, time, talent and treasure. So we're historically, when folks would hear the word philanthropy, they would only think about, you know, the monetary contribution that one can make to an organization. But that definition has been expanded. And I love, you know, hearing new ways to say it. So again, so that it's more welcoming, more inclusive. Right. Absolutely. And we, that's what we want to focus on is that inclusivity that everyone has the ability to make a difference truly. Absolutely. So important. Well, great question that came in, Chandra. Thank you so much for asking that. We wish you the best when it comes to including your culture of philanthropy or generosity point in that staff newsletter. I think that's a phenomenal idea. It sure is. It sure is. What a week, Tony. I know that today is your, your episode with us today. We've had Jack Elotto on. We had Pearl Hoaglin. And we also had Linise, I'm missing her last name, Andrade, right? Well done. Yes. Okay. Well, they were each spectacular. We talked to this entire power week again, hashtag power week on determining what a major gift is and how that might be defined within your organization. We talked about the major gift fundraising cycle, the traditional cycle, the cause selling cycle. So make sure you go back and take a look at that. We talked about prospecting for these major gifts and prospecting for the donors themselves. In stewardship, that was Linise's topic yesterday. She was such a phenomenal professional. I know, I know that I could sit and chat with her for hours. She was just a wealth of knowledge. And so it was a very robust week. And of course today with you, Tony Bell, it's just been fantastic. So thank you to everyone that has joined us for this nonprofit power week. Each and every one of today's and this week's I should say episode has been dedicated to major gifts. So Tony, what's what's happening at fundraising academy that you might want to send us off with? Is there anything that we should know? Yeah. So you know, I'm thrilled to share that we have a cause selling cohort that'll be starting in February. So for anyone that might be interested in earning a certificate in cause selling, they can go to fundraising academy.org and and take a look at that opportunity. I mentioned earlier we're building our digital library. So pretty soon we will have a digital portal for the fundraising academy with all kinds of great resources available to the nonprofit sector and and look forward to those enhancements to our program and look forward to our continued partnership with the nonprofit show. Well, thank you. The Accelerate program, I know that that is something coming up in February. I think there's still some more openings. I know I was interested in that and I've certainly shared some information with some of my colleagues. So if that piques your interest to anyone who's watching, make sure you check that out. There is still some room available and it looks like a fantastic program. It really does. It is. I mean that you know, aside from great curriculum and great takeaways, the relationships that you build through that cohort experience will stay with you your entire career. And it's a national. So it's not just your local community. You're able to really, you know, stay in touch and create this cohesive cohort team throughout the nation. So thank you for providing that opportunity and thank you to being a presenting sponsor with us each and every episode right along with our other presenting sponsors. You can see on the screen here. Just in a few minutes would be a great time to check these out. So if you stayed with us and you've eagerly been sitting on the edge of your chair wanting to look up more of these sponsors, you will have that time in just a little bit. Tony, thank you. And for anyone, everyone that is interested in finding Tony, this is where you can find him. He's also very active on LinkedIn and is very welcoming. So if there's any question that we didn't get to answer here today, please do make sure that you reach out to Tony and the National University Fundraising Academy. So it's been, it's been phenomenal. And again, that wraps up our nonprofit Power Week. While the episodes might be wrapped up, they exist in perpetuity. So make sure you check them out on our archive.  And Tony, you and your team for joining us for a fantastic week. Thank you. Thank you too. I mean, the time goes by too fast when we get together to do these. It does. And I think that's partly because we have such a shared passion for the nonprofit sector and for all of the great work that goes on out there. So we definitely want to send our thanks and gratitude to all of the folks out there that are raising funds to incredible causes, making a huge difference in their communities. I couldn't have said it better. Absolutely. And with it being a fryer, hopefully that means that each of you gets a rest this weekend. So if you're in a cold climate, I hope that you stay warm and stay well so you can do well. We'll see you back here on Monday.


You don't train for power and look for a burn or look for a pump in the muscle. There is no fatigue involved with developing power. Developing power is learning how to explode. In other words, if you're doing a jump, you jump as hard as you can after you warm up and everything, right? You jump as high as you can and then you wait until you feel like you can exert max power again, however long that takes. And then you do again, when people do this at the gym, they do not train for power.  In which case you're not developing power at all. You're just working on stamina.