So, up to now the logic that we have been using has a continuous drive to the load all the time. That means if the output is a 1 or it is a 0, then it is continuously driven to 1 or 0 by some drive, okay. Now, there is a particular style of logic which is possible only with CMOS. So, the original logic styles which developed in MOS followed the bipolar style and those styles were continuously driven styles. Those CMOS added this extra thing of low power by making sure that if pull up and pull down are there, then only one and exactly one of them will be on at a time. The natural question then arises that you have a pull up and you have a pull down. So, there are four combinations of these two, on and off, right? So, we have allowed only two combinations. That is to say the pull up is on and the pull down is off or pull up is off and pull down is on, right? And that makes sense that if you say to drive to 0 or 1, this is what you should do. But what happens in the other two cases? Now, obviously both of them being on is destructive, right? If pull up and pull down both are on, then power will just go from VDD to gram. So, that is not useful. But the other combination is what dynamic logic uses. That is to say what happens if neither is on. So, if both of them are off, what happens is that in case of MOS devices, no current is drawn from these nodes. And therefore, these nodes can retain for a pretty long time the status of 1 or 0 on that node, okay? There are only capacitive loads. The outputs go only to gates of transistors. So, there is no DC drawn. And once you charge up a particular node to a 1 or a 0, then if both the drivers are off, then that node will retain its value of 1 or 0. This is called dynamic logic. This is how DRAM works, for example. But essentially rather than using a latch for storage, you can just use a capacitor for storage, okay? Now, this is extremely advantageous if it can be used because a latch takes a lot of space and consumes power. Whereas a capacitor takes very little space. In fact, you do not add a capacitor. Just the parasitic capacitances provide the storage. You do not actually lay out a capacitor. So, therefore, simple circuits, similar to very similar to CMOS logic, not needing a new technology, can now be built which will consume very little power. And the only requirement is that they should not be left undriven for long periods of time. Because if you do not drive it for a long period of time due to parasitic leakage and so on, a node which has been charged to 1 might eventually leak down to 0 and may cause errors. So, as long as you can make sure that these things are driven pretty frequently, then there is no problem. And now you can reduce the area required for implementing a function and you can also reduce the power that this circuit will use. That is the basic idea behind all the dynamic circuits, okay? So, essentially some nodes are required to hold their logic value as a charge stored on a capacitor. Now, here is an example. Essentially what we have done is that we have taken a CMOS inverter, okay?  So, this is just like an inverter and this by itself will ensure that only at a given time both pull up and pull down cannot be on. Right? Remember there were 4 combinations. So, this one will rule out both being on at the same time. Because if the clock is high, then this guy is off. If the clock is low, then this guy is off. So, there is never a direct path from VDD to ground which is nice, okay? Now, in addition to that we have borrowed from CDO NMOS and we have that same logic style. So, from the output node towards ground we have inserted a switch combination which follows the rules that we had earlier described, okay? So, as you can see this will be A plus B because they are in parallel dot C because C is in series whole bar, okay? So, this will then implement this A plus B dot C whole bar, okay? Now, the way it works is the following. When the clock is low, then this guy is off and this is on. Because this is off, there is no current in this direction, there is current cannot flow in this direction. Whereas, this is on. So, as a result this capacitor gets charged up to VDD, okay? So, this capacitor is unconditionally charged to 1. Then when the clock goes high, this charging stops.  This transistor now turns on and depending on the values of A, B and C, the output if as a whole this switch is off then the output will remain charged to 1. If as a whole this switch is on, in this particular case either of A and B must be on and C must be on, right? So, if that condition is true then the output will be discharged to 0 through this path, okay? So, this works nicely now. No current just like CMOS. This is a low power technology. But the point is that if the output is supposed to be 1 then there is no discharge. If the output is supposed to be 0, it is conditionally discharged to the output, okay? This kind of logic is called dynamic logic. Very often we include a clock which makes sure that this charge is refreshed, okay? Suppose the output is supposed to stay 1 for a long time then what happens is that this pre-charge will not take any power actually. You might think that this is wasting power by charging and discharging a capacitor unnecessarily. But if the output is supposed to be a 1 then it is already charged up to 1 last time and it was not discharged. So, if this transistor comes on during the low phase of the clock, so what? This capacitor is already at VDD. This is also at VDD. Therefore, even though this gate is turned on when the clock goes low, no current flows. No current is drawn from VDD. So, as a result no power is actually wasted. This is discharged only when it must be discharged to make it equal to 0, okay? So, this is a useful style of logic implementation. Notice that now we have that advantage that each output now goes only to an n-channel transistor, okay? So, therefore the capacitance is lower than in CMOS and therefore the dynamic power is lower, okay? In CMOS this output would have gone to a PMOS as well as NMOS. Whereas now inputs are only NMOS. NMOS transistors are smaller than PMOS transistors because of higher mobility. So, capacitor is inherently smaller and on top of that only one transistor needs to be driven, not both. So, as a result the dynamic power is also reduced, okay? So, I will just introduce an very interesting tussle which has occurred in design styles and that is this. See the static power is whatever it is. It is some constant as a function of frequency, right? If your signal frequency changes, the static power will not change. Static power remains. It is just a leakage power. On top of that the dynamic power that is given by C V squared F, okay? Now for a given implementation V is constant and for a given gate C is constant whatever its load with respect to frequency. So, as a result the power has this kind of behaviour with frequency whereas this is the static power and the dynamic power increases linearly with frequency, okay? Now the idea is that I want to reduce this power and there are various approaches to reducing this power. So, one thing is that I can bring the whole thing by reducing static power, okay? And that is what CMOS does. So, it reduces static power to zero, right? The other thing is that you reduce the slope of this curve, okay? Now what determines the slope of this curve? C V squared, right? That is the slope. Therefore, you reduce voltages which is why you have scaled down technologies or you reduce C. Now reducing C means good layout, etc., etc., but you can go only that far. Reducing V, there is a particular voltage that you have chosen for operation, etc., etc. So, you would use as low a voltage as possible but remember that reducing V reduces the speed. Remember this was the trade-off that we did when we did the logic. So, as a result, you can reduce V but only up to a limit, okay? Now interestingly, many modern integrated circuits actually operate different parts of the IC at different voltages. So, what they do is that if some portion need not work at the highest possible frequency, then they give it a clock which is divided by a lower clock and at the same time reduce its voltage. That way, at least that part of the circuit consumes less power, okay? And very advanced power management techniques need to be employed, otherwise none of the modern ICs will actually work. So, that is called dynamic voltage switching and you then have to have circuits which will translate the output of a low power supply module to a high power supply module, okay? But coming back to the dynamic this thing, the other thing is that this frequency is actually the average rate of switching. One other technique is to reduce the rate of switching called the activity factor, okay? Now, the disadvantage that the dynamic circuits have is that the activity factor is very high. That means switching takes place at every clock, right? And the clock is the highest frequency signal. So, therefore it has a slight disadvantage. But on the other hand, it has the great advantage that this value of C is very low. The load capacitance is very low. Why is it low? Because it is going to only one transistor. Now, typically P MOS to N MOS ratio is 2 is to 1, right? So, the total loading is like 3 in case of C MOS. In this case, the total loading is like 1 because there is only an N MOS. So, you have a 3 is to 1 advantage in the capacitance. Now, you might say that look great capacitance is a very small part of the load. The actual load is from the interconnect capacitance. But even there, this has a great advantage because the N well is far away. Therefore, if you have to take a line to N MOS as well as to P MOS which has to be far away because the two wells have to be isolated. The interconnect capacitance is also very high in case of C MOS. So, you have a minimum gain of a factor of 2 in interconnect and a factor of 3 in gate capacitance, okay? So, you gain by a factor of somewhere between 2 and 3. If you use dynamic circuits, okay? So, essentially what we are trying to do is that C MOS static reduces this but cannot do anything about this slope. Whereas, C MOS dynamic can reduce this and can reduce this slope substantially. Unfortunately, it has to operate at a high point here, okay? So, if your signal itself requires switching very often, then there is nothing lost in having a high activity factor and those are the conditions in which dynamic logic is most important, okay? So, you got the motivation of going to dynamic logic otherwise why should we bother? The C MOS is supposed to be low power and so on. But what really happens is that C MOS looks like this. Its static power is nearly 0 but the slope of this line is very high, okay? Because the capacitance is very high. So, everything to the right of this intersection point favors dynamic logic and everything to the left of this intersection point favors static logic, okay? Now, it is the effort of the static logic designers to push this point as far to the right as possible. So, that static logic is optimum. And it is the effort of dynamic logic designers to reduce this slope and thus push this point to the left as possible. So, that dynamic logic is the optimum choice, okay? So, both camps then try to optimize their design styles and of course we are impartial, we will learn both. So, we have spent some time learning static and now we should see how the dynamic logic operates, okay? This provides the motivation for learning dynamic logic. However, for this to be successful, the circuit has to work. If it does not work, then all bets are off, right? Then who will use this? So, there unfortunately happens to be a flaw with this circuit. It looked very impressive when we analyzed it but there is a particular flaw with this circuit where in certain circumstances it will cause problems. So, let us see what are those circumstances. When you cascade this logic, single stage works perfectly as we had discussed. But if you cascade this logic, then we have a problem, okay? So, let us consider this case in which we have that same old logic stage which we had which was A plus B dot C whole bar, okay? And we are giving it to an inverter. Inverter is the next stage, alright? Now, this is the waveform for the clock, alright? And now, let us consider the waveform at X. Now, if A plus B dot C is false, then there is no problem, okay? Why there is no problem, alright? When the clock is low, this node X charges up, okay? Now, because A plus B dot C is false, that means either both A and B are 0 or C is 0, then there is no discharge path. So, this output remains put at 1. Okay? Because this remains put at 1, at the same time that this guy got charged up, this guy will also get charged up here when the clock is low, right? So, when the clock is low, this output charged up and because this is 1, right? This one, this will, when the clock goes high, this will discharge, right? So, as a result, the output will be 0, which is what you want. This is after an inverter. So, therefore, this should give you A plus B dot C. Since A plus B dot C is false, the output should be 0, okay? So, when A plus B dot C is false, there is no problem, okay? Just to go over this very quickly. During pre-charge, both these capacitors charge up, okay? Because A plus B dot C is false, this capacitor remains charged high, okay? As a result, when the clock goes high and this lower transistor turns on, because the input is high, this capacitor is charged through this path and as a result, the output goes to 0, which is what we expect. No problem here. The problem comes in the other case. When A plus B dot C is in fact true. In that case, what happens? As before, when the clock is low, both of these charge up, okay? When the clock goes high, that is when problem occurs. When the clock goes high, now this transistor is on and this transistor is on. Now for quite some time, this output will remain high, right? So, it will start discharging. But at the same time, this guy is sampling X and it will start discharging this output to ground. Now depending on the time that this stage takes to discharge this capacitor, this capacitor will be wrongly discharged. It was never meant to be discharged because this output was supposed to be 0 and therefore this guy was supposed to be off. But because the sampling takes place at the same time and for some time, this guy is not valid. So, that invalid value leaks away this charge and depending on how much leakage is there, this might remain at 1 and be restored the next time or may become 0. So, therefore this circuit will actually fail. So, what do we take out from here? That the circuit is quite promising, but on the other hand there are problems with it and that problem is non-symmetric. If the input is inactive, that means for an N switch, if the input was not changed, that means if the output of the previous stage was 1, then there is no problem. But if the output of the previous stage was supposed to be 0, then because for some time it is invalid, that causes problem to the output. So, this is the problem with cascading of a simple-minded dynamic logic that we had constructed at that point. So, obviously we need some correction to this and there are two separate ways of correcting this. We will look at both of these ways. Now, one way is after we analyze why is this problem occurring? This problem is occurring because in this stage the power supply has already been turned off, the p-channel has been turned off when the clock goes high. Now, if the input is active, that means if the input is 1 wrongly, then that will cause problems. If the input is 0 wrongly, then there is no problem, right? Because if the input is 0 wrongly for some time, that means this guy does not discharge this, but when the input becomes 1, then it will discharge it, right? So, that is not a correctness problem, that is a timing problem, right? So, that is an asymmetric problem. I hope you have followed this, that this problem does not occur for both combinations of logic, okay? It occurs when the input is wrongly 1. If it is wrongly 0, there is no problem because eventually it will become 1, though for some time it is 0 and being at 0 for some time does not cause any problem to the output, okay? So, essentially the tap is off, so you are not wasting anything. When the tap comes on, it is fine, you will do whatever you need to do. But if the tap is wrongly off and your storage of water is limited, then you may empty out your tap. So, the water being left on wrongly is a problem, the tap being left off wrongly is not a problem, okay? So, eventually you will turn the tap on, alright? So, therefore there are two solutions. One is that the problem is that this guy is by default 1. Why not make it by default 0? Then there will be no problem. That is one solution, okay? The other solution is that the problem is that we have been too hasty in connecting these two guys. If this guy had started sampling only after this guy had settled down two values, there would not have been a problem, right? So, these are the two parts to correcting this problem. One is to insert a time slot in between giving the time for the previous stage to stabilize and only then connect it to the next stage. Then there is no problem, okay? The other thing is that do not have the dangerous logic level as the default level. Do not pre-charge it to 1. Pre-charge it to 0 and conditionally charge it to 1. Then if it is wrongly 0, no problem. Eventually it will come to its right value and then you will evaluate the outcome. So, two different logic families have developed as a result of following these two different ways of correcting the problem, okay? Let us look at those. The first one is a four-phase dynamic logic. Obviously, this two-phase clock will not do. You need an extra phase of the clock at least to insert for completing the evaluation, okay? So, at least a three-phase clock is required. There are three-phase clock solutions. We are looking at a four-phase clock here because it has some advantages, okay? So, what happens? You have actually four clocks which are on only in phase one, phase two, phase three or phase four, okay? These are non-overlapping clocks, okay? So, clock one is on during phase one, the first quarter. Clock two is on only during the second quarter. The clock three is on only during the third quarter and clock four is on only during the fourth quarter, okay? And then after in the next, the clock one comes again, okay? So, essentially you have these phase clocks like this, one-two-three-four, one-two-three-four, right? So, you have four clocks. And now you can construct complex clocks. For example, clock one-three is a clock which is the ore of clock one and clock three, okay? Which will be on during one and three. Clock one-two, clock two-three, such clocks can be constructed, okay? This is the complication of multi-phase logic. But once you assume that the appropriate clocks will be taken to different logics, then the problem gets solved, okay? Now, notice what we do. You have a pass gate here, okay? So, this is our old friend, a plus b dot c. Same circuit we have analyzed it. There is not much problem, okay? Now, we are using this complicated clock, okay? So, rather than giving clock here, we give it clock one-two-bar. Now, this is only a complication in name. It is a same old clock actually. What do you mean by clock one-two-bar? This is a clock which is zero in one and two. And it is one in three and four. So, it is the same old clock actually. It is just two periods wide, right? So, nothing has really changed. We are just calling it by a new name, okay?  So, really not much has changed here, alright? So, clock one-two-bar gets applied here. Now, let us go phase by phase. In phase one, what will happen? The clock is higher low, one-two-bar. Therefore, it is low in phase one. So, in phase one, now this switch is clock two-three, right? This is on only during two and three. So, in phase one, this is actually off. This switch is off, okay? And this transistor is on because the clock is low and this switch is off, okay? This everybody agrees? In phase one, this clock is low. As a result, this guy is on and it charges up this capacitor, okay? This is the pre-charge phase. That is all that happens in phase one, okay? Now, we go to phase two. In phase two, this guy is still on, clock one-two-bar and this guy is still off. But now, this guy is closed. As a result, this capacitor also charges up, okay? So, as a result, both these capacitors are now charged high at the end of phase two. What happens in phase three? In phase three, this clock goes up now, okay? So, this transistor shuts off. This transistor comes on, okay? And these two capacitors are in parallel because this phase three, this is on. So, this combined capacitor is now evaluated by A plus B dot C like before, okay? So, now at the end of phase three, phase three is that safety phase in which nobody is looking at you, okay? So, at the end of phase three, the evaluation is complete. Then, in phase four, what happens? This switch goes off. Whereas, this is still on, right? So, phase four, this output retains its value, which is valid, okay? And it will also retain it during phase one. Remember, this one will be pre-charged in phase one. So, essentially, this circuit evaluates in phase three and its output is valid in phase four and phase one, okay? This is somewhat like noise margin. That means the input needs to be valid only in one phase of the clock. But the output is valid in two phases of the clock. So, the output is more generous than the input in timing sense, okay? Input needs to be valid only for one phase of the clock. The output is valid in two phases of the clock and this type of gate is called type three, okay? Type three gate is one which evaluates in clock phase three. The output is valid in four and one, okay? So, this is the four phase logic. And now, all gates have a restriction. So, you have type one gate, you know, just by cyclically permuting these clocks, you can make type one, type two, type three and type four gates. Now, notice, type one gate evaluates in clock one. And when is it valid in two and three? The two subsequent phases, it is valid, right? When it evaluates, then in two subsequent phases, it remains valid. So, therefore, type one can drive a type two gate and a type three gate, correct? Similarly, a type two gate can drive type three and type four. Three can drive four and one and four can type one and two, right? So, as a result, when you distribute logic, you make sure where the input is coming from, okay? And you have to make sure that the input is coming from the correct type of logic. Only then will it work properly. The other input, other technique, makes use of the other factor. That is to say, to en masse, a wrong one is dangerous, but a wrong zero is not dangerous, okay? So, then what we say is that, alright, I will put a static inverter here, okay? Now, when this is pre-charged to one, the output will rest at zero, right? That is not dangerous to the next stage. And then, when it conditionally discharges, should it go to zero, output will become one, okay? So, that seems to solve the problem. Then why do we bother about that four phase clock at all? It introduces a very bad problem. What is that problem? Our original logic was inverting. Now, this has become non-inverting logic, okay? You cannot produce functions which are non-inverting because of this extra inverter. Now, any function can be constructed out of inverting logic. But you cannot construct any old function with non-inverting logic, right? So, now the problem is that if my logic needs an inverting logic, where am I going to get it, okay? So, this is very often true in this business. You solve one problem and it unleashes another problem on you. This is the second problem that we now need to solve, okay? However, it is not too bad to solve because after all, who says that these switches must be N-MOS? You can use P-MOS switches, okay? And while a one is dangerous to N-MOS, a zero is dangerous to P-MOS. So, if you do not want to put an inverter here, make sure that this output goes to P-switches. And the output of that goes to N-switches, okay? So, you have, ultimately, like in the previous case, P-switch cases, N-switch cases, P-switch cases, N-switch cases alternately, okay? That logic is called NORA or zipper logic, okay? It works like a zipper. If you have ever examined how a zipper actually works. So, there are these hooks from both sides and a hook engages from this side, then a hook engages from this side, then a hook from this side. So, that is like a zipper. So, you essentially have, notice that here, these are P-MOS switches. The output is pre-discharged by the clock in the same phase while this is charging. And this output is presented to P-MOS switches, which conditionally charge, okay? You just inverted ground and VDD and change N-MOS to P-MOS. So, if this output is wrongly one, that is what it can be. It can never be wrongly zero. If this output is wrongly one, it will just hold the switch off for some time. Then when it becomes zero, this will turn on, okay? So, this will evaluate correctly. So, this kind of logic is called zipper logic and sometimes it is called NORA for no-race conditions, okay? There is lots of tasty stuff to be done for dynamic logic. But this introduction to dynamic logic now will suffice. Now, we will stop here. And then we will go over to the little discussion on HDL, largely for motivation of HDL, meaning a generic discussion of HDL rather than specifically VHDL or very long.


Hey, everybody, it's Brian and welcome to the 55th Qt tutorial with C++ and GUI programming today We're going to be covering the Q SQL query model and we're just going to make a GUI application And call it my Q SQL query mod Pretty horrendous application name. I know starting to run out of ideas if you have any ideas for application names Just let me know maybe I'll start naming everything bacon or something And then we'll say a Q dialog Next next finish finish and we're going to have a very basic Layout here because I'm pressed for time. We're going to throw a tape of you out there And first thing we need to do is update our project file give it a reference to SQL And notice how it'll re-scan your project over here once you do that All right now we have to add in our includes we'll say include And I've gotten quite a bit of flak for doing this and I apologize. It's just much faster We'll say Q SQL Forget the T in there. That's why it's not coming up. Hmm, of course as soon as I say it's faster. It's not faster That's just how life works there we go And include all right got our includes in there now what we need to do is we need to set up our models So say Q SQL query Model right there, and we're just going to call it model And if you've been following along in my other tutorials with the model view architecture This is nothing new. The only thing you're doing is you're creating a Q SQL query model So the underlying data source instead of our file system or custom data is going to be the SQL database So let's just jump right into dialogue CPP here and we're going to set up our database connection and we'll say Actually, we should back up here and actually throw it over here in our header We'll say Q SQL database. Whoops, and we'll just say whoops DB Equals sorry Q SQL database and remember we want to set up our driver. So we're going to just add the Q OD BC and Then we want to set the host name Very important to do the double slashes. Otherwise, it'll see as an escape character And I'm using SQL express but you can use whatever database system you want We're going to set the database name and in previous tutorials I created a DSN and Let me show you that DSN super quickly here because we're pressed for time in some of these videos There's my DSN 32 if you have no idea what a DSN is or what I just showed you Please go back and watch my other tutorials. I cover that pretty in-depth. All right Now What we need to do is set the query, but first thing we got to do is open the actual database We're gonna say DB dot open. We'll close our connection here. We'll say give me that close Somebody's probably gonna mail me and yell at me and say you can't close that during the deconstructor But you know what? Let's just try it. So let's compile and run And let's just make sure there aren't any horrendous bugs in our application here. All right So our application starts. There's no major meltdowns going on Let's continue So first thing we need to do is set our model so we'll say and we're going to say new cue SQL query model and Then we want to set the query. So we'll say model and we're just going to flip over to our SQL express management studio and I've got a here's my SQL server I have a test database and I have a table called people and in there I just have some columns ID first name last name And we'll just go script table and select new query window And you can execute that and you can see this is the result it returns I have Bob Hope will Smith and my daughter Heather Karen's who is now famous forever ever more and we'll just Format the string and select this and That is our query string and that is how it populates the data the data will not be in there until you do a set query So then we'll say UI table view And we'll say set model and we're going to give it the model Save and run and with any luck this will build correctly and there's our data that is how you do a Q SQL database in a model view architecture Using the Q SQL query model now. You should note that this is not editable. You cannot edit this at all What we will be covering in the next few ones are how to edit this data and it will automatically persist it back into the database for you So this is bright. Thank you for watching. I hope you found this video educational and entertaining


What is up guys, KarmaMedic here and welcome back to another dose. In today's video I'm going to be joined by three of my very close high school friends Yasorn, Steffi and Yanni who are all now doctors living and working in London. I've written down a whole bunch of questions from biology, chemistry and physics and we're going to see just how much high school sciences these doctors can remember. Let's get right into it. Everybody has a different sound on their buzzers that we'll know who hit it first. Yasorn, what's your buzzer? Okay, Steffi. Perfect, and Yanni? First one's a biology question. Okay, I will admit this is probably the hardest question that I wrote. I was hoping this one wouldn't come first until a good start. The functional unit of a muscle is called one. Yasorn? Sarcomen. Yes, Sarcomen. Let's go! There you go, that's one point for you. Ooh, physics. Name a noble gas. Zeno. Nice. What? It was the last column in the periodic table. Yeah, I do remember it was in the last column. There were like five easier ones, you know. I don't remember the hard ones. No, this is physics. The other one was chemistry. Yeah, I swear that was a chemistry question. I didn't want to say it.  Okay, the first physics question. A magnifying glass uses what type of lens? Concave. Physics one again. The phrase for every action, there is an equal and opposite reaction. It's one of many questions, but also incorrect. The phrase for every action, there is an equal and opposite reaction. It's one of Newton's three laws of motion. Okay, biology. The first mammal to ever be cloned was a sheep. Nice. Oh, she got high five. Biology. Osmosis is the movement of water from earth. Here's a joint, make a noise. Go on, Steffi. Osmosis is the movement of water from an area of high concentration to an area of low concentration across the semi-permeable membrane. Oh, very nice, Steffi. Biology. Which of the following is the strongest muscle in the human body by weight? Oh, wow. Okay. I had four options. Hector Alice Major, biceps brachii, masseter, latissimus dorsi. Masseter. I mean, I need my five options. Gregor Mendel is known as the founder of modern genetics. What type of plants did he use to establish the rules of chromosomal heredity? Biology. A group of cells working together to perform a specific function are known as What are the four stages of mitosis? Prophase, anaphase, metaphase, and telophase. Can you put them in the correct order? Okay, fine. You flipped metaphase and anaphase. Yes, that's correct. What does GMO stand for? Teletively modified organism. Nice. You guys both need that in here? XS barium nitrate solution is added to 200 milliliters of 0.2 moles per liter sodium sulfate. What is the mass of the solid form? One graph. 0.05 grams. Two grams. This is a complete joke question. I do not expect you guys to know that answer. Is it ten? It's a joke. I don't even know that answer. Five? Five? Five? Five? Five? Found in the back of the human eye, this type of cell is responsible for detecting color. What is the functional group of an alkene? There is a bonus question. What is the functional group of a ketone? Is that a C double bond OH? No. OH? It's a C double bond OH and then it joins to something else. Like another organic. I hope I have not remembered this wrong. I thought it was C double bond OH. Oh, you're probably right. Let's do a quick summary of the points here. Wow, it's two four six. You guys are actually very close. In a chemical reaction, what is the function of a catalyst? A catalyst lowers the... Yeah, the thing. Is that exactly what you're thinking of as well? Is it something? When you say it, we're going to say it. You're holding that. It's to lower the activation energy of the reaction. Fill in the blank. Oxidation is the blank of electrons. No? The first ever antibiotic discovered was by Alexander Fleming. What was the name of this antibiotic? I don't know who did that. Who did it first? Yeah, you get it. What is the atomic number of the element sodium? Do you have nothing to lose? Eleven. Geez. Nice one. Which of the following nitrogenous bases is not present in oxygen? It's not present in RNA. Sightseeing, uracil, thymine... You have to pick a scissors for that one. Or me. I'll give it to you. I think it's thymine. And it's uracil. Nice. What is another name for programmed cell death? Who did that? You guys have no say on the count of three. Three, two, one. I'll give it to you. You guys have no say on the count of three. Which of the following is a water soluble vitamin? Vitamin D, A, K... Did I hit it first? I didn't even like the original. We've not even had it yet. Again? Which of the following is a water soluble vitamin? D, A, K, C. C. Molecules are furthest apart in which state of matter? Solid. Gas. One of you two. Gas. Complete the sentence. An endothermic reaction is one which? Energy is absorbed through the process of the reaction, resulting in a lower energy state at the end compared to the beginning. I accept that it's a reaction that absorbs heat. What does DNA stand for? Right after an egg is fertilized by sperm, the resulting cell is known as a... Psycho. What does a eukaryotic cell have that a prokaryotic cell does not? A nucleus. The planet Earth can be found in which galaxy? The Milky Way. The bone known as the trapezium is found in which part of the body? Carpal bones. Carpal bones in the wrist. We didn't give an arbitrary. In the plant, where does photosynthesis get placed? Who smashed that? In chlorophyll. My country. When the plant does photosynthesis get placed, in this organelle you can find chlorophyll. In the leaves. I thought this was an easy question. A letter starts with chloro. Chloroplast. That's right. What is the second element of the periodic table? Lithium. Lithium. Globano. It's also begins with an H. My gosh, it can touch my brain. It was time for you to get a second chance. Let's try it out. The cell's plasma membrane is composed of a phospholipid bilayer. The middle of this layer can be described as Hydrophilic. What is the chemical formula for hydrochloric acid? Hydrochloric acid. This is the last one. The last one, yes on your chance to tie. Yeah, and your chance to secure the win. Yes, put some special music in this game. Oh no, don't let it press the buzzer. Which digestive enzyme is responsible for breaking down protein in the stomach? Protein. Like a pepsin. Oh, it's not a pepsin. So, in an interesting turn of events that I had not planned for at all, both Yasun and Yanni are at the tie with 13 points. Hello darkness, my old friend. Deppy's sitting out for this one and we're going to do a quick sudden death round. I'm going to ask them three questions and whoever scores the most points out of those three will win the entire competition. Okay, first question. A cell from the heart would probably have an unusually high number of one. Calcium ions. What is the energy currency for most organisms? That was big. It says ATP. Ice. Give me the ice. Well done man. So, the competition is over and Yanni has been crowned the winner. So congratulations, well done. Thank you guys so much for coming. Maybe you learned something new. Last thing before we go, I hope you guys all something small just to say thank you for coming and participating in this quiz. They are in this order of delivery if I remember correctly. What do you want? I want a pink one. Thank you so much. Thank you guys for participating in coming today. I guess that brings us to the end of the video. Thank you guys so much for watching. I hope you enjoyed it. If you did enjoy the video, please do leave a like on it and also subscribe to my channel to see more content from me in the future and I'll catch you in the next one. Peace. Bye. Smash that like button. Everyone ready? Sorry, sorry. I just need to hear it so I know when to start because, yeah, should we get started?  You also said 6 H2s. H2os. You said H2s. Playback. You said H2s. Playback. This is a bust. The cathode attracts ions of what charge? Can we get a replay on that? I don't even think I did my best. That's it.


Unpopular opinion.  Hey babe, just want to let you know that women on the internet are beautiful. I'm a feminist too? That's good! I love natal girls, like you shouldn't have to change anything, not even for a man. Exactly, like I don't even shave my legs. What was that? Yeah, I just threw up a swallow bit quick. Are you okay?  I just, I gotta go. What is a truly like to be a man in today's society? What are the difficulties? Let's see. There's no point in getting married anymore because divorce is basically incentivized. Why would an aging woman who's losing her sexual market value want to be with a man when she could just take his money? And his children. And his house.  Everyone believes women when they make false allegations. And even if they're proven to be not true, your reputation is still damaged for life.  Women want you to do and provide everything for them and change into whatever they want you to mold into, but don't want to change at all themselves. And society praises this. Women always talk about how they want a man above six feet, but when a man talks about how he wants to fit chick, he's body shaming. Nobody has our backs, not even our brothers. Men destroy men in the name of women because they bite night. We're completely disposable in today's society and nobody cares. Exibility check. Touch your toes. Eye kick. Do the split. Not a question. Where the hell are some of y'all getting all this money? Where's it coming from? Y'all have extension. This girl's stitches were turned off, but she goes on the stage.  She understands that some of it is free, but like, how are you affording all of that? Me and my boyfriend talk about this all the time. Credit card debt. I think so many people within our generation are living in credit card debt, because sure, they're influencers that get some things free. But like she said, not everything's free all the time. And the majority of the people on your Instagram feed are not influencers. They're your friends. They're people that you went to high school college with. And I do a lot of these things that this girl was talking about, like getting my nails done, I got the dermatologist, I go out to drink school on vacation. I afford this through a lot of teamwork privilege, and I've worked really hard and have a great job now. And I do not know how everybody is affording this. Like I afford it, but it's not like I'm just like blowing the money, you know? And I understand some people are probably in a similar financial situation than me, but I know not everybody is. And I also understand parents' money exists. But the majority of it, I really think it's credit card debt. This video's for all the perverts on TikTok. If you're not one of them, keep scrolling. They gone? Cool. So if you beat up to my videos, can you send me at least $5?  It's only fair. Triple the... Sir, I'm 25 years old and I sleep with Disney characters, and I make TikToks in my free time. So don't give me those rookie numbers. I'm polyamorous and I have herpes. But I don't have herpes because I'm polyamorous. I actually probably called herpes from my grandmother, who I kissed on the cheek as a child. Because guess what? Herpes can be passed by non-sexual means.  Did you know that 67% of the world population has herpes according to the WHO? And that 80% of them don't know it. Because guess what? The most common symptom of herpes is no symptoms at all. And also did you know that the herpes stigma was actually engineered by Big Pharma in the 1970s? They were trying to sell the drug as syclovir and they weren't making enough money. So they generated stigma through advertising and scaring everyone and fear mongering. To make everyone think this was a horrible, incurable disease when actually it affects most of the population. So by buying into herpes stigma, you're buying into capitalism. And this is also just really generally uncool.  See how we live in a world that makes fun of guys who cry but 80% of suicides are guys. Okay, this one is for dudes. And this is a perfect example why feminism is beneficial for men. A lot of you think feminism is hating men. It's not. It's about taking down patriarchy in its oppressive norms. Even though men are the ones who benefit from patriarchy the most, they're still victimized to an extent. You can think of it as misogyny being a two-way street. Patriarchy tells men they shouldn't be vulnerable or show emotions. It uses misogyny to label those things as feminine things. So when men get vulnerable or emotional, they're criticized, made fun of, told to be a man not to act like a woman. That's toxic as f*** for men. Because men end up puddling up their emotions. They have nowhere to seek help for. And they don't know how to deal with these emotions. Patriarchy oppresses all of us. Some more than others, yes. But all of us. So men need to be a feminist also for their own sake. Honestly, I have to come to terms that everything revolves around women and men are the problem. And no, I'm not joking. I'm being completely serious. Like, I want men to answer. Like, you men tell me who or what is going to carry your baby for nine months. Feed it and erase it so that you can create your little empire that you've got going on in this f***ing matrix. Oh, like, seriously, tell me. I want that question answered. Because you men are constantly trying to bash us, right? All the time. Oh, for talking like this, or being like that, for being too possessive, for not being possessive enough, for wearing too much makeup, for not wearing enough makeup, for being too weak, or being too tough. Like, there's no winning with you guys. But we are winning.   Where? Mother Earth. This is something that just doesn't sit right with me. I'm built like a f***ing linebacker. I look like I could play in the NFL. What's up, bro? F***ing. I want to be dainty. I want to be a f***ing princess. But look at me.  Goddamn, Gabby.  Want to settle down? I want a relationship! I'm a good person! I'll rub your feet! I'll cook for you. I have kids.  I'm 30. I'm Latina. I mean, what are you so afraid of? Message me if you're interested. This is the most beautiful ring ever. My heart went f***ing f***ing. Hey mom, what are you making for dinner today? What the f***? Rice and chicken. Mom, what are you doing? What I'm doing, I'm on Facebook. Facebook? Mom, what are you... What's happening? Billy, that's your second beer already. And I'm your second baby daddy already and you're not complaining.