So, welcome to this lecture on VHDL as part of the course digital system design with PLDs and FPGA, before going continuing with the lecture we will have a quick run through the last lectures portions. The last lecture we have completed the data types basically the composite and the integer real scalar type. And then we looked at the concurrent statement with select statement. So, a quick run through the slides, so let us go to the slide. So, we talked about the data type integer. So, what is predefined in the standard library and how to use it and the real type which is probably less used and a physical type you know the time with the unit as femtosecond you can check what is the latest the VHDL standard kind of basic unit must be femtosecond only. So, that is the various units specified and we have it is possible to define subtype on a type. The advantage of defining subtype is that you can use all the operators unlike you if you define your own data type then you need to overload all the operators functions which you need to use for this particular data type. And this shows various user defined data type enumerated these are integer these are this is real and this one is a physical data type and this is a subtype. And we have looked at the unconstrained array and we said that standard logic array is defined as unconstrained that is why we constrain it when we use it. And you can have multi dimensional array any number of dimensions. And we have seen an example of that and you can have record whereby you can kind of you know related signals or variables can be put together. And this shows some input output enable of tri-state gates are put together and you can assign like in record in structure in C the similar syntax is used and you can see that the component individual component within is accessed with the dot. And if you have some signal a part of it can be aliased like we have used the top address line of an 32 bit address is aliased with the top AD. We have also seen various ways of assigning the rows this is a positional you know kind of association this is named association this is like a string. And this one is again positional association with this others hexadecimal based specification. And if you say others means that everything is you know one value that in this case it is 0 the other case it is tri-state. So, this is very useful one because if you have say a 32 bit bus which you want to kind of output you know something is connected to 32 bit bus. And you want to initialize it to you want to tri-state it you do not have to write you know keep on writing z and counting at 32 times and all that just say others that the most useful form of array assignment. Then we have looked at the important part concurrent statement as the name suggests this is used in the concurrent body that is in the architecture statement region. This cannot be used within a function or a procedure or a process it has to be straight away used in the concurrent body or the architecture statement region. So, the syntax with select when is with some you specify some input you say select for all mutually exclusive values of that signal you specify the output the numerical values or as a function of some other inputs ok. So, we said that is nothing but the truth table in the simplest case we have seen an AND gate say a1 and a0 and for all the 0 0 0 1 1 0 1 1 the value the output is specified just simple truth table the equation is wherever there is 1. So, that minterm is the equation or if you have multiple ones then you say or if you have two ones then you say or and that to it. So, wherever one is there you pick up that minterm or the next one and so on. And this we write when others to for the simulator to completely specify all input combination because standard logic can 2 bit standard logic can take 9 into 981 values. And we are only specifying 4 of them. So, rust 77 is you know covered here. So, you could even say 1 when others but as I said you know specifying some known values will help you debugging like you know that some of those kind of combination occurs then the 0 can happen even you can say tri-state does not matter because it is useful for debugging you know. And next we have seen the case where the output is specified for all the values of input signal A as a function of B and C okay. And that is a little more complex truth table. So, you see when A is 00 then Y is B. So, Y is 0 when B is 0, Y is 1 when B is 1 and so on. And the C is do not care. So, this expands into multiple rows of the each one is expanding into kind of 2 rows of the truth table. But when the equation is written it is kind of A1 bar and A0 bar and B or like so this is straight away this choice is A1 bar, A0 bar and B is Y or A1 bar, A0 and B bar. And so each one is a minterm or a product term or this or and so on it goes the equations. So, that is what is shown here. And we have seen that the same thing and one thing to remember is that whenever there is an event on A, B or C the simulator computes this. And as far as the synthesis tool is concerned it will look at the you know look at the description and form the equation that is the simple as it is. And this can be used for you know example is shown with a multiplexer. So, natural choice for the select signal is this the select signal of multiplexer. So, for various combinations 00, 0, 1, 1, 0 Y is A, B, C, D like 0, 1, 2, 3 and the equation is like this you know the select 1 bar and select 0 bar and A or and so on ok. So, each one is a minterm or this one, this one, this one and I am showing only YI. So, because for a bus you know whether it is 4 bit or 8 bit the equations are same you know exactly similar for each bit of it because it goes through the same type of and or structure. And it is easy to confuse this kind of syntax with the multiplexer function but we have seen that any combinational circuit without priority can be easily specified by with select. So, if you have multiple inputs one output then you pick up some input and for all the mutually exclusive values of B you specify Y as sum of A and C depending on your logic and that is what is which selects provide you and this is there is no priority actually this is for all it is a plain truth table with little abstraction maybe it will translate in your bringing A and C. So, some more columns are added some more rows come into picture. So, it is still a kind of straightforward truth table and as I said if you have the output has the same function or same values for different choices of the values then you can use or and that is what this example say. So, that is what is the with select concurrent statement. So, let us look at the next one which is when else which is little more complex than the with select. So, please have a look at this syntax. So, which says that you have some output signal it could be a single bit or multiple bit it does not matter you have an output signal which is assigned some expression and this can be a numerical value like 00, 01 depending on the width or it can be some input condition input expression you can say A and B or A, A bar or whatever okay. When condition 1 that means condition is again an input you know you can say C is equal to 3 or P greater than Q and so on. So, some condition based on the input then you say else which is not there in the with select okay. Else some other expression when some other condition okay else and so on okay and at the end we say and else which is that means everything else is expression Y okay. So, this naturally brings in the priority okay that means we are saying output is some expression when some condition. Suppose we are saying a condition A equal to B and we say suppose this is 2 bits and we say 00 when A equal to B then we say else it means that A is not equal to B okay and we say another condition say D greater than B. So, it means that the output is maybe this is 00, this is 01, output is 01 when A is not equal to B and D is greater than 3 okay. When you say else it means that it is not this condition and not this condition that means you say A is not equal to B and D is less than or equal to 3 then maybe the output is expression 3 and some other condition okay. So, as you go down the note of all the previous condition is coming into picture okay. So, it brings in priority first thing to note that is that there is a priority. So, it is a little more powerful because you see this condition 1 can be in terms of 2 signals and when it comes to condition 2 it can be another signal another group of signals and this expression itself can be some inputs. So, it is quite a powerful quite an abstract statement much more powerful than with select and brings in priority and most importantly the question is that is it are we completely specifying a truth table by this kind of structure or syntax that is a question. You think about it whether it is a truth table the answer is yes it is a truth table but it is much more abstract and I will show you soon very quickly I will show you this is nothing but a truth table a complete truth table is specified in terms of all the inputs involved that we will see in a moment. So, let us look at how the equations are derived for the combinational circuit from this syntax.  So, you have an output signal and expression A when condition 1 else expression D B when condition 2 else expression C when condition 3 and so on ok. So, the equation comes like this output signal is expression A and condition 1 when I say and condition 1 is equal to working out the product terms all the product terms of the condition 1. So, it can expand into multiple product terms ok. So, it may be like you say D greater than C there could be some you know product terms in terms of D and C or and so on ok. So, there could be multiple product terms. So, it is still abstract but then the meaning is that the equation is expression A and condition 1 or and when you come here it is a nod of condition 1. So, expression B and nod of condition 1 and of condition 2 ok or when you come here it is expression C and nod of condition 1 and nod of condition 1 condition 2 and condition 3. So, it brings you know it expands like that and if you remember your basic course you would have seen a priority encoder you will see there is an AND gate as it goes down to lower priority from the higher priority. There is an AND gate with lot of bubbles you know becoming bigger and bigger. So, that is similar thing is happening there but there it is you know the single kind of normal is a single bits which is going to the AND gate nod of the previous inputs and so on. So, it is quite powerful. So, let us see an example and I want to illustrate how it is specifying the complete truth table. So, let us take an example Y is a single bit signal ABC are single bit like Y is output single bit ABC are inputs which are also single bit but these are inputs P, Q, R are inputs and they are all 2 bits you know. So, you have P1, P0, Q1, Q0, R1, R0 and so on ok. So, you can imagine a truth table with P1, P0, Q1, Q0, R1, R0 and ABC and Y ok. So, imagine wherever the values of P is greater than Q irrespective of the conditions of R, ABC, so B and C, Y gets A and when it comes other rows like P is less than or equal to Q. So, wherever the rows in the truth table where P is less than or equal to Q all conditions all rows and R is equal to Q we write Y is B ok. Else for all other rows we write C. So, it completely captures the truth table but it is very powerful I will show you the truth table. So, I have put it I have kind of compress ABC ideally I should have put in the input section this is the input section this is the output I should have put ABC also but to save space I have included ABC in the output expression but it is easy to understand ok. So, in reality the truth table is much bigger than this. So, you look at this scenario where the P1, P0, Q1, Q0, R1, R0 are the inputs Y is the output. So, look at this scenario where P1, P0 is 0, 1, Q is 0, 0, R is 1 care. So, here P is greater than Q, so the output is Y is A. As I said you should have an A column then if A is 0, Y is 0, A is 1, Y is 1. So, it is simple you can derive that and when it comes to this case you see P is 0, 1 and Q is 1, 0. So, the P is less than Q then R you look at the value R 1, 0 this is 2 then as specified the Y is B. But in other cases where P is less than Q and R is kind of not equal to 2 the Y is C and you can you know you can populate these values all the way from 0, 0, 0, 0, 0, 0, 1 all the way you know that all the way it comes to 1, 1 and 1, 1 you see is P is not greater than Q, R is not equal to 2, so this is C. So, this is a at least this truth table has 6 columns so it is kind of 64 rows but if you bring in ABC then it is 7 sorry 6 plus 3, 9 kind of columns so you will have 5, 12 rows for this truth table. But you see the power of this statement all that 5, 12 rows are compressed into 3 statement and many a times this is how we think you know we do not think like though we when you have a spec of a combinational circuit you write the truth table. But we always think in terms of abstract like this you know you have some inputs then the problem statement itself could be like this you know you have P is greater than Q then the output is this otherwise if some other input is equal to something then the output is this if none of this is then the output is something else and so on. So, that also shows that the language allows you to think real life but you should not lose sight you should not think that this is some magic ultimately this we are specifying the truth table. And a word when a simulator as far as simulator is concerned if there is any event on P, Q, R, A, B or C this Y will be computed or this you can imagine like a process with this ABC, P, Q, R in the sensitivity list. Any event happens on any of these input Y will be computed and Y is if there is another statement which is concurrent then that also will be computed. But as far as synthesis tool is concerned say it is going to look at say P greater than Q and there is an operator greater. So it goes to library pick up the greater operator and that would have been written as an already as a synthesizable code which shows the structure of greater than Q like some input greater than some other input. So, that will be replaced the synthesis tool will plug in that circuit here. And if you think this could be a kind of you know when a kind of multiplexer when this condition happens this input is left to the output if not and this condition happens this input is left to the output. So, this will be some kind of various operators implementation of operators some kind of priority and some kind of muxing happens ultimately as far as synthesis tool is concerned. So, we will see how the synthesis tool does this as we go along I am giving you a kind of taste of how things happen now only at the beginning. So, this just I have written the description in this code wherever there is P greater than Q where there the Y is a when it comes here whenever there is P is less than or equal to Q and R is to that is B. And for all other conditions C and any event happens on any of these input the simulator computes synthesis tool looks at the operator and infer the operator and replace it with the template structure from the library that is what is happening. So, let us take an example which is a priority encoder. So, you can imagine a I have not drawn the picture but then you can imagine there is a block where there are 3 inputs A, B, C single bit input which is encoded into 2 bit because we have 3 bits and so where the maximum priority is given to A next priority is B next priority is C and none of that happens the output shows 1, 1. So, the coding is that the prior which is output is 0, 0 when A is equal to 1 else that means A is not 1, A is 0 then and B is 1 then the output is 0, 1 and when it comes here A is 0, B is 0 and C is 1 then the output is 1, 0 and when it comes here none of this is 1 or A is 0, B is 0, C is 0 then the priority output is 1, 1. So, this shows a natural very simple example of using the when else maybe we will see little more kind of little more complex example with the when else. So, let us look at this example this bring in kind of 1 or 2 elements we have studied together the array assignment, the in out mode and when else everything is put together so that you get a taste of some odd real life coding. So, just please look at this structure it is a bi-directional buffer or a transceiver so please look at it. So, a bi-directional buffer gives you know the connects 2 lines in either direction. So, you see here when the direction is 1 and enable is 1, A is driving the B. So, you can imagine this as a some output section driving a bus or something like that this is where everybody is tied together similar structures. So, when direction is 1 enable is 1 this is enable and since direction is inverted here so this is disabled this is cut off this output is cut off though the input is coming here. So, naturally A goes to B and when opposite is the case when direction is 0 this is cut off because this is get 0 and the enable is 1 then this is enable. So, this part is cut off and B assume that B somebody is driving some output is driving this and B goes to A. So, mind you this is bi-directional you can drive it and somebody else from outside also can drive it. So, this has to be the mode of this B is in out mode of A is in out because in principle when this is cut off somebody can drive it and so on. So, this is the library description you know of the VHDL this is a standard logic 1164 and this is entity transceiver trans is port. We have two signal and which are 8 bit okay I am showing 8 bit because the condo signals are common for all the tri-state gate. So, AB is in out because of this structure standard logic vector 7 down to 0 enable direction is in standard logic and transceiver and we define the architecture as some name of this entity is begin and end this architecture names ends this part and this is where we write the concurrent statement. Now you see we are going to write this path first and this path because in the concurrent statement mind you you need to have a statement for one output and another one output. So, we are going to write B output first and then A output second. So, that is what we are doing B is an output B gets A when direction is 1 and enable is 1 else it is tri-stated. So, we say and this is a being a bus we say others you know assigned Z that is it okay. So, which says that B is gets A when both are 1 else it is tri-stated similarly we define the output A. So, A gets B when direction is 0 and enable is 1 else it is tri-stated you know this is tri-stated else others is Z ND flow. So, this shows how to use the when else in a more practical more real life case. We have seen how the in-out is used we have seen this array assignment the others close here. So, that shows an example of using when else another example of using when else. So, let us look at the so, we have completed the concurrent statement the concurrent statement is essentially two types with select and when else we have some loops we will see that you know together for both the concurrent and the sequential together. And the main concurrent statement are with select and when else with select is no priority output is normally specified as for all the values of some input the output can be specified as a simple truth table of numerical values or if you have other inputs you can write as a function of those inputs. In that case it translate into multiple rows of truth table. And we have seen some example of which select coding the next little more abstract one is when else which is little more powerful. We can specify priority we can specify condition in terms of multiple input the expression can be some other input. So, it can capture a much more real life scenarios from the specification given for a combinational circuit and we have seen how some simple three kind of choices can translate into a huge truth table. So, that is a power of when else and we have seen the coding for a priority encoder. And we have seen the VHDL coding for a simple bidirectional buffer or a transceiver with two controls enabled and direct. So, let us now move on to the sequential statement which are more useful more complex than the concurrent statement like with select and when else. So, let us move on to the sequential statement there are two types this is identical to what you have learned in a C language or sequential languages. So, you have if then else and case when only thing is that it is now kind of related to the hardware we are describing the hardware. So, all the equations are different you know it is not you should know what is the hardware behind it. When you use this statement you should know what hardware it means okay. It is not mere kind of some variables you are working in a sequential language okay that should be kept in mind. And I will tell you what is the kind of equations Boolean equations or the hardware you get when you use this syntax. So, the simplest syntax is like this if some condition condition one then some output get some expression of the input okay or numerical value it does not matter. So, if condition one condition in terms of the inputs then y gets else. So, the priority is there else means if not of this condition then y gets b okay. So, end if so a and b are input signal the whatever signals in the conditions are inputs. So, the equation is y is a and condition one or the moment you say else or b and not condition one. So, which is exactly similar to the when else okay. So, this one is exactly similar to when else. But mind you the sequential statement can be used only in the sequential bodies like process functions and procedure. You cannot write if or case directly in the architecture statement region of the VHDL code that is not possible. So, you should always use sequential statement in process functions and procedure. So, let us look at more complex kind of syntax. So, basically the conditions like in when else it is general conditions you can say p greater than q c equal to 3 and things like that and there is priority. So, the next kind of complex syntax is if condition one then y gets a instead of else you can say else if it is not ELS EIF it is ELS IF else if condition 2 then y get b else if condition 3 then y get c and then you say else which comprises of all not of all the conditions. So, you need to have when you specify the proper combinational circuit you should have the last else I will tell you what happens if not there. So, it is very important which comprises of everything else then only the truth table is complete okay. Because we are putting the condition which means some rows of the truth table when you say last else all other rows in the truth table that is what it means. And you can see that the equation goes like this y gets a and condition 1 or b and not of condition 1 and condition 2 or c and condition 3 not of condition 2 not of condition 1. So, exactly like when else it builds up you know as I go down when you come to the last one which is d and not of condition 3 not of condition 2 and not of condition 1. So, it is like a priority encoder it builds up and this itself can be very complex we are you know kind of abstract condition 1 condition 1 can be translated to multiple rows of the truth table. Lot of min terms or product terms it can come depending on the condition you put so that is if then else statement okay. Now I said it is equivalent to when else but so the question is if it is just equivalent to when else what is the big deal you know why you have to write a process and put this inside the process. So, can you kind of think of a reason how if then is different from when else. So, you look at the when else that the when else statement was earlier say here this is the when else an output is specified as some condition exactly like if then so what could be the difference between when else and if then think for a while. So, you can think of the C language that might give you a clue. So, basically if you look at it what it allows is that when you say condition 1 you could write another input you know you could write z get something z get something z get something. So, in an if then else structure you can specify multiple outputs okay that is one difference between when else and if then and that is very useful very powerful and so that is one you can specify multiple output and another thing again if you compare with the kind of sequential language like C you can write in principle say here if condition 1 then I can nest it I can say another if you can say if condition say 5 under this condition then why get say else why get something else and you say and if okay. So, you can nest if okay everywhere you know you can have a if here, if here, if here and so on okay and it is not that you can go on you know nesting it many synthesis tool limit the level of nesting because the equation can become messy and you are bound to make mistakes and so on. So, if then else is equivalent to the when else but it support multiple output it support nesting you know that is very powerful you can bring in lot of complexity in description by these two the multiple outputs and nesting. So, this is what I am going to show. So, you have say y and z output and 3 inputs a, b, c all are let say multiplied and now you can write say if condition 1 then y gets a z gets a and b else if condition 2 y gets b z gets c else if condition 3 then y gets c z gets a else y gets d z gets b and so on. So, this shows you that you can specify multiple output using the same if and the equations are similar you know how to work out the equation. There is no you know great you know complexity as far as the equation is concerned you have the same inputs in condition as column a, b, c as columns then you have a y output z output you can write the work out the equation say y is a and condition 1 and b and not of condition 1 and f condition 2 when it comes to z, z is a and b and condition 1 and or c and not condition 1 and condition 2 and so on ok. So, that can be worked out but if you are clever you should be asking a question say all fine you know it is great but this assume one thing that the condition for these outputs are all same ok. Maybe that you cannot the relation between the input and output are such a way that you have no way to specify like this you know z is a and b not on this particular condition you more restrictive under this condition some more conditions are required for a and b then you are in soup you know you cannot use this kind of structure. But that is where the nesting helps you you could write say if condition 1 y gets a then you can write if some other condition is met then z gets a and b else something else. So, you could further nest if to specify very specific conditions you require for multiple outputs. So, that is where the nesting is important. So, you can have a more complex behaviour or structures can be specified by nesting. Suppose we will not be like in the case of multiple output we will not have the same conditions you know satisfying all the outputs. So, you could have like this you know if condition 1 then maybe z is written here something then you say if condition 2 then y gets a else if y gets b and if then else if you know condition 3 or 4 then so on. So, you could nest if and equation as far as y is concerned it comes like this y is a and condition 1 and condition 2 because it is under this condition 1 we are putting or then you say you know b and not of condition 2 and condition 1. And when it comes to this else if condition 3 for say z or something like that then this condition 2 does not appear there and so you can work out. So, this is where the nesting is useful and let us come to another point okay. What happens if you miss else in a if case like you write if condition 1 then y gets a and we do not write else we just say end if and mind you this is a kind of valid VHDL syntax. VHDL support this the simulator support this synthesis tool support this. So, what is the meaning of this. So, you can attribute different meanings to it you can say if condition 1 is not met y can be 0 y can be 1 but these are less probable from the description. But what is the VHDL attributes or VHDL take this 4 as shown here okay. It is just by definition do not kind of argue on why this should be like that. But this could be the probable meaning and the VHDL take this in this way like it means if you write if you miss else it means that if this condition is met then y gets a else y is y itself okay. And that is funny that is dangerous okay. In the sense that it shows a feedback okay this condition is met some y gets an input if this condition is not met the output is fed back into the input that is the meaning of it. And I am showing and so there is a memory it memorizes if for this condition it is normal input goes to output if this condition is not met it memorizes the previous one. So, it is called implied memory because this code implies a memory or inferred latch or you can say this code infer a latch from the written code. So, that is why it is called implied memory or inferred latch. So, the situation is like this if y and a are single bits and there is a condition maybe p greater than q or whatever. So, that is the decode of this p greater than q when that is 1 a goes to the y and if y is if that condition is not met then this path is enabled and y is fed back and it is latched okay.  So, this you can replace by a 2 to 1 MUX with the select line. And the select line is the condition 1 when the select line is 1 a goes to b otherwise the b is fed back. So, this you can replace with the 2 to 1 MUX and with an inverter you get a latch you know that is a normal latch kind of RTL symbol. So, that is what you get okay. So, this is very valid and when you if you need a latch like this you can write a code like that. But the question is that can we have a latch in the concurrent statement okay. Concurrent statement like with select and when else the answer is yes because we at least in the case of when else because it is equivalent if then you can imagine you say when you say output is something when some condition is met. And you say instead of saying else you keep quiet you do not state that then you get a implied memory or inferred latch in a concurrent statement. So, or in the with select case you specify a condition a decode and you do not specify anything else you know then you get a latch. So, let us look at the syntax. So, with suppose you take with say this is a enable of the latch with enable select y gets a when 1 and we are not saying something for when 0 or when others okay. You say just say y is a when 1 and we do not say what happens when others that means y gets y when others okay that is the meaning of it. Or you can even say like this with enable select y gets a when 1 unaffected when others that means output is unaffected when for the other cases both are same. Similarly, for when else y gets a when enable 1 we do not say else then you get the same thing or you say y gets a when enable is 1 else unaffected okay. So, for concurrent there is a you know syntax called unaffected. So, it means that it retains the same output that is the meaning of it. Even for sequential statement there is a thing called null which will give you the same effect that means that here you can say instead of this you can say if condition 1 then y gets a else y gets null means y will you know remember the previous output that is the previous value that is the meaning of it. So, you could specify in principle null. So, that is how you write inferred latch or implied memory using the concurrent statements okay and unaffected and null can be used. And now mind you wherever you do not assign some output do not write unaffected and null you will get a latch okay. So, be very careful null does not mean you know initialising it to 0 or something like that. So, do not write null wherever you feel that something should be initialised to 0 null will give you a latch and do not write it unless you require it okay. So, let us see the use of this and you are not normally we use flip-flops as memory in the serious design you do not use a combinational kind of latch in real life. So, we do not use it okay. So, what is the use of this kind of implied latch. So, the first thing is that the implied latch or implied memory or inferred latch is useful in specifying the behaviour of latches and flip-flops or registers. So, we are discussing the combinational circuit now. So, we are discussing how the combinational circuit can be described using the concurrent statement and sequential statement. We have not yet gone to the sequential statement we are still discussing the combinational circuit. But when we go there we will see how this description helps in specifying the memory for memory part of the latches and flip-flops. But in real life when you write combinational circuit unintentional implied latches can happen okay. So, that does not mean that you will write code like this. But when you have complex code when you have a lot of multiple say one scenario is that we take this example and where multiple outputs are specified. Say here suppose you have y, z and maybe u is specified everywhere and you cut and paste you copy paste you know that is usual scenario nowadays a lot of copy paste happens. And suppose by mistake you forgot to mention z here okay. You copy pasted and you forgot to mention z here that means it essentially means z is z as far as condition 3 is concerned. So, when it comes to this choice that means condition 3 not of condition 2 and not of condition 1 z will be fed back to itself when you get a latch. And all the more not only in multiple output when you have multiple nesting very complex nesting which is unbalanced like you have an if and under that in various choices of if some as another if some does not have if and there are multiple outputs. It can be very complex and you can really miss some output to specify because it is little difficult to work out all the outputs properly. In such cases you can miss some output and you will get an implied latch. And it is extremely dangerous I tell you and this is one of the as far as I am concerned what I have seen is this is very common error and inexperienced designer commit in VHDL coding that is this implied latch when not in simple case because in simple case it is very evident when you have multiple outputs and when you have nesting very kind of complex nesting in the sense that is unbalanced. Then you will get you are bound to make mistake some output is not going to be specified properly for some condition and you will get a latch and mind you it is very difficult to debug that you know. And because when you make a mistake and you look at the code very less likely that you will kind of unearth that bug from the code. Because you are very sure everybody is confident nowadays and you look at the code 10 times 100 times you will not discover that error. And if you simulate mind you will never 99.99% you will not be able to unearth such an error by debugging in simulation. I will tell you in a moment what is the reason why it will not happen. And if you are giving it in a real life if you are in a design team many times the verification is done by some other poor soul and he would have worked out lot of test bench test factors for verifying the functionality even there it cannot be unearthed. So in a moment we will see why this is difficult to kind of debug. The first thing is that it is not enough if you verify all the condition like you have some inputs and you like suppose you have 4 inputs 4 single bit inputs. So you have 16 condition or you have say you have 10, 24 input test factors you run it through or even you have a 1 million test factors you run it very systematically 1 million test factors still this error won't be brought up. Why it is so is because suppose in our coding you miss one output in condition 3 ok. Now as I said you have simulated the million condition all the possible condition. But before the condition 3 you have suppose simulated the condition 2 for which this missing output had the same value say you are expecting in condition 3 some value. Suppose the test factor you have simulated for condition 3 the one before you simulated is condition 2 and suppose the condition 2 and condition 3 has the same output as far as this particular one is concerned then the output will be correct absolutely correct. So to unearth this error you have to work out a condition where the output is different than this particular condition. And if as a designer you inadvertently made a mistake you are very because that is by mistake you miss that and you have not realized this and you will not be able to make that condition to unearth this error. So the best thing is not to make some mistake you know make this mistake. So it is in real life also it is better some mistakes are better you don't make such a mistake like you drive on the wrong side of the road then you are bound to crash into somebody else in a two way road. So like it is better you don't make such a mistake you be very careful that you don't miss output and be very careful when you nest the if so that the implied latch or implied memory or inferred latch doesn't occur. So I think that is where the next statement we are going to look at is the case when and what we have left is the loops but maybe that we are coming to the end of the lecture we will look at it in the next lecture. So quickly we can run through the if then if then is identical to you know the case when else in the concurrent statement. So simple condition is if condition 1 then output gets something else output gets something else the equation is similar to when else the complex condition is you know you keep on giving various condition and then you say else for not of all the conditions equations are similar to when else the power comes from multiple outputs and nesting and you could specify multiple output when the conditions are not identical you can start nesting you can think of nesting in various ways and when you say if you write if under and if it translates to the condition 1 and condition 2 and when you come here condition 1 and not of condition 2 and so on. So you can kind of work it out and when you don't specify the else you get an implied latch and which is a latch which is useful and you can use concurrent statement to get the same effect and you can it is useful in specifying memory in the case of flip flops and latches but in the combination case when you have multiple output the nested if then unintentional latches can happen and as I explained it is very difficult to unearth in simulation because you made it my mistake to work out the condition is quite tough and there is no point in you know there are people who make a mistake which can be corrected in 5 minutes and next one week you will simulate to unearth that error it is not worthwhile you know you plan properly you code properly you go through the code you take any number of you know spend as much as time on paper thinking about it and design then less verification will be there you know an experienced designer or experienced engineer should plan properly go systematically so that with minimum iterations things work properly that is how you should you know work out things then you know rush through the things arbitrarily quickly writing cooking up something and for our debugging for our sorting out the problem what one mistake you made in 2 minutes can kill your 2 weeks of time many people's time so don't do that plan properly so that I stop here today with this when else and if then else which are kind of similar but if then it is complex more useful so next class we will take the case when and the loops so please revise it write some examples of your own using this statements so thank you I wish you all the best.