In the last lecture, we were discussing about various non-idealities in MOS capacitor system. We did talk about work function difference fixed oxide charge and interface trap density and how it impacts you know the capacitance voltage characteristics. You know today we will continue the discussion and look at some more non-idealities and after that we will look at parameter extraction from a capacitance voltage characteristics. Just to sort of recap what we have said earlier, if you have p-type substrate then the capacitance versus voltage curve for an ideal situation will look like this and if it is only fixed oxide charge this will essentially shift to the left because fixed oxide charge is invariably positive and on the other hand if it is due to combination of both fixed oxide charge and interface trap not only will there be a shift but also there will be a stretch out and that is what we said the C v could probably get stretched out something like this right and this could be in the presence of both fixed oxide charge and interface trap density depending on how much is the interface trap density and how much is the fixed oxide charge. Now typically today if you are looking at the silicon technology silicon CMOS technology we have figured out ways to really minimize both fixed oxide charge and interface trap density. Today routinely we get you know the fixed oxide charge in the range of less than you know 10 power 10 per centimeter square this is number if you want to actually get the charge you multiply with q that gives you the charge ok and similarly the D I T that is interface trap density could also be of the order of 10 power 10 per centimeter square you know this is the kind of technology that we have you know but in the olden days in the early days of silicon technology in this used to be very high in the range of 10 power 11, 10 power 12 per centimeter square kind of numbers right those were very high numbers but we have come up with various process techniques to overcome all these issues ok. So, and one other thing that of course if you start looking at some other dielectric not silicon oxide on silicon if you are developing a new dielectric then of course you could start with very high trap density then you need to optimize the process to minimize those trap density. Similarly today we are talking of building transistors on different substrate like germanium or you know compound semiconductors even there when you put an insulator on top of such a semiconductor your trap density may not be 10 power 10 you know your trap density not surprisingly will be in the range of 10 power 11, 10 power 12 kind of numbers. But then you need to optimize it and bring it down to these numbers if it has to complete with the kind of technology that silicon has today ok. Now in the context of fixed traps and interface traps there is one other kind of non idealities which is what is called slow interface traps ok. Now just quickly look at this typically in a silicon oxide system you will not see this slow interface traps ok. What it means is that you know it is not quite interface trap but it is not also fixed charge it does vary but it varies slowly ok. Now what is the implication of that you know the slow interface traps could lead to what is known as hysteresis in CV characteristics. Now when I say slow I need to sort of qualify that statement ok when I talk of interface traps I did tell you that interface traps do respond to the slow varying I mean that signal that is applied to the gate if it is slow varying that is because they have certain time constants to interact with the channel charge so that they can exchange charge ok. Typically the interface charge traps that we have they have time constants you know anywhere from you know microsecond to millisecond you know maybe a few tens of millisecond ok and that is why we call them you know they are fairly fast you know but if you have on the other hand if you talk of fixed charge it has time constant which is sort of infinite meaning it does not really change right once it is positive it just stays positive it does not get discharged and become neutral you see that is another extreme but if your oxide that you have put in has you know some extra defects there may not be exactly at the interface may be little away from the interface hence the time constant is little slower then you know you may have what are called slow traps and which may have the time constants in a few seconds ok a few seconds. Now what is the implication of this right typically whenever you do a CV characteristic right that is capacitance versus voltage characteristics you can sweep the gate voltage either from negative voltage to positive voltage or from positive voltage to the negative voltage and you can do both in which it is called a bi-directional CV characteristics right I have swept the voltage from negative to positive and come back from positive to negative ok. So ideally you know if you do this in the forward direction if your CV looks like this in the reverse direction the CV will essentially overlap on top of it this is what you will have ideally ok indeed this is what you will have in most of the silicon devices today you will never see any hysteresis that is forward and reverse CV are identical. Now this will happen if you have fixed charge even if you have interface state traps you know they will not really fast interface traps that is they will not really give in tries to any hysteresis ok because you know they are responding you know typically the CV measurement time frames are few seconds right maybe you know you go back here from minus 5 volt to plus 5 volt let us say you know that may take a few second and then you start coming back ok that is how your CV characteristic would look ok. Now what happens with the slow interface traps is that they do not respond during the CV sweep because that sweep is reasonably fast for them ok but once you are here you know you are essentially spending time once you reach this band bending the band bending does not change in inversion it is more or less constant and similarly the band bending in accumulation is also more or less constant ok. Now you know going up dial days coming back like this will be a matter of a few seconds during this time they would respond meaning only at this extreme and at this extreme they will respond ok because they are relatively slow they do not respond during the CV sweep ok. So what I mean by that again recall our discussion at this point our band bending will look something like this is Fermi level ok accumulation condition at this time the band bending will look like this inversion condition remember ok and you know here ideally you know all these traps should be empty and all these traps should be filled correct because below this Fermi level that is what we are looking at ok. But what happens with respect to these so called slow traps they may not be exactly at the interface but they may be little bit away from this interface let us say somewhere here and hence they take little longer time to respond they also respond to the level of Fermi level position that you have ok. So what happens is that let us say out here you have all the tabs empty ok and when you come here you fill all these traps right with the electrons ok and now when you are going back you have those extra charges in these traps ok and these extra charges stay put when you are doing this CV sweep right. So because you have these extra traps extra charge in this case when I have come from negative to positive I have this condition and when I am waiting here during this period and while I am coming back all these are now filled with electrons ok. Now you see when I am going back I have extra negative charge here and because there is an extra negative charge the CV will not trace the original CV the CV will actually go back like this why go back like this because there is an extra negative charge whenever there is an extra negative charge the curve shifts to the right ok if there is extra positive charge the curve shifts to the left ok. So it goes back like this in other words forward sweep will be like this a reverse sweep will be like this and hence there is what is called a hysteresis ok and whenever there are slow interface traps the hysteresis is always counter clockwise notice here while you are coming here the CV was like this and at this extreme you filled lot of electrons here and the charge is you know negative and hence it went in here and here you have lot of positive charge the CV will come here and so on and so forth. So whenever first of all if you see a hysteresis and CV characteristic that is indicative of the fact that there are so called slow interface traps which is also not good just as fast interface traps are not good even slow interface traps are not good and if the hysteresis is counter clockwise that is clearly a signature of the hysteresis is coming due to slow interface traps and you know it turns out you could also have hysteresis which we rarely have unless you know today we take lot of care in making sure that there are no impurities in terms of so called mobile ions such as sodium potassium and so on and so forth right. If you have mobile ions then you can also have a hysteresis which is called clockwise hysteresis hysteresis will not be a counter clockwise hysteresis hysteresis will be a clockwise hysteresis. So clockwise hysteresis is not an indication of slow interface traps whereas if you have slow interface traps there is going to be hysteresis and that is always going to be counter clockwise as we discussed. Now at this point it may be worthwhile to also discuss the non idealities of mobile ion charge which as I said is very rare but again if you mess up with your cleaning procedure and instead of taking quartz where you take a pyrex glass to clean your device silicon pyrex is a very good contaminant of sodium and potassium right. When we talk of mobile ion charge in oxide we are essentially talking of sodium potassium and so on and so forth which are you know metal impurities you know positively charged metal impurities. If you have this then you will always have again a hysteresis and that will be a clockwise hysteresis. It also becomes clear why that is the case first of all when we say mobile ion charge what it means is that I have this MOS capacitor there is an oxide here this is our SiO2. Now this oxide is contaminated with this mobile ion. So, these mobile ions can either move to this interface or move to this interface depending on your voltage on the gate electrode. When I have negative gate electrode voltage all these charges will move away from the silicon interface to this interface. Remember what we said last time the charges which are closest to the interface have the maximum effect on C v. In fact if the charges are out here they are absolutely no effect on C v characteristics. On other hand if I have a positive voltage then all these charges will be repelled because of the positive gate voltage and they will all move to this interface. But again this movement you see takes time it will not respond instantaneously and that time is also in the order of a few seconds. So, now just imagine what will happen because of this right I have this gate voltage and this capacitance curve. Let us say I started with negative gate voltage and negative voltage all these charges are here. So, there is no effect felt because of the charge and the C v will look very good like this. Now there is a positive gate voltage and because positive gate voltage will stay there for certain amount of time all these charges by this time will drift towards this and will accumulate here. So, when I am doing my reverse C v by this time all these charges would have come here. Now we have all this positive charge. So, whenever there is a positive charge the C v will go towards the left remember that right we have discussed all this in the last class. So, when I am doing the reverse C v the reverse C v will go like this. Again I go here for some time all these charges will go back now to this electrode. So, when I am doing the forward C v C v will again come back here because now it does not feel this positive charge all the positive charge are repelled all the way to the gate electrode and hence its effect is not at all felt. So, when you have this mobile ion charge the hysteresis as you see is clockwise this is what I meant clockwise hysteresis whereas, here the hysteresis is counter clockwise you know the hysteresis look looks like this you know there is a counter clockwise sense for this hysteresis. So, as I said you know if you have really these mobile ion charges for whatever reason you may see a clockwise hysteresis and if you have these slow traps because you are doing different dielectrics on silicon or new substrate again you may have slow traps that will give you counter clockwise hysteresis. Ideally we should not have any hysteresis you know forward and reverse should be exactly on top of each other that would be the ideal condition. You could have fixed charge fast interface traps, but slow interface traps should not be present and that is where you would essentially need to optimize your process and you know make sure that your slow interface traps are you know eliminated from the system there are two more rather three more non idealities that I wanted to discuss you know the next important thing is what is called this charge quantization effect and more precisely also referred to as channel charge quantization. The charge that you have and it is especially problematic when you are in inversion condition and let us just look at what it is right. So, this is p type silicon again let us say I have positive gate voltage Vg and this is SiO2 when I apply let us say plus 5 volt I have inverted this and you have lot of electrons here this is what we call channel charge. Now if you look at in this direction if you look at the band bending in that direction ok what you will essentially have is the following right this is your oxide you applied a positive voltage to the oxide ok and let us say this is your Fermi level here and there is a band bending which would look like this ok silicon band has bent and that is why it is p type here and it is n type here ok I have reached inversion condition now where are these electrons all these electrons are supposed to be very close to this interface you see this is oxide as you know SiO2 this is silicon and I have applied a positive gate voltage and hence that positive gate voltage corresponds to this distance that you have you know separation of these two Fermi levels is essentially the applied voltage correct. Now what happens in modern day device all the nanometric device right they have extremely thin oxide first of all remember and thin oxide has increased the electric fields right electric field is essentially dependent on voltage divided by thickness of oxide as you know we have not really followed constant electric field scaling theory so fields have increased that is one aspect oxide field has increased and oxide field is related to silicon field also right and the silicon field not only depends on the oxide thickness but also depends on the doping concentration if you have a high doping concentration the depletion width is small and you are dropping that voltage whatever silicon voltage over a very narrow distance and that excess abates this and hence the fields will be large in silicon and if fields are large remember we have discussed this electric field is gradient of band bending correct we have 1 over q d by dx correct that is this band bending that we have how fast is this band bending or the gradient of this band is directly proportional to electric field if we have higher and higher electric field these bands build more and more sharply something like this very sharp band bending indicating that fields are very large. Now something interesting happens and that is the electrons which are here they almost looks like a particle in a box right in other words you know what we mean by particle in a box is that if we have a potential well and if you put electrons in a potential well this electron cannot take any arbitrary energy right the energy of this electron will be quantized there are only certain modes that are allowed because the wave function of the electron should go to 0 at these points because there is a huge energy barrier electrons cannot really you know exist beyond this point based on the wave nature and that will quantize the energy electron can only take discrete energy it cannot take continuous energy in other words what happens here this is almost like this not quite you know it is not like a rectangular potential well but nonetheless it looks like a potential well and hence the energies of the electrons will be quantized and what it means is that the number of states available that goes down and hence the number of carriers will also go down right we remember the total number of carriers is probability of the occupancy which is governed by the Fermi Dirac statistics multiplied by the number of allowed energy states and what is happening because of this quantization earlier any energy allowed was allowed for the electrons now there are only fixed energy levels that electron can take and hence this is a phenomenon that is called inversion charge quantization or channel charge quantization which reflects as if your threshold voltage of the transistor increases effectively that is one aspect that is not the end of the story there is also remember the semiconductor capacitance in inversion we said d q psi s by d psi s and of course there was a negative sign here and we said in inversion the for a small change in potential there is a large change in electron concentration and hence when we had this equivalent combination of C ox in series with C silicon we said C silicon is infinity or very large compared to C ox ok and hence the net capacitance becomes C ox in inversion right but now that is no longer the case for two reasons C ox itself has gone up because C ox is epsilon ox by T ox because T ox went down C ox went up right that is one part of the story and C s will not be very large because the d q psi s by d psi s will not be large because there are only finite allowed energy states for a small change in the surface potential the electron charge will not change as rapidly as it would have earlier right and hence it degrades your inversion layer capacitance ok that is if you are doing a CV measurement on a transistor right this is very important in the context of MOS transistor your high frequency or low frequency both remember I said will give you a curve which looks like this where in this maximum capacitance is C ox ok. Now in presence of channel quantization charge quantization your maximum capacitance in inversion will be degraded like this it will be less than C ox ok it will be less than C ox because C ox is in series with C silicon C silicon is not infinity now it is finite capacitance and that will degrade the series combination ok and effective capacitance will go down ok. So, this is a very very important manifestation that happens in most of the devices today ok it could also happen in accumulation to some extent but in accumulation the band bending is not as much as it would happen in inversion ok and you know the effect in accumulation is not as severe as one would see in inversion may be in accumulation there is a very small effect may not be as big an effect as you would see in inversion ok. So, this is the CV curve in a transistor anyway if you are doing a CV curve on a capacitor you know capacitor will anyway show up like this but inversion capacitance will anyway be not at C ox it will be much lower governed by the depletion bit maximum depletion bit but accumulation capacitance may have some impact ok it may sort of degrade a little bit ok. So, this is one other important consideration that one has to people also model this effectively as if saying you know your effective oxide thickness has increased and hence your capacitance will degrade ok and that is why when we do the oxide thickness extraction using CV characteristic we call this oxide thickness as an electrical oxide thickness not a physical oxide thickness your electrical oxide thickness extracted from CV curve may not be exactly equal to your you know physical oxide thickness and this could be one of the reason why your electrical oxide thickness will be little different from physical oxide thickness. What I mean by electrical oxide thickness is that I take this capacitance value and I say ok look this capacitance or accumulation capacitance is epsilon ox epsilon naught a by T ox ok and I know what is my a I know what is my epsilon ox and epsilon naught I have measured my C and I will calculate my C ox ok. This kind of oxide thickness calculation is what is called electrical T ox as opposed to physical T ox invariably in today's devices electrical oxide thickness could be anywhere from about 4 to 6 angstrom more than physical oxide thickness and one reason is this and the other reason is what we call a poly silicon depletion effect ok. So, that is one other non ideality ok, but this effect does not exist if you have a metal gate capacitor or a metal gate transistor metal gate transistor this will not be there this will be there only if your gate is poly silicon ok. Now 45 nanometer and beyond mostly we are using metal gate transistor that you know this is a mute point in that case ok and the only thing that you worry about is quant channel charge quantization which may affect your equivalent electrical oxide thickness because you have ultra thin oxides ok. Poly silicon depletion is the case you know just for completeness let us also look at what it is you know you have p silicon and this oxide and this is poly silicon ok and this poly silicon is supposed to be doped with if it is a n mass kind of a transistor this will all be supposed to be n plus heavily doped n plus ok. But let us say for some reason it is not very heavily doped ok if it is not very heavily doped it is more like n minus ok. If it is like n minus and let us say I have applied positive voltage what will happen if I apply positive voltage it is as if I am applying a reverse bias to this p n junction this is a down potential and this is a positive potential and that will create a depletion region here correct like a reverse bias p n junction you have a depletion width you know as you increase reverse bias your depletion width starts increasing ok. And because of that this poly depletion under positive voltage not under negative voltage under positive voltage it adds a new capacitance in series earlier my model was only oxide capacitance in series with silicon capacitance. But now I have what is called a C poly capacitance ideally that poly was supposed to be a metal like you know electrode but it is no longer because it will contribute add a capacitance here and hence again the total capacitance will degrade because of that because as soon as you start putting capacitance is in series your total capacitance starts coming down ok. So, even under poly silicon depletion what you will see is again let us just look at the transistor structure this is accumulation inversion ideally you should have had something like this correct. But as I start applying positive voltage higher and higher positive voltage more and more depletion effect. So, very interestingly your curve starts looking like this ok it will never reach C ox it will start degrading and when I start again this measurement is done on a transistor not on a capacitor. If it is done on a capacitor anyway the minimum capacitance inversion is C minimum you know that we will not worry about it right now ok. But in a transistor structure the capacitance and inversion should have been oxide capacitance correct. But no longer the case because when I start putting positive here there is a poly depletion this depletion effect increases larger the depletion lower the capacitance and hence the series capacitance starts degrading because this capacitance is pulling everything down ok. So, this is also not desirable in fact one of the reason why we moved away from poly silicon gate to metal gate was precisely this it told you a couple of reasons one is the resistivity when I have this long finger poly finger you know that contributes R C delay and hence I wanted to sort of that resistance is also because you are not able to dope it very well ok. In addition to that you also have this kind of a poly depletion and your on current of the transistor will suffer very dramatically because of that ok. Because remember your on current of a transistor is directly proportional to your oxide capacitance in inversion for a transistor if your oxide capacitance in inversion degrades like this in poly depletion or degrades like this in channel quantization that will degrade your on current of a transistor and that is why we say your threshold voltage has now increased because your on current has decreased accordingly ok. So, this is one other very important non-ideality that you know we want to keep in mind and again as I said in a metal gate transistor you know this is not an issue right. So, the one last you know non-ideality that I want to talk about is during the measurement this is all related to the device structure ok. But during the measurement you may have what is called a series resistance effect or a parallel resistance or parallel conductance effect and sometimes we you know rather than calling it R parallel we call it G parallel. Now what is it how do you do the CV measurement let us just take high frequency CV measurement right. It is very simple as I have mentioned anyway you have a DC bias let us not worry about DC bias right now I apply some AC voltage which has some magnitude and an angle theta ok. Let us say this is my reference and I make this theta as 0 degree ok I am just representing it in a phasor form and I have my device under test which we call DUT ok and what you do is measure this current and its angle right theta it is a phasor right all you are doing is that you have this device under test you are applying some input excitation you are looking at what current is coming out ok. And then you say look my Z is essentially V divided by I theta correct and all that equipment is doing is measuring this current phasor that is coming out at the output and it knows what voltage phasor it has applied and taking the impedance as V divided by I theta ok. This is the you know impedance that you get which is essentially mod Z and angle phi let us say it has certain angle and it has certain magnitude. Now if it is an ideal capacitance no issue right you know because the angle will be 90 degree and you know whatever magnitude you have you know it is capacitance you know it is you know 1 over j omega c is its impedance right you know the magnitude and you equipment has some routines it will spit out a capacitance value for you. But as a user you need to tell the equipment whether the device under test looks like a series R C combination because of non idealities this is your MOS capacitor that you are trying to measure device that you have built or it looks like you know G parallel and see whatever MOS capacitance that you have ok that you have built meaning that it has to resolve this Z into either this form or into this form Z is same but when it is resolved into this form you get a different number for resistance and different number for capacitance. When you take the same Z and resolve into this you get a different value of resistance and different value of capacitance as I said if there was no non-ideality then you get 0 resistance here and the exact same value of capacitance. The capacitance here if it is let us say 100 pico farad if you get 0 resistance if you resolve it like this you get infinite conductance here ok it is like an open circuit this branch is open circuit if it is an ideal capacitance and you get the same 100 pico farad here right this is only if there are no other external non idealities external or internal. Now you see when you are doing this there may be a series resistance because you have not probed it properly if you are not very careful there could be this cable that you are connecting to equipment and that may also have some resistance ok and you know the metal that you have used may not be very good that may also contribute some series resistance all these are sources of series resistance. What are the sources of parallel conductance if you have ultra thin gate oxide if you have ultra thin gate oxide then the gate oxide will also leak because of the direct tunneling current that we talked about. If you have a thick gate oxide there is absolutely no conduct no leakage through that but if you have an ultra thin gate oxide as I said let us say 1 nanometer gate oxide and you have built this MOS capacitor there is always a leakage here there is a DC path correct and this essentially is showing the DC path ok. So, as a user for example if you have made sure that there are no series resistance invariably the rule of thumb is that if you are dealing with MOS capacitor which has reasonably thick insulator which means let us say 10, 20 nanometer and you have actually verified by doing an IV measurement that there are absolutely no leakage then you never use this model ok because there is no leakage path anyway there is no leakage path meaning this model is true. So, at no point in time it allows a DC leakage current here whereas this model allows your DC leakage current to be modeled correct that is what we are saying the device under test has to be modeled properly. So, thick oxide use a series model always because no leakage ok and you verify you can always verify you can do a very simple IV measurement on this MOS structure and make sure that there is no leakage current or even if there is a current let us say pico ampere or 10 pico ampere you have a tera I mean tera ohms kind of a you know resistance which has almost like an open circuit. So, you do not worry about this, but there could be some series resistance you model it like that then you get the right value. On the other hand if you are dealing with let us say less than 1 nanometer kind of SiO 2 or an high k dielectric which is very crappy you are developing high k process ideally high k process if you have a 5 to 10 nanometer it should have 0 direct leakage current, but for some reason you know you really have large leakage which you can always verify by doing a simple DC IV measurement ok then you better use this model because there is always a DC conduction path and what it means is that the current that you are measuring has a DC component also you tell the equipment that this is a more realistic model to use not this model right. If you do not follow this then you will actually get an incorrect result for your capacitance ok. In fact you know I will leave this as an exercise you can actually do it yourself that if you were to do this kind of an equivalence you see that when r is not 0 and this is not infinity your capacitances in these two cases will not be equal right for the same Z you will get two different capacitance value ok and that is when you have to decide what is the value to choose and that depends on what additional information that you have on your device ok and you need to be careful about you know that nonly an ideality ok and more specifically you know if I may sort of elaborate it very quickly if you have let us say series resistance only let us say this is my ideal CV curve HFCV curve which I should have got ok right when you are RS is equal to 0 and accordingly your R parallel is infinity ok but if RS is non-zero then if you are doing the CV measurement the what will happen is that in the low capacitance value range the effect will be not as great but when the capacitance is very large you know you will actually see a degradation of the capacitance that is if in reality now this is RS non-zero RS non-zero ok but you have told the equipment that RS non-zero meaning this is how the model should have been this is your actual capacitance that you wanted to get but by mistake you have told the equipment that use this model that either is effectively it looks like this and there is a parallel resistance and my DUT is look this you extract this value from Z if it extract this value your capacitance will be less than what it should have been but if you use the right model then you know you will get back the same capacitance in fact when you do the measurement right of course if RS is 0 the ideal then there is no issue but non-zero RS or conductance whenever you ask the equipment to do a series model and parallel model you see that the two CVs will be entirely different right and you make sure that you do the right model representation for the device and you get the right capacitance right so that is important message that I wanted to convey ok.  So, what you do first is that you look at this value accumulation capacitance and you say that this accumulation capacitance is essentially due to oxide capacitance ok and you say that you know this is epsilon naught you know the area of the capacitance that you have built and T ox electrical ok T ox electrical extracted in accumulation region right. So, you know this you know this and hence you could extract your oxide thickness ok once you have the oxide thickness right then you can go back to this minimum capacitance C minimum ok remember that C minimum is essentially determined by the doping concentration ok it has a strong influence I mean doping concentration has a strong influence on minimum capacitance right. So, first of all what you have to do is that from this measured C minimum you need to get what is the silicon C minimum because this measured C minimum is really silicon C minimum in series with oxide capacitance you see in other words whenever you are doing the measurement what you measure is really always oxide capacitance in series with silicon capacitance correct. So, you need to first get the silicon capacitance from this you know this already you know this already because this is oxide capacitance you can always get the minimum silicon capacitance ok. Now you also know the area once you get minimum silicon capacitance you remember always we deal with per unit area capacitances when we do calculations right. So, you know divide it by area and you get the per unit area capacitance right which let me call C s min prime which is essentially this divided by area and that is essentially epsilon silicon epsilon naught divided by W max where W max is a maximum depletion width correct. So, now you know this and this is known anyway and you can extract what is maximum depletion width once you know the maximum depletion width you can find out doping concentration because as you may recall the maximum depletion width essentially is given by right when you reach a band bending of 2 phi b that is when I reach inversion correct divided by q n a where n a is the doping concentration that I want to find out. However, phi b is also dependent on doping concentration because phi b is k t over q l n n a over n i, but you can solve this equation iteratively and because you know this you can extract n a value right and hence you find out what is n a value and this we are doing assuming that the doping concentration is uniform. If it is not uniform doping concentration then also there is a way to extract doping concentration as a function of depth by looking at the CV characteristics right. So, you know the textbooks will certainly discuss that you know there is little more involved, but one can easily do that, but for most of the calculation uniform doping concentration is a reasonably good estimate right especially when one is doing process development anyway one starts with the you know standard silicon wafer which has any uniform doping concentration you do not do any implantation or diffusion which will alter the doping concentration as a function of depth. So, uniform doping concentration is a reasonably good estimate as soon as you get this doping concentration I can extract what is flat band capacitance. First of all flat band capacitance in silicon because flat band capacitance in silicon as you know is epsilon silicon epsilon naught by debilant lambda l d or sometimes this is also referred to as lambda d debilant and remember I told you what debilant is in the last lecture that is essentially related to your doping concentration ok. So, once you know NA this is thermal voltage instead of band bending psi s psi s is 0 anyway we have thermal voltage here and NA is what is already evaluated and I can find out this and everything else is known anyway you multiply this with area you get flat band capacitance of silicon then you can ask the question ok if this is a flat band capacitance of silicon because it is coming in series with oxide capacitance what would be the measured flat band capacitance and that is simply CFB measured is 1 over I mean C ox in series with silicon flat band capacitance correct and that will give you what is the flat band capacitance that would be measured flat band capacitance what it means is that in the CV curve now I am locating a very unique point which is a flat band capacitance point and this point on the CV curve gives you flat band voltage and that is how you obtain a flat band voltage ok. Once you know the flat band voltage you know the flat band voltage as you know is phi ms minus qf by C ox correct phi ms presumably you know because you know phi s because you have obtained doping concentration in silicon it is easy to find out phi s now phi m presumably you know what metal you have put on the gate and you can take the metal work function as phi m phi ms is known vfb is known already from the graph and I can calculate what is qf correct qf can be easily computed using this ok. So now I have done T ox I have done Na I have done qf the next important thing is to measure D it you know which is one of the most important thing especially if you want to get a very good quality MOS capacitor so how do we get this D it there are multiple ways one can get this D it. So let us look at you know different ways of getting D it the first thing that you can do is that you can look at only high frequency CV from high frequency CV you can get D it you do not need to do low frequency CV remember our model that we have I apply a gate voltage on the gate terminal this is oxide capacitance this is my channel and that is the psi s surface potential this is the surface potential which is changing depending on the applied gate bias and your silicon capacitance plus interface trap capacitance at high frequency it is 1 over C ox plus 1 over C s because when I am doing a high frequency measurement C it does not respond although the stretch out is there the value of the capacitance will not increase this is what we have discussed in the last lecture on other hand in the low frequency you know it is C s plus C it which comes in series with C ox. So in a high frequency CV measurement just looking at this I do not have the D it information however remember the stretch out of the high frequency characteristic gives me D it information. So what I need to find out is what is that stretch out so how do you do that. So let us look at this right you know your oxide voltage can be written as V g minus psi s right and that is what it is V g V ox is equal to V g minus psi s psi s is a silicon potential now there are two elements in series total voltage is V g subtract the silicon potential you get the oxide potential also q g the charge that is put at any gate bias remember the stretch out that we are talking about at any gate bias when I go from one gate bias to the next gate bias I give enough time and hence there is a stretch out. So the gate charge that is put is now q s and q i t combined q s is a silicon charge which is essentially coming due to the impurities ionized impurities and electrons and q i t is an interface trap charge and now hence I can write V ox is C ox times q g is essentially C ox times V g minus psi s okay and this essentially is q s and q i t and what I am doing here is that you differentiate this equation with respect to psi s okay and if you do that C ox d V g over d psi s minus 1 because d psi s by d psi s is 1 minus d q psi s by d psi s and d q i t by d psi s and what is this this is C s plus C i t okay. So C ox is d V g by d phi s minus 1 equal to C s plus C i t and hence C i t is C ox times d V g over d psi s minus 1 minus C s okay. This we can rewrite it as because V g is an independent variable I am controlling V g from the external world and psi s is a dependent variable psi s is responding to the change in gate voltage and hence I am rewriting d V g by d psi s as d psi s by d V g inverse right that is all I have done here it is the same thing rewritten here okay. So C i t is C ox times this quantity and C s. Now you see I have a means to figure out d i t if I do high frequency measurement from high frequency measurement at every psi s each psi s uniquely defined C s remember that because psi s is the band bending as soon as you fix the band bending there is a particular value of C s that is it because that band bending will fix Q s in silicon and that Q s will correspond to certain C s value. So at any psi s I know C s and if I have already computed C ox because C ox is measured anyway that is known to me if we can find out what is d psi s by d V g at every value of psi s then I can put that value here and C s value here and get C i t. If I get C i t remember C i t is Q d i t and hence I get d i t value at that psi s and hence I can generate d i t versus psi s plot okay at different band bending I can get d i t in other words I am getting interface traps in the band gap very nicely. So how do you do that from the measured information so what you do is the following right I need to get this how do you get this and to get this we essentially first we note that as I mentioned for any band bending psi s I can estimate what should be C s because there is a very unique mapping between psi s and C s and that is essentially based on solution of Poisson's equation. If you solve Poisson's equation you get Q s which is semiconductor charge as plus minus plus minus indicating that when it is an accumulation it is positive charge when it is in depletion on inversion it is negative charge okay accordingly psi s is positive or negative in accumulation it is negative in inversion it is positive okay. So this expression here this corresponds to all your charge corresponding to whole charge this you know whole charge and also the depletion charge and this expression corresponds to your minority carrier charge which is electron charge I have already found out any you see and I know you know all other constants epsilon silicon everything now for different values of psi s I can generate Q s right I have given a doping concentration I have a very unique relation between Q s and psi s once you know the Q s and psi s you can very easily get capacitance because capacitance remember is D Q psi s C silicon capacitance by D psi s okay so all you need to do is that you generate psi s versus Q s which is here and you differentiate this you know you can write a very simple program to do that it could be even a excel program to do that you put in several psi s value generate Q s you do D Q s by D psi s and you have a capacitance except if you want to get high frequency capacitance you ignore this term because this term is due to minority carriers we say that under high frequency minority carriers do not respond and hence I ignore this term I only retain this term and I generate C h f versus psi s okay in other words for different values of psi s psi s going from 0 which is flat band going towards 2 phi b which is going towards inversion I generate all the values of capacitances so this is theoretical right from theory I have been able to generate this but this value of capacitance uniquely corresponds you know this is my measured C h f versus V g I have measured it but this psi s uniquely corresponds to the same band bending because only when you have that band bending you will get this capacitance because it is C ox in series with C silicon and hence for every capacitance value you have a unique value of psi s and this unique value of psi s maps to a unique value of V g this is your measured curve okay so for every value of psi s again you know you can either do it graphically but you do not want to do it manually again a very simple program can be written to do that every value of psi s will have a unique value of V g and in other words what you have generated is really psi s versus V g this psi s versus V g would be theoretical I do not really need to worry about theoretical psi s versus V g and I can also generate psi s versus V g theoretically okay forget about this curve all I am trying to tell you is that by comparing this with the measured C v I have this psi s versus V g curve and because I have psi s versus V g curve I can get d psi s by d V g very easily at any value of psi s I put a value of psi s I find out what is d psi s by d V g and I also find out what is C s because it is very uniquely defined for that value of psi s as soon as I know both these quantities I know C s I put that value here I know d psi s by d V g I put that value here I have any way measured oxide thickness oxide capacitance I know what is C i t once you know C i t you know d i t in other words what you have generated for every value of psi s you have generated d i t versus psi s plot okay and this d i t versus psi s plot gives you the interface dead density in the band gap of silicon okay and this is what is called the sometimes this was first proposed by a person called term and in fact it is also called termans differentiation technique use this differentiation process of psi s versus V g d psi s by versus d V g is used in estimating interface trap density so this is one way of doing so just by having high frequency C v capacitance you can do this measurement especially when your trap density is very large this measurement is fairly accurate but if you are trap density is very very low like 10 power 10 then this kind of a differentiation process leads to some errors okay then this process will not be very accurate but for most of the process development when you are doing a new high k dielectric you know your trap density is reasonably large and you can very easily just do a C v measurement just high frequency C v and you can obtain the interface trap density as well using the C v measurement okay there are two other ways of doing C interface trap measurement which we will discuss in the next lecture those two measurements will work only if you have a ideal I mean not ideal a good low frequency measurement done along with the high frequency measurement okay and that we will discuss in the next lecture so just to sort of wrap up you know there are multiple non idealities in a C v system which we discussed ranging from fixed charge interface charge slow traps right and we need to deal with these non idealities and also there are ways to extract the various parameters from the C v measurements as we discussed today. So you know now if you have both high frequency and low frequency measurement you know then what one could do is that you know as I mentioned here I will go to this equation remember this then you know from this equation I should be able to get the interface trap density here okay. So you know how does one do that right and assuming that you have just the low frequency capacitance okay do not worry about this equation you know we will postpone the discussion on this equation for a minute okay okay maybe I was looking at the wrong slide yeah maybe let us just focus on this right. I have measured low frequency C v measurement remember that in the depletion region the low frequency capacitance responded to interface states right if your high frequency was lower your low frequency was higher it would be much higher because the slow varying signal traps can easily respond to that and that is why I have this model C s plus C i t and now C i t can be written as 1 over C l f minus 1 over C ox minus C s okay you have measured this low frequency capacitance and all you need to do now is that at different psi s you need to find out C s and also need to find out a relationship between psi s and v g earlier we found that psi s versus v g relationship through the differentiation technique but here we will not do that differentiation we will actually use an integration technique of a low frequency curve as opposed to differentiation technique of psi s v g derived out of a high frequency curve now we are not looking at high frequency at all we are only looking at a low frequency curve so what do we do right and this is a generic expression that we have C ox times d v g by d psi s minus 1 is C s plus C i t okay which is what we derived earlier when we were discussing the c v measurement now you know one can sort of rewrite this equation a little bit you know just some algebraic manipulation right you know you sort of you know take this d phi s on this side and you know you have the C ox d v g as d phi s times this and in other words d psi s is equal to C ox divided by this times d v g okay now what I can do now is that this part right first of all if I can express this part as a major low frequency capacitance and then I can integrate this whole thing phi s psi s would be psi s 0 plus integration from v g naught to v g of C ox divided by C ox plus C s plus C i t d v g right I mean I am just sort of integrating it for example at v g naught is equal to v f b right your flat band voltage is 0 right so that is an initial condition for example okay and you know from that you can actually go to different gate voltages and you do this integration okay and you can get different values of psi s as a function of v g what I am going to do now is that I am going to rewrite this right I based on you know this capacitance equation 1 over C l f is 1 over C ox plus 1 over C s plus C i t okay and I am multiplying this equation on both side by C ox again doing some algebraic manipulation here okay and I am simplifying that equation and what I get is C ox divided by C ox plus C s plus C i t is same as 1 1 minus C l f by C ox and this is something interesting right C l f is what is measured externally C ox can always be obtained because it is you know looking at the accumulation value of capacitance you can find out what is C ox right in other words this term inside the integral can be replaced by 1 minus C l f measured divided by C ox. So now all you need to do is that put different values of psi s at these different values of psi s you precisely know you know what is the value of v g okay and accordingly you also know what is the value of C i t so at different values of v g you know what is the value of l f capacitance that you have measured and hence you would be able to find out d i t as a function of psi s again you are mapping d i t to psi s two major differences one first difference is that the way I computed d i t is from low frequency capacitance okay and this is what I used to compute d i t that is one major difference compared to previous technique in previous technique only high frequency was used. The second difference also is that to compute psi s versus v g relationship earlier I did it using high frequency curve but now I am doing it with a low frequency curve so both these things are done using a low frequency capacitance voltage characteristic right that is a major departure here okay and hence you know again this was first postulated by Borgland and this is using an integration process to compute psi s versus v g relationship and hence the name d i t computation using the Borgland's integration okay to get that psi s versus v g relationship okay. Then last technique if you have both high and low frequency at your disposal okay then what you can do is that you can use what is called h f l f technique right meaning that I have measured high frequency capacitance which looks like this I have measured a low frequency capacitance which looks like this in this region which is where your band bending is going from flat band to inversion that is the region of interest for us okay from 0 to 2 phi b psi s is going from 0 to 2 phi b in this region your low frequency capacitance is higher compared to high frequency capacitance you can look at this difference and you can get c i t as you know something like this you make use of a low frequency capacitance and the c s that I had in the previous equation that can be computed using high frequency capacitance 1 over c h f minus 1 over c ox inverse. So, the c i t or in other words d i t is now computed based on two actually measured values okay low frequency value and high frequency value right and this is how I get d i t as a function of v g at different values of v g I get d i t, but you really need to map it to different values of surface potential and in order to get that you still need psi s versus v g. So, that you can if you get psi s versus v g then because you know this you can map this d i t versus psi s and for that you know you can essentially use the same burglant's integration that we talked about earlier right you can use that and you would be able to get psi s versus v g relationship from the low frequency curve you do it from the low frequency rather than high frequency because the integration process will not give rise to too much of noise whenever you are trying to do differentiation from a measured curve you can end up with large noise in the differentiation process okay and this is what is called HFLF technique right. So, one can extract this interface trap density either solely by high frequency curve or solely by low frequency curve or a combined high and low frequency curve right. So, depending on what you have at your disposal you can do one or all of these okay and this also happens to be one very important you know parameter extraction process. So, then let us you know stop here that sort of completes all the discussion on MOS capacitance characterization and in the next lecture we will you know discuss about current voltage characterization on a transistor okay.