Verilog error : A reference to a wire or reg is not allowed in a constant expression
<p>I'm new to Verilog and I would really appreciate it if someone could help me out with this error:</p>

<pre><code>output  reg [0:image_width][image_height:0]    result
....
integer i, j, imageX, imageY, x, y, kernelX, kernelY;
....

@(negedge ACLK)
for(x = 0; x &lt; image_width; x++) begin 
    for(y = 0; y &lt; image_height; y++)
    begin
    //multiply every value of the filter with corresponding image pixel
        for(kernelX = 0; kernelX &lt; kernel_width; kernelX++) begin            
            for(kernelY = 0; kernelY &lt; kernel_height; kernelY++)
                begin           
                    imageX = (x - kernel_width / 2 + kernelX + image_width) % image_width;
                    imageY = (y - kernel_height / 2 + kernelY + image_height) % image_height;

                    // ignore input samples which are out of bound
                    if( imageY &gt;= 0 &amp;&amp; imageY &lt; image_height &amp;&amp; imageX &gt;= 0 &amp;&amp; imageX &lt; image_width )
                        //ERROR HERE!!!
                        result[x][y] += image[imageX][imageY] * kernel[kernelX][kernelY];   
                    end
                end
        end
    end
end
</code></pre>

<p>The error I get is:</p>

<blockquote>
  <p>error: A reference to a wire or reg ('x') is not allowed in a constant expression. <br>
   error: Array index expressions must be constant here. <br>
  error: A reference to a wire or reg ('imageX') is not allowed in a constant expression.<br>
  error: Array index expressions must be constant here.<br>
  error: A reference to a wire or reg ('kernelX') is not allowed in a constant expression.<br>
  error: Array index expressions must be constant here.</p>
</blockquote>

<p>Could somebody tell me what I'm doing wrong? Thank you!</p>