Verilog: Illegal redeclaration
<p>I am attempting to generate a programming file useing ISE 14.7 for some of the benchmarks provided on Trust-Hub.org. I am working with AES-T100 which contains a series verilog files. I have never worked with verilog and haven't touched VHDL in years.</p>

<p>In theory the verilog code provided by trust-hub should work however trying it gives the compile error</p>

<pre><code>ERROR:HDLCompilers:27 - "../../../../../../AES-T100/src/TjIn/TSC.v" line 28 Illegal redeclaration of 'load'
</code></pre>

<p>Now, this error is fairly self explanatory however looking at a beginners verilog tutorial <a href="http://www.asic-world.com/verilog/syntax2.html" rel="nofollow noreferrer">here</a> I can see the exact same repetition of variables names.</p>

<p>Does this verilog code below look correct or is there some error in the trust-hub code?</p>

<pre><code>`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:20:01 03/06/2013 
// Design Name: 
// Module Name:    TSC 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module TSC(
    input rst,
    input clk,
    input [127:0] key,
    output [63:0] load
    );

    reg [63:0] load;
    wire [19: 0] counter;

    lfsr_counter lfsr (rst, clk, counter);
    always @ (posedge clk)
        begin
            load[0] &lt;= key[0] ^ counter[0]; 
            load[1] &lt;= key[0] ^ counter[0]; 
            load[2] &lt;= key[0] ^ counter[0]; 
            load[3] &lt;= key[0] ^ counter[0]; 
            load[4] &lt;= key[0] ^ counter[0]; 
            load[5] &lt;= key[0] ^ counter[0]; 
            load[6] &lt;= key[0] ^ counter[0]; 
            load[7] &lt;= key[0] ^ counter[0]; 

            load[8] &lt;= key[1] ^ counter[1]; 
            load[9] &lt;= key[1] ^ counter[1]; 
            load[10] &lt;= key[1] ^ counter[1];    
            load[11] &lt;= key[1] ^ counter[1];    
            load[12] &lt;= key[1] ^ counter[1];    
            load[13] &lt;= key[1] ^ counter[1];    
            load[14] &lt;= key[1] ^ counter[1];    
            load[15] &lt;= key[1] ^ counter[1];    

            load[16] &lt;= key[2] ^ counter[2];    
            load[17] &lt;= key[2] ^ counter[2];    
            load[18] &lt;= key[2] ^ counter[2];    
            load[19] &lt;= key[2] ^ counter[2];    
            load[20] &lt;= key[2] ^ counter[2];    
            load[21] &lt;= key[2] ^ counter[2];    
            load[22] &lt;= key[2] ^ counter[2];    
            load[23] &lt;= key[2] ^ counter[2];    

            load[24] &lt;= key[3] ^ counter[3];    
            load[25] &lt;= key[3] ^ counter[3];    
            load[26] &lt;= key[3] ^ counter[3];    
            load[27] &lt;= key[3] ^ counter[3];    
            load[28] &lt;= key[3] ^ counter[3];    
            load[29] &lt;= key[3] ^ counter[3];    
            load[30] &lt;= key[3] ^ counter[3];                
            load[31] &lt;= key[3] ^ counter[3];                

            load[32] &lt;= key[4] ^ counter[4];    
            load[33] &lt;= key[4] ^ counter[4];    
            load[34] &lt;= key[4] ^ counter[4];    
            load[35] &lt;= key[4] ^ counter[4];    
            load[36] &lt;= key[4] ^ counter[4];    
            load[37] &lt;= key[4] ^ counter[4];    
            load[38] &lt;= key[4] ^ counter[4];    
            load[39] &lt;= key[4] ^ counter[4];    

            load[40] &lt;= key[5] ^ counter[5];    
            load[41] &lt;= key[5] ^ counter[5];    
            load[42] &lt;= key[5] ^ counter[5];    
            load[43] &lt;= key[5] ^ counter[5];    
            load[44] &lt;= key[5] ^ counter[5];    
            load[45] &lt;= key[5] ^ counter[5];    
            load[46] &lt;= key[5] ^ counter[5];                
            load[47] &lt;= key[5] ^ counter[5];                

            load[48] &lt;= key[6] ^ counter[6];    
            load[49] &lt;= key[6] ^ counter[6];                
            load[50] &lt;= key[6] ^ counter[6];    
            load[51] &lt;= key[6] ^ counter[6];    
            load[52] &lt;= key[6] ^ counter[6];    
            load[53] &lt;= key[6] ^ counter[6];    
            load[54] &lt;= key[6] ^ counter[6];    
            load[55] &lt;= key[6] ^ counter[6];

            load[56] &lt;= key[7] ^ counter[7];    
            load[57] &lt;= key[7] ^ counter[7];    
            load[58] &lt;= key[7] ^ counter[7];    
            load[59] &lt;= key[7] ^ counter[7];    
            load[60] &lt;= key[7] ^ counter[7];    
            load[61] &lt;= key[7] ^ counter[7];    
            load[62] &lt;= key[7] ^ counter[7];    
            load[63] &lt;= key[7] ^ counter[7];                
        end

endmodule
</code></pre>

<p><strong>Edit</strong>
I found this discussion <a href="https://stackoverflow.com/questions/37200244/why-does-the-following-redeclaration-error-happen-in-verilog">here</a> that talks about the ansi style header.
I changed the top of the module code to this:</p>

<pre><code>module TSC(
    input rst,
    input clk,
    input [127:0] key,
     output reg [63:0] load
    );

    //reg [63:0] load;
    wire [19: 0] counter;
</code></pre>

<p>And it worked. Is the style above that didn't work from older versions of verilog or something? Why would they publish 'tested' code that so clearly doesn't work?</p>