full adder 3-bit std_logic_vector
<p>i am learning vhdl and i get an error when i simulate a 3-bit full adder 
that implements with std_logic_vector (because of ability to use '+' operation)
just an example that our teacher gave us,
forgive me if it is a simple question...
here is code : </p>

<pre><code>Library ieee;
use ieee.std_logic_1164.all;
entity adder_3_bit is
    port(
    a,b : in std_logic_vector(2 downto 0);
    cin : in std_logic;
    cout : out std_logic;
    sum : out std_logic_vector(2 downto 0)
    );
end adder_3_bit;
architecture behav of adder_3_bit is 
    signal temp : std_logic_vector(3 downto 0);
    begin
    temp &lt;= ('0' &amp; a) + ('0' &amp; b) + ("000" &amp; cin);
    sum &lt;= temp(2 downto 0);
    cout &lt;= temp(3);
    end behav;
</code></pre>

<p>i get an error when temp is trying to add 0's at then end of 2 bit arrays,
which it says : </p>

<pre><code>Line 15: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"ERROR:HDLCompiler:854
</code></pre>

<p>every body here is the working code:</p>

<pre><code>Library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder_3_bit is
    port (
    a,b : in std_logic_vector(2 downto 0);
    cin : in std_logic;
    cout : out std_logic;
    sum : out std_logic_vector(2 downto 0)
    );
end adder_3_bit;
architecture behav of adder_3_bit is 
    signal temp : std_logic_vector(3 downto 0);
    begin
     temp &lt;= std_logic_vector(('0' &amp; unsigned (a)) + ('0' &amp; unsigned(b)) + ("000" &amp; cin));
    sum &lt;= temp(2 downto 0);
    cout &lt;= temp(3);
end behav;
</code></pre>