How to bind an interface with system verilog module?
<p>I have an system verilog interface </p>

<pre><code>interface add_sub_if(
input bit clk,
input [7:0] a,
input [7:0] b,
input       doAdd,
input [8:0] result
);

  clocking dut_cb @(posedge clk);
    output    a;
    output    b;
    output    doAdd;
    input     result;
  endclocking // cb

  modport dut(clocking dut_cb);

endinterface: add_sub_if
</code></pre>

<p>And i have a SV module which uses this interface</p>

<pre><code>module dummy(add_sub_if.dut _if);
  ....
endmodule: dummy
</code></pre>

<p>What is the ideal way to hook up this in my TB?</p>

<p>If i instantiate the interface, i need to create wires.</p>

<p>If i use bind then also i need to do a port mapping of the individual signals, that beats the convenience of having an interface.</p>

<p>Another add on question is, how to assign one such interface to another interface?</p>

<p>Thanks in advance,</p>

<p>Rajdeep</p>