Condition: Logical state of multi-bit packed array
<p>The configuration below</p>

<pre><code>reg [3:0] myreg;

always@(...) begin
...
    if(myreg) begin &lt;events&gt; end ...
end
</code></pre>

<p>How reference to "myreg" in condition without referring specific bit and logical operation between bits in packed array will be handled?</p>

<p><strong>Edit: Would you please provide where this behavior you explained is documented?</strong> As this semantic structure is allowed, I guess there should be some documentation about it... Thank you!</p>

<p><strong>Edit 1: Thanks for all your answers so far. Let's refocus on the following two points:</strong></p>

<ul>
<li>Why you believe logical value of (myreg) is reduction OR (not AND for example) - is there standard guideline? Let's turn off common sense and our feeling of "right" and "wrong" - these are not the matters we can base our conclusions on in mathematics/cybernetics.</li>
<li>is it true that "it may behave differently with another simulator" - or in the real life?
This strikes me because (a) I can not find document which states that it MUST be a reduction OR, and (b) that Quartus (which I use) does not give any warning or error for the syntax above.</li>
</ul>