"component instance "uut" is not bound" when simulating test bench with GHDL simulator
<p>I am having a problem with using GHDL (<a href="http://ghdl.readthedocs.io/en/latest/" rel="nofollow">http://ghdl.readthedocs.io/en/latest/</a>) to simulate my VHDL design. So, when I use the command <code>ghdl -e Averager_tb</code> to compile the test bench with GHDL I get the warning:</p>

<pre><code>Averager_tb.VHD:33:3:warning: component instance "uut" is not bound
Averager_tb.VHD:11:14:warning: (in default configuration of averager_tb(behaviour))
</code></pre>

<p>To compile the test bench for simulation I use the following commands:</p>

<pre><code>ghdl -a Averager_tb.VHD # the test bench file is Averager_tb.VHD
ghdl -e Averager_tb # the entity for the test bench is Averager_tb
</code></pre>

<p>And the output of my design stays unchanged throughout the testbench, I also find that the print statements inside the Design are not executed. </p>

<p>To execute the compiled test bench simulation I use the command:</p>

<pre><code>ghdl -r Averager_tb
</code></pre>

<p>However when I simulate the same testbench on <a href="http://www.edaplayground.com" rel="nofollow">http://www.edaplayground.com</a> using the Aldec Riviera Pro 2015.06 simulator I find that the print statements within the design are executed and the output changes as I would expect. </p>

<p>Why is this and how might I fix it?</p>

<p>Here is the entity declaration in my design</p>

<pre><code>-- Entity Declaration in Design
entity Averager is
port (
clk : in std_logic;
ClockEnable : in std_logic;
Averager_In : in std_logic_vector(7 downto 0);
Averager_Out : out std_logic_vector(7 downto 0)
);
end Averager;
</code></pre>

<p>Below is the test bench:</p>

<pre><code>-- TEST BENCH

architecture behaviour of Averager_tb is
  signal X : real := 0.0; -- a real math variable initialized to 0
  signal sine : real := 0.0; -- a real math variable initialized to 0

  component Averager
  port(
    clk : in std_logic;
    ClockEnable : in std_logic;
    Averager_In : in std_logic_vector(7 downto 0);
    Averager_Out : out std_logic_vector(7 downto 0)
    );
  end component;

  signal clk : std_logic := '0';
  signal ADC_clk : std_logic := '0';
  signal Input : std_logic_vector(7 downto 0);
  signal FPGAOutput : std_logic_vector(7 downto 0);
  signal int_sine : integer;
  constant clk_period : time := 5 ns;

begin
    -- Instantiate the Unit Under Test (UUT)
  UUT : Averager
  port map (
    clk =&gt; clk,
    ClockEnable =&gt; ADC_clk,
    Averager_In =&gt; Input,
    Averager_Out =&gt; FPGAOutput
  );

  ...
</code></pre>