Avoid using inout in VHDL
<p>I want to avoid using inout at the following code.</p>

<p>Is there any way I can do it? For example a helping signal?</p>

<pre><code>entity LA_Unit is
    Port ( Cin : in    STD_LOGIC;
           P   : in    STD_LOGIC_VECTOR (3 downto 0);
           G   : in    STD_LOGIC_VECTOR (3 downto 0);
           C3  : out   STD_LOGIC;
           C   : inout STD_LOGIC_VECTOR (2 downto 0));
end LA_Unit;

architecture Behavioral of LA_Unit is
begin
  C(0) &lt;= (P(0) and Cin) xor G(0);
  C(1) &lt;= (P(1) and C(0)) xor G(1);
  C(2) &lt;= (P(2) and C(1)) xor G(2);
  C3   &lt;= (P(3) and C(2)) xor G(3);
end Behavioral;
</code></pre>