Counter is not incremented when controlling signal changes
<p>I implemented a simple counter 0 to 255 design in VHDL. It works as expected on the FPGA board, but when I simulate it in Modelsim, the counter does not add when I force <code>key(0)</code> to change. Any thoughts? </p>

<pre><code>library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY PROC_TEST     IS
  PORT(
    CLOCK_50: IN STD_LOGIC;
    KEY: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    LEDR: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
    );
END PROC_TEST;

ARCHITECTURE MAIN OF PROC_TEST IS
  SIGNAL COUNTER: INTEGER RANGE 0 TO 255;
BEGIN

  LEDR(7 DOWNTO 0)&lt;= STD_LOGIC_VECTOR (TO_UNSIGNED(COUNTER,8));

  PROCESS (CLOCK_50)
  BEGIN
    IF (KEY(0)'EVENT AND KEY(0) = '0')THEN
      COUNTER&lt;=COUNTER + 1;
    END IF;
  END PROCESS;
END MAIN;
</code></pre>