Why on a wire with delay, sharp voltage change at one end will not be observed at the other end
<p>When I was writing some Verilog code, I found something really confusing. </p>

<p>I defined a wire whose delay is 20ns. The module is as follows:</p>

<pre><code>`timescale 1ns/1ns
module wireDelay(
    input a_i,
    output b_o
);

wire #20 w_tmp;

assign w_tmp = a_i;
assign b_o = w_tmp;

endmodule
</code></pre>

<p>And during the simulation, I found that if the electrical level of input doesn't stay for some time longer than wire delay, it wouldn't be observed on the output side.</p>

<p><a href="https://i.stack.imgur.com/CpqFl.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CpqFl.png" alt=""></a></p>

<p>The wave above is input while the other is output.</p>

<p>I am wonder why it happens and whether it's true in the real world?</p>