Questions regarding operations on NaN
<p>My SSE-FPU generates the following NaNs:</p>

<ul>
<li>When I do a any basic dual operation like ADDSD, SUBSD, MULSD or DIVSD and one of both operands is a NaN, the result has the sign of the NaN-operand and the lower 51 bits of the mantissa of the result is loaded with the lower 51 bits of the mantissa of the NaN-operand.</li>
<li>When both operations are NaN, the result is loaded with the sign of the destination-register and the lower 51 bits of the result-mantissa is loaded with the lower 51 bits of the destination-register before the operation. So the associative law doesn't count when doing multiplications on two NaN-operands!</li>
<li>When I do a SQRTSD on a NaN-value, the result has the sign of the NaN-operand and the lower 51 bits of the result is loaded with the lower 51 bits of the operand.</li>
<li>When I do a multiplication of infinity with zero or infinity, I always get -NaN as a result (binary representation 0xFFF8000000000000u).</li>
<li>If any operand is a signalling NaN, the result becomes a quiet NaN if the exception isn't masked.</li>
</ul>

<p>Is this behaviour determined anywhere in the IEEE-754-standard? </p>