Verilog always inside a generate block is throwing error
<p>I am trying to execute addition through using ripple carry adder using for loop and I wanted the operation to be performed only at posedge of clock. For doing so, I have used a generate block and used for loop inside the generate block. If I use without always statement it would work fine, but when I add the always block it would result in error when simulating. 
Below is the code:</p>

<pre><code>genvar i;
generate
    always @(posedge clk)
    for(i=0;i&lt;=31;i=i+1) begin : generate_block         
        fulladd f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));

    end
    end

endgenerate
</code></pre>

<p>Here fulladd is a different module.</p>

<p>Below is the error that I am getting when simulating:</p>

<pre><code>   Error-[IBLHS-CONST] Illegal behavioral left hand side
   add32.v, 36
   Constant Expression cannot be used on the left hand side of this assignment
   The offending expression is : i
   Source info: i = 0;


   Error-[IBLHS-CONST] Illegal behavioral left hand side
   add32.v, 36
   Constant Expression cannot be used on the left hand side of this assignment
   The offending expression is : i
   Source info: i = (i + 1);


   Error-[SE] Syntax error
   Following verilog source has syntax error :
   "add32.v", 37: token is '('
        fulladd 
   f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));
</code></pre>

<p>add32.v is the design module name. I have used synopsis vcs. I am new to verilog programming, please explain the underlying concept which I have mistaken. Thanks in advance</p>