Bitwise Extract Vector in ASIMD instruction (ARM platform)
<p>I want to implement bitwise extract vector instruction in ASIMD assembly instruction. Let me put it this way that in ARMv7 NEON instructions, suppose I have some values inside <code>q15</code> and <code>q11</code>, and I have:</p>

<pre><code>"vext.8 d30, d30, d22, #4 \n\t"
"vext.8 d31, d31, d23, #4 \n\t"
</code></pre>

<p>As you can see here, I'm extracting 4-byte elements from the bottom end of <code>d22</code> and 4-byte elements from the top end of <code>d30</code>. Then I combine them into one 64-bit register <code>d30</code> (first instruction above). The same operation is done on the second half of the <code>q</code> vectors (<code>d31</code> and <code>d23</code>). Now, I want to implement the exact same logic in ARMv8 ASIMD instructions. The replacement instruction for <code>vext</code> in ASIMD is <code>ext</code> and it's defined as:</p>

<blockquote>
  <p>EXT Vd.(T), Vn.(T), Vm.(T), #index</p>
  
  <p>Bitwise extract (vector). Where (T) is either 8B or 16B. The index is an immediate value in the range 0 to nelem((T))-1.</p>
</blockquote>

<p>My question is, How can I use this instruction to construct the same logic in my two SIMD vector registers <code>v15</code> and <code>v11</code> for example. </p>