Verilog: Assigning a register to a register
<p>In the below Verilog assignment register <code>rotationDoneR</code> is assigned to the Signal and then the other register <code>rotationDoneRR</code> is assigned to the same register. Doesn't that mean that both registers hold the same value and the condition is never true?</p>

<pre><code>input wire RotationDone; // from the module definition

reg rotationDoneR;
reg rotationDoneRR;

rotationDoneR &lt;= RotationDone; 
rotationDoneRR &lt;= rotationDoneR;  

if ( rotationDoneR &amp;&amp; (! rotationDoneRR ) ) begin 
    InterruptToCPU &lt;= 1; 
end 
</code></pre>

<p>Thanks for any clarification!</p>