Skylake L2 cache enhanced by reducing associativity?
<p>In <a href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf#page=35" rel="nofollow noreferrer">Intel's optimization guide</a>, section 2.1.3, they list a number of enhancements to the caches and memory subsystem in Skylake (emphasis mine):</p>

<blockquote>
  <p>The cache hierarchy of the Skylake microarchitecture has the following
  enhancements:</p>
  
  <ul>
  <li>Higher Cache bandwidth compared to previous generations.</li>
  <li>Simultaneous handling of more loads and  stores enabled by enlarged buffers. </li>
  <li>Processor can do two page walks in parallel compared  to one in Haswell microarchitecture and earlier  generations. </li>
  <li>Page split load penalty down from 100 cycles in previous generation to 5 cycles. </li>
  <li>L3 write bandwidth increased from 4 cycles pe r line in previous generation to 2 per line. </li>
  <li>Support for the CLFLUSHOPT instruction to flush ca che lines and manage memory ordering of flushed  data using SFENCE. </li>
  <li>Reduced performance penalty for a software prefetch that specifies a NULL pointer. </li>
  <li><strong>L2 associativity changed from 8 ways to 4 ways.</strong></li>
  </ul>
</blockquote>

<p>The final one caught my eye. In what way is a reduction in the number of ways an enhancement? By itself, it seems that fewer ways is strictly worse than more ways. Of course, I get that there might be valid engineering reasons why a reduction in the number of ways could be a tradeoff that enables other enhancements, but here it is positioned, by itself, as an enhancement. </p>

<p>What am I missing?</p>