how can I control the signal in two always block
<p>I am trying to write initial LCD module. I didn't finish letter writing part. When I'm creating that part, there is small problem in my code. I can't write data in two always blocks. When I do that , Xilinx says <strong>ERROR: counter signal is connected to multiple drivers.</strong>, comment language is Turkish but it's not important. </p>

<p>I just want to know how I can reset and increment <code>counter</code> reg to increase in <code>always *(posedge CLK or posedge RESET)</code> block and reset the <code>counter</code> reg in <code>always *@</code> block?</p>

<pre><code>/*


 Wait 45ms. 
 Write 0x38, wait 4.1ms. 
 Write 0x38, wait 100us. 
 Write 0x38, wait 40us. 
 Write 0x38, wait 40us. 
 Write 0x0F, wait 40us. (Display ON, Cursor ON, Blinking ON) 
 Write 0x01, wait 1.64ms. (Clear display) 
 Write 0x06, wait 40us. (Entry Mode Set, Auto-Increment, No Shift) 
 Write LETTER_PRINTED 
*/
//////////////////////////////////////////////////////////////////////////////////
module LCD_Baslangic(
    input CLK,
    input RESET,
     input wire [7:0] LETTER_PRINTED, //letter to be printed
    output wire LCD_E,
     //output wire LCD_RW,
    output wire LCD_RS,
    output wire [7:0] LCD_DATA
    );
        //Başlangıç değerleri
    reg [7:0] sampled_LCD_DATA = 8'd0;
    reg sampled_LCD_E = 0;
    reg sampled_LCD_RS = 0;
    //reg sampled_LCD_RW = 0;



    reg [19:0] counter = 20'd0 ; // 83.3 ns göre hesaplandı. 
    //En yüksek bekleme süresi 45ms olduğu için counter 10000011111111111111 
    //dönmesi demek,540671 kez dönmesi demektir.

    reg [19:0] precomp_delay = 20'd0;
    reg flag_45ms = 0, flag_function_is_set = 0;


    localparam t_45ms = 540000; // beslenme delayı
    localparam t_4_1ms = 54000;  // 
   localparam t_1_64ms = 19680; // Clear Display komutun işleme cycle
   localparam t_100us = 1200;
    localparam t_40us = 480;
    localparam t_40_80ns = 1;
    localparam t_240ns = 3;

    localparam [3:0] 
                        starting_state                          = 4'd0, // 45ms Beklenen kısım
                        reset_state                                 = 4'd1,
                        write_state                                 = 4'd2, // İlk Write State
                        data_delay_state                            = 4'd3, // 80ns bir bekleme yapıyoruz. Yazılan data garanti olsun diye 
                        enable_high_state                       = 4'd4, // Enable ın 1 oldugu durum bu state 240ns korunur.
                        oneclock_delay_state                    = 4'd5, // 240ns den sonra 10 ns bir bekleme gerçekleşir.Fakat FPGA kartımız en 83.3 ns clock üretebildiği için en az bir clock sağlıyabilirz.
                        precompiler_delay_state                 = 4'd6, // yapılan işleme göre LCD gerçekleştirme süresidir
                        check_isthereanywritingdata_state   = 4'd7, // yapilacak başka bir işlem varsa write state'e geri döner, yoksa bir state atlar
                        infinity_state                              = 4'd8; // Programın sona erdiği yer.

    reg [4:0] substate = 5'd0;
    reg [3:0] state_reg = 4'd0;
    reg [3:0] state_next = 4'd0;

    always @(posedge CLK or posedge RESET)
        begin
            if (RESET)
                begin
                    state_reg &lt;= reset_state;
                    counter      &lt;= 20'd0;
                end
            else
                begin
                    state_reg   &lt;= state_next;
                    counter       &lt;= counter + 20'd1;
                end 
        end

    always @*
        begin
            state_next = state_reg;
            case (state_reg)
                starting_state:
                        begin
                            if (counter == t_45ms)
                                begin
                                        counter = 20'd0;
                                        state_next = write_state;
                                        flag_45ms = 1;
                                end
                        end
                    reset_state:
                        begin
                            if (RESET == 0)
                                begin
                                    if (flag_45ms == 1) // Demekki ilk durum gerçekleşmiş
                                        begin
                                            if (flag_function_is_set == 0) // Fonksiyonlarda gönderilmemiş
                                                state_next = write_state;
                                            else
                                                state_next = infinity_state;
                                        end
                                    else
                                        state_next = starting_state;
                                end
                            else
                                state_next = reset_state;
                        end
                    write_state:
                        begin
                                case (substate)
                                        5'd0:
                                            begin
                                                sampled_LCD_DATA = 8'h38;
                                                precomp_delay = t_4_1ms;
                                                sampled_LCD_RS = 0;
                                            end
                                        5'd1:
                                            begin
                                                sampled_LCD_DATA = 8'h38;
                                                precomp_delay =  t_100us;
                                                sampled_LCD_RS = 0;
                                            end
                                        5'd2:
                                            begin
                                                sampled_LCD_DATA = 8'h38;
                                                precomp_delay = t_40us;
                                                sampled_LCD_RS = 0;
                                            end 
                                        5'd3:
                                            begin
                                                sampled_LCD_DATA = 8'h38;
                                                precomp_delay = t_40us;
                                                sampled_LCD_RS = 0;
                                            end
                                        5'd4:
                                            begin
                                                sampled_LCD_DATA = 8'h0F; // Display ON, Cursor On, Blinking On
                                                precomp_delay = t_40us;
                                                sampled_LCD_RS = 0;
                                            end
                                        5'd5:
                                            begin
                                                sampled_LCD_DATA = 8'h01; // Clear Display
                                                precomp_delay = t_1_64ms;
                                                sampled_LCD_RS = 0;
                                            end
                                        5'd6:
                                            begin
                                                sampled_LCD_DATA = 8'h06; // Entry Set, Auto-Increment,No Shift
                                                precomp_delay = t_40us;
                                                sampled_LCD_RS = 0;
                                            end
                                        default:
                                            sampled_LCD_DATA = sampled_LCD_DATA;
                                    endcase
                                state_next = data_delay_state;
                        end
                    data_delay_state: // Data Oluşum Delayı
                        begin
                            if (counter &gt;= t_40_80ns)
                                begin
                                    state_next = enable_high_state;
                                    counter = 20'd0;
                                    sampled_LCD_E = 1; // Enable High olur
                                end

                        end
                    enable_high_state: // 240ns Enable High durumunu korur.
                        begin
                            if (counter == t_240ns)
                                begin
                                    state_next = oneclock_delay_state;
                                    counter = 20'd0;
                                    sampled_LCD_E = 0; // 10 ns bekleme yapalım
                                end
                        end
                    oneclock_delay_state:
                        begin
                            if (counter &gt;= t_40_80ns)
                                    begin
                                        state_next = precompiler_delay_state; // bir clock 83.3 lük bekleme yapar, 
                                                                                         //yani 10 ns lik bir delay anca en az 
                                                                                       //bir clock yaparak uyarlanabilir.
                                        counter = 20'd0;                                
                                    end
                            else
                                counter = counter + 20'd1;
                        end     
                    precompiler_delay_state: // Pre Compiler Delay.
                        begin
                            if (counter == precomp_delay)
                                begin
                                    counter = 20'd0;
                                    precomp_delay = 20'd0;
                                    state_next = check_isthereanywritingdata_state;
                                end
                            else
                                counter = counter + 20'd1;  
                        end
                    check_isthereanywritingdata_state: // 
                        begin
                            if (substate == 5'd6)
                                begin
                                    state_next = infinity_state; // yapilacak işlemler bittiyse öbür state e geç
                                    flag_function_is_set = 1;
                                end
                            else
                                begin
                                    substate = substate + 3'd1;
                                    state_next = write_state; 
                                end
                        end
                    infinity_state:
                        state_next = state_reg ; // durumunu korur.Program sona erer.
                endcase
        end

    assign LCD_E = sampled_LCD_E;
    //assign LCD_RW = sampled_LCD_RW;
    assign LCD_RS = sampled_LCD_RS;
    assign LCD_DATA [7:0] = sampled_LCD_DATA [7:0];
</code></pre>