Error in verilog, coding for CSHM Filter using generate statement
<pre><code>    module CSHM #(parameter data_width=8,order=4)
(y,in,clk,reset_n);

wire [data_width-1:0]coeff[0:order-1];
output reg signed [2*data_width-1:0]y;

input clk,reset_n;
input signed[data_width-1:0]in;
integer i;
wire [15:0] product1,product2,product3,product4,product5,product6,product7,product8;
wire signed[3:0]lsboutputcoeff;
wire signed[7:4]msboutputcoeff;
wire signed[2:0]lsbcount,msbcount;
wire signed[2:0]lsbselect,msbselect;

wire signed[2*data_width-1:0]muxoutput,shiftoutlsb,shiftoutmsb;
  wire [3:0] lsbcoeff;
  wire [7:4] msbcoeff;
    //reg [7:0] this_coeff;

wire [2:0]inputshift;
wire signed[15:0]muxout;
wire signed[15:0]leftshiftone,leftshifttwo,leftshiftthree;
wire [15:0]outputshift;




bankofprecomputers b1(.product1(product1),.product2(product2),.product3(product3),.product4(product4),.product5(product5),.product6(product6),.product7(product7),.product8(product8),.in(in));

genvar count;
generate        
 assign  coeff[0]= 8'd1;
 assign coeff[1]= 8'd2;
 assign coeff[2]= 8'd3;
 assign coeff[3]= 8'd4;
 for(count = 0; count &lt; order ; count = count+1)
 begin : gen_loop
    assign lsbcoeff = coeff[count][3:0];
      assign msbcoeff = coeff[count][7:4];



shifter s1(.lsboutputcoeff(lsboutputcoeff),.msboutputcoeff(msboutputcoeff),.lsbselect(lsbselect),.msbselect(msbselect),.lsbcount(lsbcount),.msbcount(msbcount),.lsbcoeff(lsbcoeff),.msbcoeff(msbcoeff));
   end
endgenerate
mux8_1msb m1(.muxoutput(muxoutput),.msbselect(msbselect),.product1(product1),.product2(product2),.product3(product3),.product4(product4),.product5(product5),.product6(product6),.product7(product7),.product8(product8));

mux8_1LSB m2(.muxoutput(muxoutput),.lsbselect(lsbselect),.product1(product1),.product2(product2),.product3(product3),.product4(product4),.product5(product5),.product6(product6),.product7(product7),.product8(product8));              

inverse_shifter is1(.shiftoutmsb(shiftoutmsb),.muxoutput(muxoutput),.msbcount(msbcount));

inverse_shifter_LSB is2 (.shiftoutlsb(shiftoutlsb),.muxoutput(muxoutput),.lsbcount(lsbcount));



      always@(negedge clk)
        begin
      y = shiftoutmsb+shiftoutlsb;
          end



endmodule
</code></pre>

<p>When im trying to synthesis , im getting error as </p>

<blockquote>
  <p>Multi-source in Unit  on signal lsbcoeff3; this signal is
  connected to multiple drivers.</p>
  
  <p>Multi-source in Unit  on signal lsbcoeff0; this signal is
  connected to multiple drivers.</p>
</blockquote>

<p><strong>If im wrong anywhere , please guide me</strong> </p>