yosys fails at ABC pass (on counter.v demo)
<p>I hope someone can help me with this...</p>

<p>This is my first encounter with yosys. For the start, I'm trying to run the very same demo as Clifford explained in his presentation. I downloaded the demo at the following location: <a href="https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro" rel="nofollow">https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro</a></p>

<p>yosys run beaks at the ABC pass with following message:</p>

<pre><code>12. Executing ABC pass (technology mapping using ABC).

12.1. Extracting gate netlist of module `\counter' to `&lt;abc-temp-dir&gt;/input.blif'..
Extracted 6 gates and 12 wires to a netlist network with 4 inputs and 2 outputs.

12.1.1. Executing ABC.
Running ABC command: &lt;yosys-exe-dir&gt;/yosys-abc -s -f &lt;abc-temp-dir&gt;/abc.script 2&gt;&amp;1
ABC: ABC command line: "source &lt;abc-temp-dir&gt;/abc.script".
ABC: 
ABC: + read_blif &lt;abc-temp-dir&gt;/input.blif 
ABC: + read_lib -w /home/boris/Documents/Self Learning/yosys_synthesys/mycells.lib 
ABC: usage: read_lib [-SG float] [-M num] [-dnvwh] &lt;file&gt;
ABC:               reads Liberty library from file
ABC:    -S float : the slew parameter used to generate the library [default = 0.00]
ABC:    -G float : the gain parameter used to generate the library [default = 0.00]
ABC:    -M num   : skip gate classes whose size is less than this [default = 0]
ABC:    -d       : toggle dumping the parsed library into file "*_temp.lib" [default = no]
ABC:    -n       : toggle replacing gate/pin names by short strings [default = no]
ABC:    -v       : toggle writing verbose information [default = yes]
ABC:    -v       : toggle writing information about skipped gates [default = yes]
ABC:    -h       : prints the command summary
ABC:    &lt;file&gt;   : the name of a file to read
ABC: ** cmd error: aborting 'source &lt;abc-temp-dir&gt;/abc.script'
ERROR: Can't open ABC output file `/tmp/yosys-abc-KDGya6/output.blif'.
[boris@E7440 yosys_synthesys]$ 
</code></pre>

<p>I have had a look at the file location mentioned in the error statement above, there is no output.blif in there:</p>

<pre><code>[boris@E7440 yosys_synthesys]$ ll /tmp/yosys-abc-KDGya6/
total 12K
-rw-rw-r--. 1 boris boris 542 Jul  5 11:21 abc.script
-rw-rw-r--. 1 boris boris 526 Jul  5 11:21 input.blif
-rw-rw-r--. 1 boris boris 852 Jul  5 11:21 stdcells.genlib
[boris@E7440 yosys_synthesys]$ 
</code></pre>

<hr>

<p>Buy the way, here is some system/tools info that might be relevant for debugging:</p>

<pre><code>Linux E7440.DELL 4.4.13-200.fc22.x86_64 #1 SMP Wed Jun 8 15:59:40 UTC 2016 x86_64 x86_64 x86_64 GNU/Linux

Yosys 0.6+141 (git sha1 080f95f, gcc 5.3.1 -fPIC -Os)

UC Berkeley, ABC 1.01 (compiled Mar  8 2015 01:00:49)
</code></pre>