Make an up down counter using structural design
<p>I've tried to made a 4 bit up down counter using structural design .
My code is the following :</p>

<pre><code>entity counter4bit is
    Port ( clock : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           load : in  STD_LOGIC;
           enable : in  STD_LOGIC;
           counterOut : out  STD_LOGIC_VECTOR (3 downto 0);
           updown : in  STD_LOGIC);
end counter4bit;

architecture Behavioral of counter4bit is

component D_FlipFlop
    Port ( d : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clock : in  STD_LOGIC;
           load : in  STD_LOGIC;
           enable : in  STD_LOGIC;
           updown : in  STD_LOGIC;
           q : out  STD_LOGIC);
end component;

component MUX 
    Port ( i0 : in  STD_LOGIC; 
           i1 : in  STD_LOGIC; 
           i2 : in  STD_LOGIC; 
           i3 : in  STD_LOGIC;
           inload : in  STD_LOGIC;
           bitout : out  STD_LOGIC;
           load : in  STD_LOGIC;
           updown : in  STD_LOGIC;
           en : in  STD_LOGIC);
end component;

signal w: std_logic_vector(3 downto 0);
signal cnt : std_logic_vector(3 downto 0);

begin

FF0 : D_FlipFlop
    port map( d =&gt; w(0),
                 reset =&gt; reset,
                 clock =&gt;clock,
                 load =&gt; load,
                 enable =&gt; enable,
                 updown =&gt; updown,
                 q =&gt; cnt(0) );

FF1 : D_FlipFlop
    port map( d =&gt; w(1),
                 reset =&gt; reset,
                 Clock =&gt; clock,
                 load =&gt; load,
                 enable =&gt; enable,
                 updown =&gt; updown,
                 q =&gt; cnt(1));

FF2 : D_FlipFlop
    port map( d =&gt; w(2),
                 reset =&gt; reset,
                 clock =&gt; clock,
                 load =&gt; load,
                 enable =&gt; enable,
                 updown =&gt; updown,
                 q =&gt; cnt(2));

FF3 : D_FlipFlop
    port map( d =&gt; w(3),
                 reset =&gt; reset,
                 clock =&gt; clock,
                 load =&gt; load,
                 enable =&gt; enable,
                 updown =&gt; updown,
                 q =&gt; cnt(3));

MUX0 : MUX
    port map( i0 =&gt; '1',
                 i1 =&gt; '1',
                 i2 =&gt; '1',
                 i3 =&gt; cnt(0),
                 inload =&gt; '1',
                 bitout =&gt;w(0) ,
                 load =&gt; load,
                 updown =&gt; updown,
                 en =&gt; enable);

MUX1 : MUX
    port map( i0 =&gt; cnt(0),
                 i1 =&gt;'1',
                 i2 =&gt; '1',
                 i3 =&gt; cnt(1),
                 inload =&gt; '1',
                 bitout =&gt;w(1) ,
                 load =&gt; load,
                 updown =&gt; updown,
                 en =&gt; enable); 

MUX2 : MUX
    port map( i0 =&gt; cnt(0),
                 i1 =&gt; cnt(1),
                 i2 =&gt;  '1',
                 i3 =&gt; cnt(2),
                 inload =&gt; '0',
                 bitout =&gt;w(2) ,
                 load =&gt; load,
                 updown =&gt; updown,
                 en =&gt; enable);

MUX3 : MUX
    port map( i0 =&gt; cnt(0),
                 i1 =&gt; cnt(1),
                 i2 =&gt;cnt(2),
                 i3 =&gt; cnt(3),
                 inload =&gt; '0',
                 bitout =&gt;w(3) ,
                 load =&gt; load,
                 updown =&gt; updown,
                 en =&gt; enable);

counterOut &lt;= cnt ;

end Behavioral;
</code></pre>

<p>When I simulate it it starts from 0 as it should cause of the reset , then counts to 1 and then again 0 . I can't see why it goes back to 0 after 1.</p>

<p>Here is my code for mux :</p>

<pre><code>entity MUX is
    Port ( i0 : in  STD_LOGIC; 
           i1 : in  STD_LOGIC; 
           i2 : in  STD_LOGIC; 
           i3 : in  STD_LOGIC;
           inload : in  STD_LOGIC;
           bitout : out  STD_LOGIC;
           load : in  STD_LOGIC;
           updown : in  STD_LOGIC;
           en : in  STD_LOGIC);
end MUX;

architecture Behavioral of MUX is
signal  sel : std_logic_vector(1 downto 0);
signal y, z, x: std_logic;
begin

y &lt;= (updown and i0 and i1 and i2 and en);
z &lt;= (not updown) and i0 and i1 and i2 and en;

sel(0) &lt;= not load;
sel(1) &lt;= y or z ;

process(sel, x)
    begin 
        if sel = "00" then x&lt;= i3;
        elsif sel = "01" then x &lt;= (not i3);
        else    x &lt;= inload;
        end if;
    end process;
    bitout &lt;= x ;
end Behavioral;
</code></pre>

<p>And the code for Flip Flop :</p>

<pre><code>entity D_FlipFlop is
    Port ( d : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clock : in  STD_LOGIC;
           load : in  STD_LOGIC;
           enable : in  STD_LOGIC;
           updown : in  STD_LOGIC;
           q : out  STD_LOGIC);
end D_FlipFlop;

architecture Behavioral of D_FlipFlop is

begin

process(clock, reset)
begin
    if (reset = '0') then
        q &lt;= '0';
    elsif (rising_edge(clock)) then
        q &lt;= d;
    end if;
end process;

end Behavioral;
</code></pre>

<p>I have to note that load and enable are synchronous while reset is asynchronous, i will also attach one picture of my simulation .<a href="https://i.stack.imgur.com/gSend.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gSend.png" alt="enter image description here"></a></p>