VHDL: Assigning a smaller std_logic_vector to a bigger one
<p>I'm trying to assign a smaller <code>std_logic_vector</code> to a bigger one like this:
</p>

<pre><code>library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

entity subarray_tb is
end subarray_tb;


architecture VERHALTEN of subarray_tb is 

signal big : std_logic_vector(15 downto 0) := x"A5A5";
signal small : std_Logic_vector(7 downto 0) := x"F0";

begin

  big &lt;= small;

end VERHALTEN;
</code></pre>

<p>As expected I get the following error from within Modelsim:</p>

<blockquote>
  <p>** Error (suppressible): C:/altera/15.1/subarray_tb.vhd(19): (vcom-1272) Length of expected is 16; length of actual is 8.</p>
</blockquote>

<p>I know how to fix this, but I'm not happy with the result, cause it looks very unreadable:</p>

<pre><code>big(big'LEFT downto (big'LEFT-small'LENGTH+1)) &lt;= small;
</code></pre>

<p>I don't want to use fixed ranges in the brackets cause my real problem is a bit more complex. The smaller array is a concatenation of different std_logic_vectors, so I want the solution to be flexible.</p>

<p>Has anyone a nicer solution that is more human readable?</p>