block ram (BRAM) read and write using different clocks
<p>I am relatively new to some advanced VHDL programming and have a problem i have been facing for a while. 
I will try to be very thorough in my problem description.</p>

<p>I am using a Digilent Nexys-3 board with SPARTAN - 6 FPGA</p>

<p>Here is what i am trying to implement:</p>

<ul>
<li>Read data from ADC SPI bus and store it into the BRAM.</li>
<li><p>For this i instantiate a block RAM using a memory IP core generator</p>

<pre><code>ADC_BRAM: bram
port map( ..
          ..
          addra =&gt; addra,
          dina =&gt; ADC_DATA,
          ..
          ..
         );
</code></pre></li>
</ul>

<p>The addra, ADC_DATA (data on SPI bus stored into a std_logic_vector) is assigned during the "read_adc" state of the FSM in the ADC module.</p>

<ul>
<li><p>After the ADC has sampled 100 points I stop writing into the BRAM</p>

<pre><code>main: process(clk)
begin
if(rising_edge(clk)) then

case state is

when  read_adc =&gt;
.....   
.....   
.....   
if(addra &lt; "1100100") then
.....   
   &lt;some code&gt;  
   addra &lt;= addra + 1;
.....            
elsif (addra = "1100100") then
   state &lt;= endofconversion;
end if;

when endofconversion =&gt;
    addra &lt;= "00000000";
    wea   &lt;= "0"; -- write enable for BRAM

    state &lt;= read_bram;
</code></pre></li>
<li><p>Next, i want to access the data from the BRAM and send it using USB-UART. </p></li>
<li><p>From what i understand all the BRAM's are synchronous and thus have to be implemented with process(clk,reset).</p></li>
<li><p>Currently i have implemented the state " read_bram" under the same process as mentioned above</p>

<pre><code>main: process(clk)
begin
if(rising_edge(clk)) then

case state is

&lt;some code&gt; 

when endofconversion =&gt;
    addra &lt;= "00000000";
    wea   &lt;= "0"; -- write enable for BRAM

    state &lt;= read_bram;

when read_bram =&gt;
.... 
&lt;some code&gt;
....
end case;
</code></pre></li>
<li><p>Now the UART clock needs to be much slower than the rate at which ADC has been read. </p></li>
</ul>

<p>My question is " <strong><em>How do i implement the read operation of the BRAM using a much slower clock, which will ensure proper functioning of the UART" ?</em></strong></p>

<p>I also tried another approach where the BRAM module is defined in the top level file and i send the " addra, ADC_DATA" generated from the ADC module into the port map of the BRAM module.</p>

<p>Now, on the top level if i create a slower clock to read the data ("douta") from the BRAM and send it to UART, i need to generate "addra"  in this process and send it to BRAM port "addra"</p>

<p>This causes issues of " multiple drivers " connected to signal "addra", as its values changes in the "process()"  of both the ADC module (faster clock) and the top level module (slower clock).</p>

<p>Please help me out. I can provide more info if the problem description is not clear.</p>

<p><strong><em>TLDR; How can i use 2 separate clocks while implementing synchronous memory BRAM
 - "faster clock => write into BRAM" -- based on ADC sampling rate
 - " slower clock => read from BRAM"  -- based on UART clk (slower BAUD rate than ADC sampling speed)</em></strong></p>