VHDL frequency divider code
<p>I have this code:</p>

<pre><code>architecture Behavioral of BlockName is
  signal t: std_logic;
  signal c : std_logic_vector (1 downto 0);
begin
  process (reset, clk) begin
    if (reset = '1') then
      t &lt;= '0';
      c &lt;= (others=&gt;'0');
    elsif clk'event and clk='l' then
      if (c = din) then
        t &lt;= NOT(t);
        c &lt;= (others=&gt;'0');
      else
        c &lt;= c + 1;
      end if;
    end if;
  end process;
  dout &lt;= t;
end Behavioral;
</code></pre>

<p>This code's role is to divide the frequency when it gets input (clock + value) and outputs a divided frequency.</p>

<p>Now my questions:</p>

<ol>
<li>What does this <code>c &lt;= (others=&gt;'0');</code> mean ?</li>
<li>What value does t get here <code>t &lt;= NOT(t);</code> ? the last t value?  does the <code>&lt;=</code> work as <code>=</code> ?</li>
</ol>