can packed arrays be passed by reference to the task in systemverilog
<p>Can s_clk be passed as argument to xyz task in below code?</p>

<pre><code>module test(input logic m_clk, output [1:0] logic s_clk);
  ...
  xyz (m_clk,s_clk);//assuming m_clks and s_clks are generated from top
  ...
  task automatic xyz (ref logic clk1, ref [1:0] logic clk2);
    ...
  endtask
endmodule
</code></pre>