Verilog, Module Instantiation with inputs from different modules
<p>Module's Hierarchy where uart_receiver.v=ModuleA, RSD.v=ModuleB, uart_transmitter.V=ModuleC<br>
<img src="https://i.stack.imgur.com/5YuaN.png" alt=""></p>

<p>Suppose I want to Instantiate <strong>ModuleA</strong> with inputs from different modules, B, and the name of inputs are: <em>WR_EN</em> from <strong>moduleB</strong> and <em>RD_EN</em>, <em>DT</em> from <strong>moduleC</strong></p>

<pre><code>module A(
  input wr_EN,
  input rd_EN,
  input DT,
  output out
);
</code></pre>

<p>I tried to do the below with no success, in ISE Xilinx with Verilog</p>

<p><strong>B MODULE</strong></p>

<pre><code>module B(...)
  assign wr_EN = 1;
  ...  
  // Now call module A from B:
  module A A_instance(.wr_EN(wr_EN) );
</code></pre>

<p><strong>C MODULE</strong></p>

<pre><code>module C(...) 
  ... 
  assign rd_EN = 0;
  assign DT = 1;
  .... 
  // And then call module A from C
  module A A_instance(.rd_EN(rd_EN), .DT(DT) );
</code></pre>

<p>If I call module instances with same names the program doesn't make a second instance, despite the fact that I want one. 
 I searched but I haven't found similar example</p>