How to bind a SV interface signal to a VHDL type?
<p>I am trying to bind an interface to my VHDL module. The signal that I want to bind to is defined as follows in the module:</p>

<pre><code>TYPE dut_fsm_type is (
                           IDLE_STATE,
                           WAIT_STATE,
                           IDENTIFY_STATE,
                           LATCH_STATE,
                           DONE_STATE,
                           ERROR_STATE
                          );
signal dut_fsm_state       : dut_fsm_type;
signal prev_dut_fsm_state  : dut_fsm_type;
</code></pre>

<p>My instantiation of the interface module and bind statement looks something like this:</p>

<pre><code>bind my_dut my_intf my_intf_0 (.*,
                               .fsm_state     (tb.u_dut.dut_fsm_state),
                               .prev_fsm_state(tb.u_dut.prev_dut_fsm_state)
                              );
</code></pre>

<p>I had no idea what length my input signal fsm_state should be, so I just set it to 32 bits.</p>

<pre><code>interface my_intf (
  input bit[31:0] fsm_state,
  input bit[31:0] prev_fsm_state
);
</code></pre>

<p>When I try to compile in questasim 10.4, I get the following message:</p>

<blockquote>
  <p>(vopt-2245) Type ('dut_fsm_type') of VHDL hierarchical reference, used
  as actual expression in bind statement, must be defined in a package.</p>
</blockquote>

<p>Any idea how to handle this?</p>