Verilog: wire value not updated
<p>I have the following MWE:</p>

<pre><code>module test(
    input wire clock,
    input wire start
);

reg [7:0] x = 8'b10101010;
reg processing = 0;
wire [7:0] x_wire0 = x;
wire [7:0] x_wire1 = {4'hf, x};
wire [11:0] x_wire2 = {4'hf, x};

always @(posedge clock) begin
   if (start &amp; ~processing) begin
       x = 8'h0f;
       processing = 1;
   end

   $display("---&gt; x=%h x_wire0=%h x_wire1=%h x_wire2=%h",
       x, x_wire0, x_wire1, x_wire2);
end
endmodule
</code></pre>

<p>with the testbench</p>

<pre><code>module test_test();

reg clock = 0;
reg start = 0;

test test(
    .clock(clock),
    .start(start)
);

always #5 clock = ~clock;

initial begin
    $monitor("%b %b", clock, start);

    #20 start = 1;
    #20 start = 0;

    #200 $finish;
end
endmodule
</code></pre>

<p>which using Icarus Verilog 0.9.7 gives me the output</p>

<pre><code>0 0
---&gt; x=aa x_wire0=aa x_wire1=aa x_wire2=faa
1 0
0 0
---&gt; x=aa x_wire0=aa x_wire1=aa x_wire2=faa
1 0
0 1
---&gt; x=0f x_wire0=0f x_wire1=aa x_wire2=f0f
1 1
0 1
---&gt; x=0f x_wire0=0f x_wire1=0f x_wire2=f0f
1 1
0 0
...
</code></pre>

<p>I wonder why x_wire1 is not updated until the next clock tick and whether there are any rules (of thumb) to avoid these kind of situations.
If I use a "#0" before the display command, it is updated.</p>