I'm trying to write a code for counter using vhdl
<p>this is the VHDL code for synchronous type counter. As I'm still new in vhdl, I'm having problem in writing the testbench to simulate this code. can anyone give me some suggestions on how to write the testbench? thank you</p>

<pre><code>library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity cnt4 is
    port( CLK, RST  : in std_logic;
          Q         : out std_logic);
end cnt4;

architecture EX1 of cnt4 is
signal cnt : std_logic_vector(1 downto 0);

begin
    process(CLK, RST)
    begin
        if RST = '1' then
            cnt &lt;= "00";
        elsif CLK'event and CLK = '1' then
            if cnt = 3 then
                cnt &lt;= "00";
                Q &lt;= '1';
            else
                cnt &lt;= cnt + 1;
                Q &lt;= '0';
            end if;
        end if;
    end process;
end EX1;
</code></pre>

<hr>

<p>this is the testbench that i've tried to write so far</p>

<pre><code>library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity TESTBENCH is 
end TESTBENCH;

architecture EX1 of TESTBENCH is
    signal CLK, RST : std_logic;
    signal Q        : std_logic;

    component cnt4
        port( CLK, RST : in std_logic;
              Q        : out std_logic );
    end component;

begin
    U0: cnt4 port map(CLK, RST, Q);

    process
    begin
        CLK &lt;= '1';
        wait for 10 ns;
        CLK &lt;= '0';
        wait for 10 ns;
        wait;
    end process;

    process
    begin
        RST &lt;= '0'; wait for 10 ns;
        RST &lt;= '1'; wait for 10 ns;

        wait;
    end process;
end EX1;
</code></pre>

<p>the simulation result using the testbench above is as in the picture</p>

<p><a href="http://i.stack.imgur.com/el1ze.jpg" rel="nofollow">simulation</a></p>

<p>it may look ridiculous as I don't really know how to write the testbench. would be glad if anyone can help me</p>