Creating a 32 bit ALU in Structural Verilog and I'm not quite sure how to implement opcodes
<p>I have to create a 32 bit ALU in structural verilog with opcodes for AND(000), OR(001), ADD(010), SUB(110), SLT(111), and BEQ(100).  I understand how each of these work individually at the gate level I'm just confused on how to use opcodes to get my desired output.  For example if it was a high level language I would write something like if opcode == 100 {output = branch}.  I apologize if this is a dumb question I'm just new to verilog and many of the answers online either use behavioral verilog or are very confusing.</p>

<p><a href="https://i.stack.imgur.com/FJ7rX.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/FJ7rX.jpg" alt="Image of circuit"></a></p>