In systemverilog # delay fails when RHS signal changes faster than delay
<p>Following code in systemverilog fails:</p>

<pre><code>module test_dly;
  reg clk = 0;
  wire w_clk_d;

  always #1ns  clk &lt;= ~clk;
  assign #1400ps w_clk_d = clk;
endmodule
</code></pre>

<p>I expected that w_clk_d will be delayed version of clk, but it is not.
Seems that # not working if new event arrived before delay expired.
I wrote code to deal with this, but is there way to make # work as expected?
Thanks,</p>