What is the difference between = and <= in Verilog?
<p>What is the difference between <code>=</code> and <code>&lt;=</code> in this code?  Also, how do I print the value of <code>data</code>?</p>

<pre><code>    module always_example();
reg clk,reset,enable,q_in,data;

always @ (posedge clk)
if (reset)  begin
   data &lt;= 0;
end else if (enable) begin   
   data &lt;= q_in;
end
// if i put     $print("data=%d", data);   there is error
endmodule
</code></pre>