VHDL - comparing signals (integers) in IF-statement
<p>I am trying to write code to change the frequency of my clock. But the output is always zeroes...</p>

<pre><code>signal cycle_counter : integer := 0;
signal HALFCYCLES : integer;
signal MY_CLK1, temporal : std_logic :='0';

frequency_divider: process (Clk,cycle_counter, HALFCYCLES) 
begin
   if rising_edge(Clk) then
          cycle_counter &lt;= cycle_counter + 1;
          if cycle_counter = (HALFCYCLES-1) then 
              temporal &lt;= NOT(temporal);
              cycle_counter &lt;= 0;
          end if;
   end if;
      MY_CLK1 &lt;= temporal;  
    end process frequency_divider;
</code></pre>

<p>When i put instead of <code>HALFCYCLES-1</code> some integer value, all is working just fine, but i need this signal to be changeable.
I believe, that the problem is in comparing, but can't detect it.</p>

<p>I tried  to make <code>HALFCYCLES</code> a variable, instead of signal, but compiler was against it :)</p>

<p>Full code (main goan - to put in the LED two different animations. Frequency and type of animation you should choose via switchers (input logic_vector S)</p>

<pre><code>    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LED2 is
  generic (FIFT : std_logic_vector (15 downto 0) := "1111111111111111";
        ZERO : std_logic_vector (15 downto 0) := "0000000000000000");
    Port ( S : in  STD_LOGIC_VECTOR (7 downto 0);
           Clk : in  STD_LOGIC;
           R : in  STD_LOGIC;
           LED : out  STD_LOGIC_VECTOR (7 downto 0));
end LED2;

architecture Behavioral of LED2 is
signal statement: std_logic_vector (7 downto 0);
signal cycle_counter : integer := 0;
signal CNT1, CNT2, CURCNT, CNT_NO : integer:= 0;
signal HALFCYCLES : integer;
signal MY_CLK1, MY_CLK2, temporal : std_logic :='0';

begin

frequency_divider: process (Clk,cycle_counter, HALFCYCLES) begin
  if rising_edge(Clk) then
      cycle_counter &lt;= cycle_counter + 1;
    if cycle_counter = (HALFCYCLES-1) then --(HALFCYCLES-1)
      temporal &lt;= NOT(temporal);
      cycle_counter &lt;= 0;
    end if;
  end if;
  MY_CLK1 &lt;= temporal;
  MY_CLK2 &lt;= temporal;  
end process frequency_divider;




counter1: PROCESS (MY_CLK1, R)
BEGIN
IF (MY_CLK1 = '1' AND MY_CLK1'EVENT) THEN
    IF (R='1')  THEN 
    CNT1 &lt;=0;
    ELSIF (CNT1 = 15) THEN
      CNT1 &lt;= 0;
    ELSE
      CNT1 &lt;= CNT1 + 1;
   END IF;
END IF;
END PROCESS counter1;

counter2: PROCESS (MY_CLK2, R)
BEGIN
IF (MY_CLK2 = '1' AND MY_CLK2'EVENT) THEN
    IF (R='1')  THEN 
    CNT2 &lt;=0;
    ELSE
    if (CNT2 = 15) then
      CNT2 &lt;= 0;
      else
      CNT2 &lt;= CNT2 + 1;
    end if;
  END IF;
END IF;
END PROCESS counter2;

freq_changer: PROCESS (CNT1, CNT2, S)
BEGIN
  IF (S(7) = '1')
  THEN HALFCYCLES &lt;= 50000000;  CURCNT &lt;= CNT1; CNT_NO &lt;= 1;--1hz
  ELSIF (S(6) = '1')
  THEN HALFCYCLES &lt;= 5000000;   CURCNT &lt;= CNT2; CNT_NO &lt;= 2;--10hz
  ELSIF (S(5) = '1')
  THEN HALFCYCLES &lt;= 500000;    CURCNT &lt;= CNT1; CNT_NO &lt;= 1;--100hz
  ELSIF (S(4) = '1')
  THEN HALFCYCLES &lt;= 50000;     CURCNT &lt;= CNT2; CNT_NO &lt;= 2;--1khz
  ELSIF (S(3) = '1')
  THEN HALFCYCLES &lt;= 5000;      CURCNT &lt;= CNT1; CNT_NO &lt;= 1;--10khz
  ELSIF (S(2) = '1')
  THEN HALFCYCLES &lt;= 500;           CURCNT &lt;= CNT2; CNT_NO &lt;= 2;--100khz
  ELSIF (S(1) = '1')
  THEN HALFCYCLES &lt;= 50;            CURCNT &lt;= CNT1; CNT_NO &lt;= 1;--1mhz
  ELSIF (S(0) = '1')
  THEN HALFCYCLES &lt;= 10;            CURCNT &lt;= CNT2; CNT_NO &lt;= 2;--5mhz
  ELSE HALFCYCLES &lt;= 5;         CURCNT &lt;= CNT1; CNT_NO &lt;= 1;--10mhz
   END IF;
END PROCESS freq_changer;

main: PROCESS (CNT_NO, CURCNT)
BEGIN
c:  CASE  CNT_NO IS
    WHEN 2 =&gt;
counter2:CASE CURCNT IS
        WHEN 0  =&gt; statement &lt;= "00000001";
        WHEN 1  =&gt; statement &lt;= "00000010";
        WHEN 2  =&gt; statement &lt;= "00000100";
        WHEN 3  =&gt; statement &lt;= "00001000";
        WHEN 4  =&gt; statement &lt;= "00010000";
        WHEN 5  =&gt; statement &lt;= "00100000";
        WHEN 6  =&gt; statement &lt;= "01000000";
        WHEN 7  =&gt; statement &lt;= "10000000";
        WHEN 8  =&gt; statement &lt;= "10000000";
        WHEN 9  =&gt; statement &lt;= "01000000";
        WHEN 10     =&gt; statement &lt;= "00100000";
        WHEN 11     =&gt; statement &lt;= "00010000";
        WHEN 12     =&gt; statement &lt;= "00001000";
        WHEN 13     =&gt; statement &lt;= "00000100";
        WHEN 14     =&gt; statement &lt;= "00000010";
        WHEN 15     =&gt; statement &lt;= "00000001";
        WHEN OTHERS =&gt; statement &lt;= "00000000";
      END CASE counter2;

    WHEN OTHERS =&gt;
counter1:CASE CURCNT IS
        WHEN 0  =&gt; statement &lt;= "10000001";
        WHEN 1  =&gt; statement &lt;= "01000010";
        WHEN 2  =&gt; statement &lt;= "00100100";
        WHEN 3  =&gt; statement &lt;= "00011000";
        WHEN 4  =&gt; statement &lt;= "00011000";
        WHEN 5  =&gt; statement &lt;= "00100100";
        WHEN 6  =&gt; statement &lt;= "01000010";
        WHEN 7  =&gt; statement &lt;= "10000001";
        WHEN 8  =&gt; statement &lt;= "00011000";
        WHEN 9  =&gt; statement &lt;= "00100100";
        WHEN 10     =&gt; statement &lt;= "01000010";
        WHEN 11     =&gt; statement &lt;= "10000001";
        WHEN 12     =&gt; statement &lt;= "10000001";
        WHEN 13     =&gt; statement &lt;= "01000010";
        WHEN 14     =&gt; statement &lt;= "00100100";
        WHEN 15     =&gt; statement &lt;= "00011000";
        WHEN OTHERS =&gt; statement &lt;= "00000000";
      END CASE counter1;
  END CASE c;
  LED &lt;= statement;
END PROCESS main;



end Behavioral;
</code></pre>

<p>testbench</p>

<pre><code>LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.Numeric_Std.all;



ENTITY LED_controller_tb IS
END LED_controller_tb;

ARCHITECTURE behavior OF LED_controller_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT LED2
    PORT(
         S : IN  std_logic_vector(7 downto 0);
         Clk : IN  std_logic;
         R : IN  std_logic;
         LED : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal S : std_logic_vector(7 downto 0) := (others =&gt; '0');
   signal Clk : std_logic := '0';
   signal R : std_logic := '0';

         --Outputs
   signal LED : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant Clk_period : time := 10 ns;

BEGIN

        -- Instantiate the Unit Under Test (UUT)
   uut: LED2 PORT MAP (
          S =&gt; S,
          Clk =&gt; Clk,
          R =&gt; R,
          LED =&gt; LED
        );

   -- Clock process definitions
   Clk_process :process
   begin
                Clk &lt;= '0';
                wait for Clk_period/2;
                Clk &lt;= '1';
                wait for Clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
            wait for Clk_period * 8;    

                S &lt;= std_logic_vector(to_unsigned(to_integer(unsigned(S)) + 1, 8));

      -- insert stimulus here 

   end process;

reset: PROCESS
        BEGIN
                WAIT FOR  1 us;
                R &lt;= '1';
                WAIT FOR 500 ns;
                R &lt;= '0';
        END PROCESS reset;
END;
</code></pre>