Makefile set variable in target
<p>I have a makefile where a variable <code>$DEBUG</code> decides whether to build for deployment or debugging. There is one main Makefile, and multiple platform-specific makefiles that get included. I want the variable <code>$DEBUG</code> to be set to <code>1</code> automatically when the target <code>test</code> is built.</p>

<p>The main makefile:</p>

<pre><code>DEBUG := 0

test : override DEBUG := 1

DIST_DIR := dist/
ifeq ($(DEBUG), 1)
    BUILD_DIR := build/debug
else
    BUILD_DIR := build/deploy
endif


# detect operating system
ifeq ($(OS), Windows_NT)
    UNAME := Windows
else
    UNAME := $(shell uname -s)
endif

# include platform-specific Makefile
export
ifeq ($(UNAME), Darwin)
    include Makefile.darwin
endif
ifeq ($(UNAME), Linux)
    include Makefile.linux
endif
</code></pre>

<p>And the platform-specific <code>Makefile.linux</code>:</p>

<pre><code>... 
CXX := clang++-3.8
CXXFLAGS := -std=c++14 -fPIC -I./external/include -fcolor-diagnostics
LDFLAGS := 
LDLIBS := -lpthread -lm


ifeq ($(DEBUG), 1)
    CXXFLAGS += -g
else
    CXXFLAGS += -O3 -DNDEBUG
endif

... 

all : $(TARGET)


test : $(TEST_TARGET)
    $(TEST_TARGET)
</code></pre>

<p>So there are two rules for <code>test</code>: One in the main makefile sets the target-specific variable <code>$DEBUG</code>, and the one in <code>Makefile.linux</code> builds the test. The variables used for building (<code>$CXXFLAGS</code>, <code>$BUILDDIR</code>, and others) are set before the rules, and use conditionals.</p>

<p>Everything in the makefiles is working correctly, however calling <code>make test</code> does not alter the variable <code>$DEBUG</code>: both <code>$CXXFLAGS</code> and <code>$BUILDDIR</code> still get set to the values they would have for a deployment built.</p>

<p>Is there a way to first set <code>$DEBUG := 1</code> in <code>Makefile</code> when the target is <code>test</code>, and then normally proceed?
Or is there a special variable that contains the target name, for example</p>

<pre><code>ifeq ($(MAKEFILE_TARGET), test)
    ...
endif
</code></pre>