Structural design of Shift Register in VHDL
<p>I've made a structural design of a shift register in vhdl . When WriteShift is 1 then I got shift and when it is 0 then shift register loads a price. Although load works perfectly when I set writeshift to 1 in testbench I get 00000 in simulation.</p>

<p>My code is the following:</p>

<pre><code>entity ShiftRegis is
    Port ( Din : in  STD_LOGIC_VECTOR (4 downto 0);
           WriteShift : in  STD_LOGIC;
           Clock : in  STD_LOGIC;
              reset : in  STD_LOGIC;
              En : in STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (4 downto 0));
end ShiftRegis;

architecture Behavioral of ShiftRegis is

component notGate 
    Port ( in0 : in  STD_LOGIC;
           out0 : out  STD_LOGIC);
end component;

component nand4Gate 
    Port ( i0 : in  STD_LOGIC;
           i1 : in  STD_LOGIC;
           i2 : in  STD_LOGIC;
           i3 : in  STD_LOGIC;
           bitOut : out  STD_LOGIC);
end component;

component D_FlipFlop 
    Port ( Din : in  STD_LOGIC;
           En : in  STD_LOGIC;
           Q : out  STD_LOGIC;
              reset : in STD_LOGIC;
           Clk : in  STD_LOGIC);
end component;

signal q4, q3, q2, q1, in3, in2, in1, in0, notWS : std_logic;

begin

ff4 : D_FlipFlop
    port map( Din =&gt; Din(4),
             En =&gt; En,
             Q =&gt; q4,
                reset =&gt; reset,
             Clk =&gt; Clock);

ff3 : D_FlipFlop
    port map( Din =&gt; in3,
             En =&gt; En,
             Q =&gt; q3,
                reset =&gt; reset,
             Clk =&gt; Clock);

ff2 : D_FlipFlop
    port map( Din =&gt; in2,
             En =&gt; En,
             Q =&gt; q2,
                reset =&gt; reset,
             Clk =&gt; Clock);

ff1 : D_FlipFlop
    port map( Din =&gt; in1,
             En =&gt; En,
             Q =&gt; q1,
                reset =&gt; reset,
             Clk =&gt; Clock);

ff0 : D_FlipFlop
    port map( Din =&gt; in0,
             En =&gt; En,
             Q =&gt; Q(0),
                reset =&gt; reset,
             Clk =&gt; Clock);

notg4 : notGate
    port map( in0 =&gt; WriteShift,
                 out0 =&gt; notWS);

nandg3 : nand4Gate
    port map( i0 =&gt; Din(3),
             i1 =&gt; notWS,
             i2 =&gt; WriteShift,
             i3 =&gt; q4,
             bitOut =&gt; in3);

nandg2 : nand4Gate
    port map( i0 =&gt; Din(2),
             i1 =&gt; notWS,
             i2 =&gt; WriteShift,
             i3 =&gt; q3,
             bitOut =&gt; in2);

nandg1 : nand4Gate
    port map( i0 =&gt; Din(1),
             i1 =&gt; notWS,
             i2 =&gt; WriteShift,
             i3 =&gt; q2,
             bitOut =&gt; in1);

nandg0 : nand4Gate
    port map( i0 =&gt; Din(0),
             i1 =&gt; notWS,
             i2 =&gt; WriteShift,
             i3 =&gt; q1,
             bitOut =&gt; in0);

Q(4) &lt;= q4;
Q(3) &lt;= q3;
Q(2) &lt;= q2;
Q(1) &lt;= q1;

end Behavioral;
</code></pre>