Read, then write RAM VHDL
<p>in VHDL all the code lines are executed in a parallel way, since its a machine.
i want to create this RAM that reads a certain register from a ram block to the output and only 'afterwards' writes to the same register the input. my code goes like this:</p>

<pre><code>architecture Behavioral of RAM is

type ram_t is array (0 to numOfRegs-1) of std_logic_vector (rLength-1 downto 0);
signal ram_s: ram_t;
signal loc : integer;

begin

process(clk)
begin
    if(rising_edge(clk)) then
        if(we='1') then
            dataout &lt;= ram_s(loc); -- reads the 'old' data to the output 
            ram_s(loc) &lt;= datain;  --  writes the 'new' data to the RAM
            loc &lt;= conv_integer(addr);
        end if;
    end if;
end process;                
end Behavioral;
</code></pre>

<p>there is a similar case presented 
<a href="https://stackoverflow.com/questions/33875158/write-followed-by-read-in-vhdl-process">here</a>.</p>

<p>so I'd like to ask, is my code works fine or is there need for tweaking like putting a delay of half clock cycle, and if so, how to implement it.
I'm very new to VHDL thanks for your patience and help.</p>

<p>ive add a testbench simulation below . as can be seen the dataout isnt working at all.</p>

<p><a href="https://i.stack.imgur.com/d2WJv.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/d2WJv.jpg" alt="testbench i&#39;ve simulated"></a></p>