VHDL: conv_std_logic_vector parameter error
<p>I'm having some problems with the <code>conv_std_logic_vector</code> function in Quartus. I'm using the function to convert a integer variable into a <code>std_logic_vector</code>. When i compile the code below, Quartus shows the following error message: </p>

<blockquote>
  <p>Error (10344): VHDL expression error at counter_Wbits.vhd(32): expression has 3 elements, but must have 4 elements.</p>
</blockquote>

<p>I have searched this function on the internet and people always use 2 parameters, what is happening?</p>

<pre><code>LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_arith.ALL;

ENTITY counter_Wbits IS
  GENERIC(W : NATURAL := 4);
  PORT (portae   : IN  BIT;-- data input
        portas   : IN  BIT;-- data input
        clk : IN  BIT;  -- clock
        clrn: IN  BIT;  -- clear
        ena : IN  BIT;  -- enable
        q   : BUFFER STD_LOGIC_VECTOR(W-1 DOWNTO 0));-- data output
END counter_Wbits;

ARCHITECTURE arch_1 OF counter_Wbits IS
BEGIN
  PROCESS(clk,clrn)
  variable cont : integer range 0 to 15;
  BEGIN
    IF (clrn='0') THEN
      q &lt;= (OTHERS =&gt; '0');
    ELSIF (clk'EVENT AND clk='1') THEN
      IF (ena='1') THEN
        IF(portae='1') THEN
          cont := cont+1;
        ELSIF (portas='1') THEN
          cont := cont-1;
        END IF;
      END IF;
    END IF;
    q &lt;= conv_std_logic_vector(cont, W-1);  -- LINE 32
  END PROCESS;
END arch_1;
</code></pre>