Fixed point converstion; understanding the to_sfixed(x,y,z) vhdl functon in the ieee_proposed library
<p>I'm looking at some code containing the following line:</p>

<pre><code>a &lt;= to_sfixed (-3.125, 7, -6);
</code></pre>

<p><strong>What is in <code>a</code> after this line has been run?</strong></p>

<p>I think I've found the function in <code>float_pkg_c.vhd</code>, this appears to be a key part of the code:</p>

<pre><code>result_big := to_sfixed (
  arg         =&gt; STD_LOGIC_VECTOR(rsigned),
  left_index  =&gt; left_index,
  right_index =&gt; (right_index-3));
result := resize (arg            =&gt; result_big,
                  left_index     =&gt; left_index,
                  right_index    =&gt; right_index,
                  round_style    =&gt; round_style,
                  overflow_style =&gt; overflow_style);
</code></pre>

<p>I've read <a href="http://web.archive.org/web/20160305202256/http://www.vhdl.org/fphdl/" rel="nofollow">the guidance</a>. From <a href="http://web.archive.org/web/20160305202256/http://www.vhdl.org/fphdl/Float_ug.pdf" rel="nofollow">here</a>:</p>

<blockquote>
  <p>To_sfixed – “float” to “sfixed”. Inputs: arg (float), left_index and
  right_index (natural) OR size_res  (ufixed). Parameters round_style :
  Boolean (true), overflow_style : Boolean (true), check_error : Boolean
  (true), and denormalize : Boolean (true).</p>
</blockquote>

<p>However, I still haven't worked out the expected bits - Am I right to be expecting 13bits in total?</p>

<p><strong>Is there a simple way of answering such questions (e.g. with a command line interface) for myself?</strong> </p>