Change priority level level of running interrupt handler?
<p>I am trying to implement the following pseudocode on a cortex-m3 controller, (STM32L151 in particular)</p>

<pre><code>void SysTick_Handler() {
    do_high_priority_periodic_tasks(); // not to be interrupted
    lower_interrupt_priority();
    do_low_priority_periodic_tasks();  // these may be interrupted
}
</code></pre>

<p>In other words, run the first part with priority level 0, then somehow lower the current interrupt priority to 15, so that the rest could be preempted by other hardware interrupts.</p>

<p>One idea is to move <code>do_low_priority_periodic_tasks();</code> into a separate interrupt handler, and invoke this handler through <code>NVIC_SetPendingIRQ()</code> which sets a pending bit in the <code>NVIC-&gt;ISPR[]</code> register. This way, the other interrupt would immediately follow <code>SysTick</code>, unless there is anything with priority between 0 and 14 pending.</p>

<pre><code>#define LOWPRIO_IRQn 55
void IRQ55_Handler() {
    do_low_priority_periodic_tasks();  // these may be interrupted
}

void SysTick_Handler() {
    do_high_priority_periodic_tasks(); // not to be interrupted
    NVIC_SetPendingIRQ(LOWPRIO_IRQ);
}

void main() {
    HAL_Init();
    HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
    HAL_NVIC_SetPriority(LOWPRIO_IRQn, 15, 0);
    HAL_NVIC_EnableIRQ(LOWPRIO_IRQn);
    while(1) {
        /* main loop */
    }
}
</code></pre>

<p>I've picked IRQ 55 because it's not occupied on my controller, it would be the AES interrupt handler on a STM32L162, but I'm a bit worried there. Should I pick a different IRQ instead, perhaps an unused DMA channel interrupt? Is it safe to use interrupts 57-67, which are defined in the Cortex-M3 core, but not on the STM32L series? Is there any better way to do it?</p>