Is this code structure going in the right direction?
<p>I am trying to utilize a 7 segment display. I have written a module which I want to take 4 inputs and change the hex output. There seems to be an issue with unpacked/packed arrays and I really don't know what on earth I'm doing. Any help much appreciated.</p>

<pre><code>module hexDisplay(hex, c0, c1, c2, c3);
    input c0;
    input c1;
    input c2;
    input c3;      
    output hex[6:0];       
    reg out[6:0];

    always@(*)
    begin
        case({c3, c2, c1, c0})
            4'b0000:out [5:0] = 1;
            // 0001-1111 go here
            //...
            default:out [6:0] = 0;
         endcase
      assign hex = out;
     end

endmodule
</code></pre>

<p>Errors:</p>

<blockquote>
  <p>Error (10773): Verilog HDL error at lab2pre.v(55): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions
  Error (10133): Verilog HDL Expression error at lab2pre.v(61): illegal part select of unpacked array "out"</p>
  
  <p>Error (10133): Verilog HDL Expression error at lab2pre.v(62): illegal part select of unpacked array "out"</p>
  
  <p>Error (10048): Verilog HDL error at lab2pre.v(64): values cannot be assigned directly to all or part of array "hex" - assignments must be made to individual elements only</p>
  
  <p>Error (10137): Verilog HDL Procedural Assignment error at lab2pre.v(64): object "hex" on left-hand side of assignment must have a variable data type</p>
  
  <p>Error (10044): Verilog HDL error at lab2pre.v(64): expression cannot reference entire array "out"</p>
  
  <p>Error: Quartus II 64-Bit Analysis &amp; Synthesis was unsuccessful. 6 errors, 1 warning
      Error: Peak virtual memory: 959 megabytes
      Error: Processing ended: Tue Feb  2 17:33:35 2016
      Error: Elapsed time: 00:00:15
      Error: Total CPU time (on all processors): 00:00:46</p>
  
  <p>Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 1 warning</p>
</blockquote>