Combining `others` expression with `signed` cast
<p>Let <code>var</code> stand for a signed vector (library IEEE.NUMERIC_STD.ALL) of size <code>m</code>.</p>

<p>Let <code>foo</code> be another variable of type <code>std_logic_vector(n-1 downto 0)</code>, where n is smaller than m.</p>

<p>I want to concatenate a '0' left of <code>foo</code>, then pad it with zeroes in its right until it size is <code>m</code> and then store the result in <code>var</code>.</p>

<p>I tried</p>

<pre><code>rdsor &lt;= signed('0' &amp; divisor &amp; others=&gt;'0');
</code></pre>

<p>But Xilinx complains with the following message on synthesis:</p>

<pre><code>Syntax error near "others".
</code></pre>

<p>How do I do what I want?</p>