Is it possible to take input port as array in verilog?
<pre><code> module median_five(out1,a[0],a[1],a[2],a[3],a[4],en,clka);             
    input [7:0] a[0:4];              
    output out1;              
    endmodule            
</code></pre>

<p>**It is giving error.  </p>

<pre><code> module median_five(out1,a,b,c,d,e,en,clka);             
        input [7:0] a,b,c,d,e;              
        output out1;              
        endmodule   
</code></pre>

<p>**It is right.</p>

<p>But I want input a,b,c,d,e in array like :             </p>

<pre><code>array[0]&lt;=a;            
array[1]&lt;=b;               
array[2]&lt;=c;             
array[3]&lt;=d;            
array[4]&lt;=e;            
</code></pre>