Is it possible to do interactive user input and output simulation in VHDL or Verilog?
<p>For example, I would like to run a simulation for an interactive game like: <a href="https://github.com/fabioperez/space-invaders-vhdl" rel="nofollow noreferrer">https://github.com/fabioperez/space-invaders-vhdl</a> without an FPGA, such that:</p>
<ul>
<li>signals are set by keyboard keys</li>
<li>outputs can be displayed on a window</li>
</ul>
<p><a href="http://www.nand2tetris.org/" rel="nofollow noreferrer">http://www.nand2tetris.org/</a> does this, but is uses a simplified custom educational language for it.</p>
<p>VHDL's <code>textio</code>'s <code>read(input</code> and <code>write(output</code> get somewhat close, but not quite:</p>
<ul>
<li><code>read(input</code> waits for a newline, we'd want something that can detect is a keyboard key is pressed or not</li>
<li><code>write(output</code>: would need some way to flush data to ensure that the renderer that will emulate, say, a display gets it</li>
<li>we need some way to throttle simulation speed</li>
</ul>
<p>Of course, I don't need to do everything in VHDL: I just need a minimal way to communicate with VHDL synchronously with other programs, and then I can do the e.g. display with SDL in C.</p>
<p>Also asked at: <a href="https://github.com/tgingold/ghdl/issues/92" rel="nofollow noreferrer">https://github.com/tgingold/ghdl/issues/92</a></p>