VHDL - Testbench internal signals
<p>I am spending some time learning about writing test benches to try out on some of the models I have produced. Does anyone know a way to monitor signals that are internal to the architecture of the unit under test. I have tried using </p>

<pre><code>LIBRARY MODELSIM_LIB;
USE MODELSIM_LIB.UTIL.ALL;
    spy_process : process begin
        init_signal_spy("Q4/C1/A1/chip_sel","/chip_sel",1);
        wait;
        end process spy_process;
</code></pre>

<p>But I get a compiler error of the :</p>

<blockquote>
  <p>Error (10481): VHDL Use Clause error at Q4.vhd(15): design library "MODELSIM_lib" does not contain primary unit "util"</p>
</blockquote>

<p>I've checked the Quartus II library folder and util is there in the correct place.
Any suggestions?
Thanks D</p>