How to write SDC timing constraint an encrypted verilog code?
<p>I have received a verilog project, with a key component in it being encrypted. </p>

<p>The performance on a FPGA varies depending on build environment and configuration[Note 1] and I suspect this is caused by insufficient timing constraints [Note 2].</p>

<p>In the TimeQuest timing analyzer I can see the names of the pins, nets, registers, ports within the encrypted core, but without looking at the actual code I don't know exactly what they mean.</p>

<p>So how should I start writing a SDC timing constraint in this situation?</p>

<hr>

<p>Note 1:</p>

<p>The component is a MIPI-CSI2 TX. On the test RX side I constantly get SoT error(SoT error and sync not achieved), and sometimes ECC errors.</p>

<p>For a while, to make it "work" on an FPGA the code has to built on a Windows Machine. Then a few minor and unrelated changes are made to the code, it could work if built on a Linux machine. Then very recently a Linux build machine seems to perform better than a Windows machine.</p>

<p>Also changing optimization parameters seems to break the code very badly. E.g. currently only "Balanced" mode works. "Performance" and "Aggressive Performance" modes, which should improve performance, causes a lot of errors in the received signals. Memory contents of a upstream signal processing block also affect the MIPI-CSI2 TX this way.</p>

<p>Above all make me think there are some uncertainties not fully constrained by the SDC timing constraints.</p>

<hr>

<p>Note 2:</p>

<p>I'm not able to fully verify this theory because I don't have the equipment to fully test signal, nor could I do gate-level simulation because the encrypted code does not allow me to generate EDA netlist.</p>