Generate random enum using system Verilog
<pre><code>typedef enum int { IPV4_VERSION = 0, IPV4_IHL = 1, IPV4_TOTAL_LENGTH = 2,IPV4_CHECKSUM = 3 } ipv4_corrupton;

ipv4_corrupton ipv4_corrupt;

std::randomize(ipv4_corrupt) with {ipv4_corrupt dist { IPV4_VERSION :=2,IPV4_IHL := 4,IPV4_TOTAL_LENGTH := 4,IPV4_CHECKSUM := 2}; };
</code></pre>

<p>I ran the above code 10 times and always got <code>IPV4_CHECKSUM</code>. I am making any mistake? </p>