Port mapping sub elements of array in specific order in VHDL?
<p>So, I am writing a wrapper for a component. The component has some input in form of array like</p>

<pre><code>-- Definition in the original component
array_1 : out std_logic_vector (1 downto 0);
array_2 : out std_logic_vector (1 downto 0);
</code></pre>

<p>I am trying to assign sub elements of array in port map as</p>

<pre><code>-- All foo1, foo2, bar1, bar2 are defined as output std_logic in wrapper port list
array_1 (0) =&gt;   foo1,
array_2 (0) =&gt;   bar1,
array_1 (1) =&gt;   foo2,
array_2 (1) =&gt;   bar2,
</code></pre>

<p>The above produces an error like: formal association is made more than once</p>

<p>But weirdly, the following compiles fine.</p>

<pre><code>array_1 (0) =&gt;   foo1,
array_1 (1) =&gt;   foo2,
array_2 (0) =&gt;   bar1,
array_2 (1) =&gt;   bar2,
</code></pre>

<p>Am I missing something, I can't find anywhere that the sub elements of an array have to be associated together but I can't find an example in which they are not. I know I could just do the latter but I am curious. Any help would be appreciated. </p>

<p>BTW, this is a short example I made up... the original code has over 50 elements but I have narrowed the problem to this. Thanks for any help or suggestions.</p>