aamod bhagwat
Design Verification Engineer at Apple
design verification engineer apple
ip verification engineer apple inc .
Apple
https://www.linkedin.com/company/apple
Working as a DV engineer functionally verifying Apple IPs using System Verilog and UVM methodologies
Austin, Texas Area
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Design Verification Engineer
Qualcomm
https://www.linkedin.com/company/qualcomm
Working as SoC/chip level verification engineer on the next generation Server SoC at Qualcomm Data Center Group, Raleigh. 
System level interconnect integration verification of the ARM/PCIe coherent bus architecture of QDT's first commercial server SoC Centriq2400. 
Experience in System level verification, test planning, System Verilog & UVM methodology driven verification, constraint random stimuli, Perl scripting, TestPlan/Regression management using Splunk/other EDA tools, and Defect management using in-house Bugzilla software.
Experience in closing SV Functional Coverage at chip level.
Well versed with AMBA3 AXI and AHB Bus Protocols
Verification of multi-die SoC architecture where two dies are connected via an in-house FLIT interface
Raleigh-Durham, North Carolina Area
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Senior Engineer
Qualcomm
https://www.linkedin.com/company/qualcomm
Verification of core level design using UVM and Formal verification methodologies. Actively involved in test planning, test development/debug and toggle coverage closure. Used Jasper formal tool for running large test suites. 
Member of Bus/Interconnect Integration team that verifies the bus infrastructure on a chip. Exposure to several VIP bus protocols like AHB, AXI etc. Actively involved in closing functional coverage on buses. 
Experience in Jasper based formal bus certification flow to qualify the protocol compliance of any interface using System Verilog assertions and cover properties
Raleigh-Durham, North Carolina Area
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SoC Verification Engineer
TATA Power Co. Ltd
Biometric Security System and Data Logging
          Designed a fingerprint based access control system using PIC18F452 and PIC18F252 microcontrollers.
          Implemented remote wireless data logging through ZIGBEE ­ a wireless data transfer module.
          Used FIM30N fingerprint module and XBee trans-receiver module.
          Simulated Real time clocking via DS1307and LCD interfacing with control boards.
Project Trainee
Masters
Focus on Computer Architecture and ASIC Design-Verification.
Coursework in ASIC Verification,  ASIC design, Computer Design, Advanced Micro-Architecture, Architecture of Parallel Computers, DSP, Embedded Systems RTOS
Efficient in C, C++, Verilog, System Verilog OOPS programming, VHDL
Computer Engineering
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North Carolina State University
https://www.linkedin.com/school/north-carolina-state-university/
Bachelor of Engineering (B.E.)
Bachelor of Electronics Engineering.
Coursework in MicroComputer System Design, Embedded Systems, Computer Organization, Digital Design, Control Systems
Electronics Engineering
K J Somaiya COE, University of Mumbai
Primary and Middle School
VPM Eng Med School
ASIC Design
ECE 520
ASIC Verification
ECE 745
Advanced Computer Design
ECE 785
Advanced MicroArchitecture
ECE 721
Architecture of Parallel Computers
ECE 506
Computer Design and Technology
ECE 521
Computer Networks
ECE 570
Digital Signal Processing
ECE 513
Embedded Systems
ECE 561
Computer Organization
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Digital System Design
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Embedded Systems and Real Time Programming
ECE 561
Microcomputer System Design
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Built several misprediction recovery techniques on the FabScalar Simulator (Prof Eric Rotenberg, NCSU), involving different processor structures. Developed an aggressive Eager Misprediction Recovery scheme on the simulator and studied its benefits. Comparison amongst the recovery approaches based on simulations on several benchmarks (gcc, gzip, go etc.), adding few dimensions to the simulator to study the effect on branch recovery in terms of recovery cycles.
Efficient Branch Misprediction recovery in Out-Of-Order Superscalar Processor
Verifying data and control path of a pipelined LC-3 microcontroller developed at NCSU.
Developed a reusable and layered test-bench in System Verilog to test all the features of LC-3, with the help of assertions, clocking blocks etc.
Maximum coverage achieved through valid coverage points and cover groups.
Data and Control path Verification of Pipelined LC-3 micro-controller - ASIC Verification
Studying the benefits of Logic-On-Logic 3D Integration and placement and extending it on to several technological processes like 130 nm, 45 nm, etc.
Taking up RTL design and doing detailed Synthesis using Synopsys Synthesis tools, doing a 2D place and route using Cadence Encounter tool.
Performing Static Timing Analysis using Synopsys PrimeTime environment, partitioning the design using sHmetis tools and performing 3D trial placement on Bottom and Top halves of the design.
45 nm 3D Place and Route study
Implemented stopwatch on RL78 board. Analyzed the performance and optimized energy and power consumption through various software and hardware optimization techniques..
Energy Optimization and Performance improvement on an RL78 Development kit
Developed a packet forwarding engine in Verilog RTL using a compression technique algorithm.
Built a hierarchy model and interfaced SRAM and DRAM for fast address lookups. Performed Synthesis and Functional Verification using ModelSim on the developed model. 
Built a high level Digital Design System and programmed the routing model in Verilog HDL.
Packet Routing Engine - ASIC Design
Developed two simple timer applications on the RL78 development kit. Modeled a Race Condition between the two tasks by using the common resource as the on board Graphics LCD.
Using RTOS concepts, inserted semaphores to avoid the race condition.
Synchronization using RTOS and Semaphores
Developed an interactive game using the RL78G13 Microcontroller.
Used the on-board accelerometer and Graphics LCD. Microcontroller and the related peripherals were coded in C programming language.
Run time profiling and optimization was conducted on the application developed, improving its performance and speed
Interactive Game Development and Run time optimization
Simulated an out-of-order super-scalar processor. Implemented dynamic instruction scheduling in C programming language
The pipeline was studied for various configurable parameters
Instruction Level Parallelism using Tomasula's algorithm
Cache coherence protocols like MSI, MESI and MOESI were built on a symmetric multiprocessor system with single level caches. It involved programming in C++ and tested the concepts of a multi-processor environment and the cache hierarchy behaviour
Cache Coherence Protocol on Symmetric Multiprocessor system
Designed a dynamic branch predictor for simulating Bimodal, Gshare or Hybrid branch predictor. Analysis was done studying the branch miss prediction rates - Project included C programming
Dynamic Branch Predictor
Designed a flexible 2 level cache simulator in C language and studied  the memory hierarchy performance using the SPEC Benchmarks. Configurable parameters included cache size, block size and associativity
Generic Cache Simulator and Memory Hierarchy
The project done under TATA Power Co. Ltd. involved developing a biometric security system using PIC microcontroller and FIM30N fingerprint scanner. Remote data logging was implemented using a wireless data transmission tool called ZIGBEE. Involved Embedded C programming and X-CTU software coding
Biometric Security System and Data Logging
Execution driven timing and functional simulator for superscalar processor. developed the debug buffer interface for decoding the instructions and collecting statistics for the simulator.
Exercised an ILP Limit Study using SPEC2K benchmarks achieving an ILP of 6-8 for real branch predictions
ILP Limit Study for a Superscalar processor on a Simplescalar toolset
https://www.linkedin.com/in/minaltekade
San Francisco Bay Area
Minal Tekade
Design Verification Engineer
https://www.linkedin.com/in/abhjosh2
Raleigh, NC
Abhishek Joshi
CPU Verification Engineer at Apple
https://www.linkedin.com/in/stella-ma-58201163
San Francisco Bay Area
Stella Ma
SoC Verification Engineer at Apple
https://www.linkedin.com/in/ramapriya-namo-achyutha-70325019
Austin, TX
Ramapriya Namo Achyutha
Senior Staff Engineer at Qualcomm
https://www.linkedin.com/in/geetika-agrawal
San Jose, CA
Geetika Agrawal
Soc Verification Engineer at Qualcomm
https://www.linkedin.com/in/gomathinayagam-balasubramanian
Morrisville, NC
Gomathinayagam Balasubramanian
Senior Hardware Design Engineer at Microsoft
https://www.linkedin.com/in/shruthiravishankar
Raleigh, NC
Shruthi Ravishankar
Incoming GPU Verification Intern at Nvidia | Computer Engineering Graduate Student at NC State University | Ex- Design Verification Engineer at Qualcomm
https://www.linkedin.com/in/iyerbala
San Francisco Bay Area
Bala Ramakrishnan
Senior Engineer at Apple
https://www.linkedin.com/in/suneetsasidharan
Seattle, WA
Suneet Sasidharan
Senior Software Engineer at Microsoft
https://www.linkedin.com/in/ravihbhatt
Cupertino, CA
Ravi Bhatt
Senior Engineering Program Manager at Apple
https://www.linkedin.com/in/keithxm23
Boston, MA
Keith Mascarenhas
Senior Software Engineer II Lead at Akamai Technologies
https://in.linkedin.com/in/hemant-singh-chauhan-48b94442
Rajsamand
Hemant Singh Chauhan
Associate manager (Electrical) at HZL Vedanta
https://in.linkedin.com/in/akash-pasa
Bhubaneshwar
Akash Pasa
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TATA POWER
https://in.linkedin.com/in/madhu-muthu-90a60922
Greater Chennai Area
Madhu Muthu
XMIB-GE, Ex-Schneider-Electric
https://ca.linkedin.com/in/karim-khordoc
Greater Ottawa Metropolitan Area
Karim Khordoc, Principal Eng. and Tech. Lead, ASIC
Principal Engineer, Formal Methods at Oski Technology, Inc.
https://in.linkedin.com/in/mohammad-imran-181910164
Dhanbad
Mohammad imran
Lead Engineer
https://www.linkedin.com/in/anandsahoo1008
San Francisco, CA
Anand Sahoo
MSBA Student at UC Davis
https://www.linkedin.com/in/chaudharynitin
Cupertino, CA
Nitin Chaudhary
Design Verification Engineer at Apple
https://www.linkedin.com/in/bhavesh-battiwala-b0202a2b
San Diego County, CA
Bhavesh Battiwala
Senior Staff Modem Design Verification
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📍HOME.NC State has been named one of the most beautiful urban college campuses of 2022 by College Consensus.
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India plans a ₹76,000-cr red carpet for semiconductor companies
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To my past, present and future mentors, managers, colleagues and also to my friends - Thank You for your support! Wishing you and your family a…
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Maharashtra, India
Aamod Bhagwat
Sub Divisional Engineer at Bharat Sanchar Nigam Limited
Qualcomm: Alumni
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