aaron arena
Applications Engineer at Intel Corporation
application engineer intel psg
application engineer intel psg . hands-on project orientated person , strive create innovate . continually trying learn expanded technical background . technical skill : - specialty : fpga configuration , partial reconfiguration ( pr ) , video protocol ( e.g . displayport , hdmi ) , xcvr's - tool : quartus , unity - hdl : verilog , vhdl - programming : python , c , c # , c++ , assembly , javascript , html , cs - framework : electron , sfml
Intel Corporation
https://www.linkedin.com/company/intel-corporation
MAG Team (Nov. 2019 - Present)
- Provide customer support regarding FPGA Design and Debug Tools, IP, I/O, and Documentation
   - Specialty Support Areas: Configuration, Partial Reconfiguration (PR), Video (i.e. DisplayPort)
- Mentor Interns and Emerging Professionals in Rotation Program to develop technical capabilities and offer guidance along career path
 

Rotation Program (Jun. 2018 - Oct. 2019)
* New User Experience Group
   - Organized Training Material and Workshop
   - Created an Intro to Video Workshop using VGA on a Terasic DE10-Lite w/ MAX 10 FPGA
   - TA'ed and taught workshops to local universities
   - Revamped the upload process the Intel Design Store (Intel's online repository for FPGA Designs)

* Regional Applications Engineering (RAE)
   - Provided technical support related Quartus and Design Tools, Configuration, I/O and Documentation for customers

* Native PHY (Design) Programmable IP Engineering (PIPE)
   - Built a CSV translation tool in Python to accelerate IP development in Perforce
San Jose, CA
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Applications Engineer
Hewlett Packard Enterprise
https://www.linkedin.com/company/hewlett-packard-enterprise
American multinational enterprise information technology company that focuses on providing businesses with server, storage, and networking solutions

Job Duties:
•	Setup a test to evaluate the signal integrity and performance of a PCIe Ethernet switch 
•	Compiled and updated guides to use a cross-referencing tool within Cadence
•	Designed a net name symbol parser to aid in building custom symbol blocks inside of 
        Cadence schematics
Roseville,CA
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R&D Hardware Design Engineer
Kipkay Kits
Online-based company that designs do-it-yourself (DIY) projects to educated and expanded people’s knowledge about engineering and electronics while yielding valuable hands-on experience

Job Duties:
•	Designed, prototyped, and built small DIY electronic projects for kids and hobbyists  
•	Developed assembly instructions and customer service protocols for each project
Culver City, CA
Lead Hardware Engineer
Master of Science - MS
Electrical Engineering
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California Polytechnic State University-San Luis Obispo
https://www.linkedin.com/school/california-polytechnic-state-university-san-luis-o/
Bachelor of Science - BS
Electrical Engineering
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California Polytechnic State University-San Luis Obispo
https://www.linkedin.com/school/california-polytechnic-state-university-san-luis-o/
Cal Poly Rugby Club
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Consumer Electronics Society
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IEEE
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Radio Waves, Microwaves, and Photonics
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Causal 3D Physics-based Puzzle Platformer

Built in one week using Unity
Fun with Physics
https://aaron7eleven.itch.io/fun-with-physics
Video game submission for GMTK Game Jam 2020

Built in 3 days using Unity
Speed
https://aaron7eleven.itch.io/speed
A compiler that accepts software (e.g. C) and returns a combination of software and HDL (e.g. C and Verilog) that represents a fully functional SoC Design

•	Integrated the Tabu Search + Simulated Annealing (TSSA) and Genetic Search (GS) partitioning algorithms into a Cal Poly Designed Heterogeneous Compiler: Twill

•	Implemented resulting SoC design with Xilinx ISE and Xilinx SDK on a Virtex 5 FPGA with a Microblaze softcore processor

•	When using a Sobel Filter as the stimulus with a problem size ranging from 49 to 32,400 and comparing the SoC design with the original partitioning algorithm (Knapsack 0-1),
o	the TSSA partitioned SoC designs gained a performance boost between 38.3 % and 56.5 % while using between 2.4 % and 8.8 % less energy
o	the GS partitioned SoC designs gained a performance boost between 46.6 % and 113.6 % while using between 10.3 % and 46.8 % less energy
Heterogeneous Compiler
Designed, prototype, and built a portable USB phone charger using a pre-designed boost converter and Lipo battery charger module and a 3.7 V Lipo Battery
Portable Phone Charger
A CPU designed in VHDL to run assembly programs on a Diligent Nexys 2 board and Digilent Basys 3 board

•	Improved processor by changing architecture into 5 stage pipeline MIPS architecture to improve performance and parallelism 

•	Added a 2-bit saturated counter branch predictor to improve performance and decrease branch stalls

•	Added a 176B four way set associative cache to emulate real world scenarios
RAT CPU
A filter that contains an edge detection algorithm that applies a 2D convolution on an image or video

•	The filter was implemented on Digilent Basys 3 FPGA using Vivado IDE

•	The goal was to compare the Sobel filter runtime using a hardware (Verilog) and software (C) implementation

•	The hardware provided a 35 % speed up compared to the software
Sobel Filter Hardware Accelerator
Aimed to aid in building custom symbol blocks inside of Cadence schematics
Net Name Symbol Parser
Labview designed automated system to check given specs (such as PWM) of an Arduino Uno
Arduino Specifications Checker
Allows user to see and feel music they are listening to

● This system was composed of the Digilent Zybo board, coin cell motors, LED's and a RTOS (freeRTOS) using Vivado and Xilinx SDK as the dev tools

● The user inputted a music (via headphone jack) to an on-board audio codec on Zybo board and send the audio data (via I2C) to the RTOS

● Inside of the RTOS, a FFT and Peak Detection were done on the audio to gather the peak frequency data

● The frequency data was sent back to the FPGA to output to the external LED's and motor to blink and vibrate, respectively, with each LED and motor combo corresponding to a certain frequency
Audio Feeler & Visualizer
Measures the lights brightness, light brightness information is transmitted to Arduino Uno and displayed onto an LCD screen
Luxmeter
Listens for ambient noise in a quiet setting, detects loud noises (e.g. snoring), and triggers an alarm to wake the person snoring

● The snore detector was comprised of an Arduino Uno, a Sparkfun microphone, an Adafruit 8 x 8 LED Matrix, a buzzer, and a DC motor

● The microphone would gather the raw audio data and send it Arduino to see if the audio is loud enough to be snoring

● The Arduino would send the audio data (via I2C) to the LED Matrix to visualize the audio data

● Once the Ardunio detected three instances of snoring, it would trigger the buzzer to sound, the motor to vibrate and the LED matrix to blink in order to wake the person up
Snore Detector
A dual 20 V (30 W) power supply. Assembled as a part of the class: IME 156.
DC Power Supply
Education
Intel Innovators
Intel Innovators is a chapter of Toastmaster International based in San Jose

- Manage membership dues
- Set up bank account for club
- Volunteer Roles in Speaking Contests
Treasurer
Education
Intel Latinx Network (ILN)
- Lead events to help develop skill, such as Leadership and Networking, in career
- Get feedback on where and how people want to grow
- Volunteer to help with internal development conferences
Professional Development
Education
IEEE Consumer Electronics Society
https://www.linkedin.com/company/ieee-consumer-electronics-society
o	Designed, prototyped, and built a portable USB phone charger
	Allow club members to build project that supplemented existing technology
	Created a source of income for the club

o	Marketed and planned hands-on workshops
	Posted flyers, sent event invites via email and posted on Facebook
	Provided tools and personal expertise to help club members build the phone charger or teach them how to solder
Project Head
Cal Poly Rugby
Processed paperwork for team eligibility and travel
Vice President of Away Games
Radio Waves, Microwaves, and Photonics
Planned external social events and booth for Cal Poly's EE Open House
Social Coordinator
https://www.linkedin.com/in/marjorie-catt-b749b511
San Jose, CA
Marjorie Catt
High Speed Analog Applications Engineer at Intel Corporation
https://www.linkedin.com/in/yucheng-wang-a25607a3
Milpitas, CA
yucheng wang
Intel - Application Engineer
https://www.linkedin.com/in/benjamin-reynolds-666a28b7
San Jose, CA
Benjamin Reynolds
Application Engineer at Intel Corporation - Programmable Solutions Group
https://www.linkedin.com/in/bret-gustafson-695368173
San Francisco Bay Area
Bret Gustafson
Application Engineer at Intel Corporation
https://www.linkedin.com/in/joel-hernandez-ba3397197
McAllen, TX
Joel Hernandez
Applications Engineer at Intel Corporation
https://www.linkedin.com/in/mathias-berglund-592b30132
San Jose, CA
Mathias Berglund
Application Engineer at Intel Corporation
https://www.linkedin.com/in/aracelymejia
San Jose, CA
Aracely Mejia
PSG Application Engineer at Intel Corporation
https://www.linkedin.com/in/shawnnac
Greater Seattle Area
Shawnna Cabanday
Application Engineer at Intel Corporation
https://www.linkedin.com/in/jaewon-seo-2517a56
Dublin, CA
JaeWon Seo
IP Design Engineer at Altera
https://www.linkedin.com/in/deepika-ganju-67436789
Austin, Texas Metropolitan Area
Deepika Ganju
Application Engineering Manager at Intel
https://www.linkedin.com/in/neehar-jandhyala-6034284
San Jose, CA
Neehar Jandhyala
Physical Design Engineer at Intel Corporation
https://www.linkedin.com/in/susan-cohen-977560177
Austin, Texas Metropolitan Area
Susan Cohen
Application Engineer, Acceleration at Intel Corporation
https://www.linkedin.com/in/cathy-nguyen-b0b9711b0
Austin, TX
CATHY NGUYEN
Server Validation Engineer at Intel Corporation
https://www.linkedin.com/in/anil-godbole-76ab555
Cupertino, CA
Anil Godbole
FPGA IP Marketing Manager at Intel Corporation
https://www.linkedin.com/in/prasad-reddy-5197553
San Jose, CA
Prasad Reddy
Field Applications Engineering Management - Intel Corporation
https://www.linkedin.com/in/djnielsen
San Francisco Bay Area
Daniel Nielsen
PSG Rotation Program at Intel Corporation
https://www.linkedin.com/in/janpreet
New York City Metropolitan Area
Janpreet Singh
DevOps Engineer at Unqork
https://www.linkedin.com/in/apurva-gandole-887aa775
Mountain View, CA
Apurva Gandole
Applications Engineer Sr l at Synopsys Inc
https://www.linkedin.com/in/prasadmayank
Tempe, AZ
Max Prasad
Entrepreneur & Computer Engineer
https://www.linkedin.com/in/niletronics
Redmond, WA
Nilesh Dattani
Senior Hardware Engineer at Microsoft
https://www.linkedin.com/in/aaron-arenas-a3a119b8
United States
Aaron Arenas
general manager at Emergency Restoration specialist Corp.
https://pa.linkedin.com/in/aaron-arenas-501ab473
Panama
Aaron Arenas
Mecánico y operador de Grúas Porticas en Manzanillo International Terminal
https://aw.linkedin.com/in/aaron-arenas-a73b091b4
Oranjestad
Aaron A. Arenas
Senior student at Colegio E.P.I. unit Economia in specialisation Tourism Administration
https://cl.linkedin.com/in/julio-aar%C3%B3n-arenas-leon-934524b0
Valparaíso
Julio Aarón Arenas Leon
Asesor Ssoma   en Incolur