aakash verma
Staff Emulation Engineer - Barefoot Networks Division at Intel Corporation
emulation / design verification engineer | ex-marvell | usc alumnus
electrical engineer extensive experience spanning emulation soc pre-si verification targeting functional & power verification . • skilled emulation tool , flow methodology hw verification sw/firmware development . • adept uvm , object-oriented systemverilog , verilog , verdi , dve , eclipse dvt , c++ , testbench architecture working knowledge python . • experienced digital rtl design & micro-arch specification , low-power methodology , chipset soc architecture involving multiple low/high speed i/os .
Intel Corporation
https://www.linkedin.com/company/intel-corporation
San Francisco Bay Area
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Staff Emulation Engineer - Barefoot Networks Division
Marvell Semiconductor
https://www.linkedin.com/company/marvell
Working on Emulation and FPGA Prototyping technologies for ThunderX family of ARM processors in Server Processor Business Unit focusing on Cadence Palladium platform.
San Francisco Bay Area
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Staff Design Verification Engineer - Emulation
Intel Corporation
https://www.linkedin.com/company/intel-corporation
•	Responsible to verify functional and power-saving features at IP & SoC level for multi-generation Platform Controller Hub (PCH) Chipset SoC targeting Server, IOTG, PC and mobile markets.
•	Developed test-plans, test cases in UVM/System Verilog, SV assertions & functional coverage to check design compliance with the architectural specs for various blocks at SoC like PLLs, PHYs, Voltage Regulators, and Clocking Unit to meet power targets. 
•	Verified reset/boot-up flows at SoC and protocols like USB, SATA, PCIE, GBE at interface level on a partition-based UPF SoC model with multiple voltage rails and power domains.
•	Developed and modified existing testbench components like monitors, scoreboards, interfaces and overall environment.
•	Lead TR (technology readiness) activities for a future project namely feature evaluation, project scoping and resource distribution. Contributed exhaustively in verification enhancement primarily stub-modeling.
•	Devise new capabilities and enhance existing for HW/SW components like testbench DPI transactors, runtime software in System Verilog/C++ and integrate them with the emulation model for streamlined testing and verification of the RTL.
•	Developed system-level emulation (SLE) models for IPs (Memory Controller, PCIE) targeting Datacenter SoCs on Synopsys ZeBu (ZSE) Platform and drive the enablement with focus on clocks and reset.
San Francisco Bay Area
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Senior Design Verification Engineer (SoC Pre-Si and Emulation)
Intel Corporation
https://www.linkedin.com/company/intel-corporation
•	Responsibilities included developing RTL for performance features for the Instruction Decode Queue in the Front-End (FE) Cluster for 10nm Intel Core CPU that involves coordinating the efforts between RTL, validation and circuit design teams. 
•	Lead the Formal Equivalence Verification (FEV) – Syn2sim for the Front-end cluster.
San Francisco Bay Area
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Microprocessor Logic Design
Intel Corporation
https://www.linkedin.com/company/intel-corporation
•	Developed various Quality Assurance (QA) checks & Automation Scripts in PERL to automate Standard Cells, Parasitic Extraction Flow and Auto Place and Route (APR) Flow for the next-generation SSD memory.
•  Developed GUI for Parasitic Extraction Netlisting (StarRC) using SKILL scripting language for Cadence that is included with the existing options in Virtuoso IC 6.1.5 (Open-Access).
Sacramento, California Area
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Component Design Engineer (CAD Engineer Intern)
University of Southern California
https://www.linkedin.com/company/university-of-southern-california
Managing the inventory database at Housing Office and directly dealing with the Manager.
Greater Los Angeles Area
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Student Worker at USC Housing
Physical Research Laboratory
https://www.linkedin.com/company/physical-research-laboratory
Project: Iodine Cell Temperature Control System

• Built the microcontroller (Atmega 16) based hardware system monitoring and maintaining the ambient temperature by switching the heater around the Iodine Cell, used in the optical arrangement of sky observation.
• It was part of PARAS, India’s first exo-planet search program and stationed at Mt.Abu Observatory, India.
Ahmedabad, Gujarat, India
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Project Trainee
Masibus Automation
https://www.linkedin.com/company/masibus-automation
Worked upon the basic aspects of MSP430 microcontroller by Texas Instruments, incorporated by Masibus in the RTU (Remote Terminal Unit) of the project funded by Siemens Ltd. India.
Ahmedabad Area, India
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Trainee
Masters of Science (M.S.)
Electrical Engineering (Digital VLSI and Computer Architecture)
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University of Southern California
https://www.linkedin.com/school/university-of-southern-california/
B.E
Electronics and Communication
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L.D College of Engineering - Ahmedabad
https://www.linkedin.com/school/l.d-college-of-engineering---ahmedabad/
Recognized to shift left the power validation by 1 milestone on next generation Chipset
Intel Corporation
Department Impact Award
Was recognized for the efforts towards Pre-Si Verification for next generation Platform Controller Hub (PCH) SoC that facilitated early Post-Si debug.
Intel Corporation
Division Recognition Award
University of Southern Califormia
Viterbi Graduate Mentor 2012
Computer System Organization
EE457
Computer Systems Architecture
EE557
Digital Systems Design: Tools and Techniques.
EE560
MOS VLSI Circuit Design
EE477L
Solid State Processing and Integrated Circuits Laboratory
EE504L
VLSI System Design
EE577b
VLSI System Design.
EE577a
• The controller designed in Verilog will provide a simple FIFO based front-end that would support write/read transactions like scalar and block

• Designed the initialization engine as a part of the controller at 250MHz for 512Mb DDR2 SDRAM, keeping in mind the CAS & Additive Latency, ODT (On Die Termination), Burst Length, Precharging to perform scalar & block Read/Write operations.

• Designed the processing logic to handle data and command transactions via SSTL interface between Memory and Controller. 

• JEDEC DDR2 SDRAM Standard (JESD79-2C) is referred for all timing, bus interface and initialization specifications. 

• Delay Optimizations by performing Static Timing Analysis and set-up/hold check with extracted RC after Place & Route
Design (Verilog),Synthesis and Layoyut of DDR2 SDRAM memory controller
•  RTL Coded the same 4-stage hardware in Verilog mentioned previously to soothe out the image pixel.
•  It was simulated by Cadence NCSim.
Digital Image Uniform Noise Reduction (RTL)
• Synchronous and Asynchronous FIFO design using n and (n+1) pointers, width & depth expansion mechanisms of FIFO and
VHDL implementation, debouncing, gated clocking implementation.
• Wave Pipelining, PCI Bus Protocol, Synchronous SRAM & DRAM, SDRAM Controller, Initiator & Data Stationary control
design for non-linear pipeline, Content Addressable Memory (CAM).
• State Machine Design, Processor Architecture/Logic Design, Timing Analysis and Timing Constraints in Xilinx using VHDL,
Slack borrowing and Time Stealing, Code Coverage Analysis in ModelSim.
• Virtual I/O & File I/O using Xilinx USB/EPP (Enhanced Parallel Port) interface to FPGA board, DFT. Some of the above
concepts were implemented in VHDL for which testbenches were also coded.
Digital Design Concepts
• RTL Coding and design of 32-bit, 25Mhz OoO Processor using VHDL, inclusive of speculative execution and branch prediction. Included designing of various modules like Branch Prediction Buffer (BPB), Re-order buffer (ROB), Address Buffer, Store Buffer, Issue Queue (IQ), Load Store Queue (LSQ), Copy-free-checkpoint (CFC), Physical Register File (PRF), Free Register List (FRL), Dispatch Unit and Issue Unit 
• Testing by various instruction streams & testbenches and synthesis on Spartan-6 FPGA.
• Tools: Xilinx ISE Design Suite 13.2 and Modelsim 10.1a.
“Tomasulo Algorithm” based Out-of-Order (OoO) Execution Processor design using VHDL, synthesis and implementation on Spartan-6 FPGA.
• Designed and implemented a fully associative cache capable of catering 8, 16-bit words on Spartan-6 FPGA.
• LRU (Least Recently Used) mechanism was used to update the entries from a main memory emulator.
• Tools: Xilinx ISE Design Suite 13.2 and Modelsim 10.1a.
Cache Design on FPGA.
• Designed schematic & layout of a pipelined noise reduction hardware using adders and 1024-bit SRAM memory to sooth the image pixel based consulting the neighbouring pixels. This noise reduction algorithm implemented was simplified version of “Averaging Algorithm” and the concepts applied were Finite State Machine Design, Logical Effort and Pipelining.
• The project included designing of Special Accumulator, Clock-Divider Circuits, Read/Write Control Logic & 16-bit Carry look-ahead adders as well.
• Tools: Cadence Virtuoso for schematic & layout and Spectre for simulation.
Digital Image Uniform Noise Reduction.
• Electrical Devices like MOSFET, Diodes, Capacitors and Resistors were fabricated on 3” silicon wafer at Powell Foundation Instructional Laboratory, USC using photolithography. Electrical characterization and analysis of the above active devices was carried out and different electrical parameters were calculated from the extracted data.
Solid State Processing and Integrated Circuits Laboratory.
• Designed the layout & schematic of 1024-bit SRAM, 16-bit word with bank interleaving of 2, each 32x16 bits wide while optimizing its area and delay. It also included designing Row Decoder Circuit to access the rows in SRAMs using the concepts of Logical Effort
• Tools: Cadence Virtuoso for schematic & layout and Spectre for simulation.
1024-bit 6-Transistor SRAM design.
• Built the schematic and layout of digital timer working in count up and countdown mode and successfully & verified the functioning by simulation as well as LVS and DRC checks.
• Tools: Cadence Virtuoso for schematic & layout and Spectre for simulation.
4-bit Digital Counter with countup and countdown mode and asynchronous reset.
• Designed a 5 Stage early branch Pipelined CPU datapath using Verilog and RTL coding and appropriate Forwarding Unit (FU) & Hazard Detection and Stalling Unit (HDU) to handle structural, data and control hazards.
5-Stage Pipeline MIPS Processor CPU Design using Verilog and RTL Coding.
https://www.linkedin.com/in/baosheng-wang-10ab654
Santa Clara, CA
Baosheng Wang
Design Verification Expert in Functionality, Structural, Power and Performance
https://www.linkedin.com/in/vishalshehrawat
San Francisco Bay Area
Vishal Shehrawat
Senior Staff Design Verification Engineer
https://www.linkedin.com/in/vinay-dave-3a75265a
San Francisco Bay Area
Vinay Dave
Staff Engineer at Qualcomm
https://www.linkedin.com/in/shashank-kulkarni-69244838
San Jose, CA
Shashank Kulkarni
SoC Design Engineer at Apple
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Fremont, CA
Henry Yang
Principal Firmware Engineer at Marvell Semiconductor
https://www.linkedin.com/in/nitinsharma3
Redwood City, CA
Nitin Sharma
Sr. Director, Engineering at Qualcomm
https://www.linkedin.com/in/vandit-mehra-7bb8916
San Jose, CA
Vandit Mehra
Staff GPU Performance Engineer
https://www.linkedin.com/in/prasun-kapoor-4083911
Fremont, CA
Prasun Kapoor
Senior Director Software Engineering  at Marvell Semiconductor
https://in.linkedin.com/in/kiran-maturu-baa607b
Bengaluru
Kiran Maturu
Senior Manager, Design Verification at AMD
https://www.linkedin.com/in/rachitkumar03
San Francisco, CA
Rachit Kumar
Staff Software Engineer at Uber
https://www.linkedin.com/in/alfredo-alvarez-1a179b9
Hillsboro, OR
Alfredo Alvarez
Debug Engineer at Intel Corporation
https://www.linkedin.com/in/srinivas17
Cupertino, CA
Srinivasa T A Pillai
Hardware Engineering Manager at Apple
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Mountain View, CA
sridharan madabhushanam
Director Applications at Synopsys Inc
https://www.linkedin.com/in/ruchikajaisinghani
San Francisco, CA
Ruchika Jaisinghani
Scientist at Aligos Therapeutics
https://www.linkedin.com/in/anjali-donaldson-b26b968a
San Francisco, CA
Anjali Donaldson
Global Operations Lead @Uber
https://www.linkedin.com/in/zakirhas
Greater Chicago Area
Zakir Hussain Abdul-Salam
Technology Leader at Humana
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Raleigh-Durham-Chapel Hill Area
Sruthi Bathina
Senior Design Verification Engineer at Marvell Semiconductor
https://www.linkedin.com/in/ravi-raj-40a15526
Santa Clara, CA
Ravi Raj
Staff Verification Engineer at Qualcomm
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Milpitas, CA
Saikishore Reddy Thiyyagura
Design Verification Engineer at NVIDIA
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San Diego, CA
Yuxuan Zhang
Design Verification Engineer
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Bangalore Urban
Aakash Verma 🇮🇳
Engineering at ShareChat ◉ Co-founder & Instructor at Innoskrit ◉ YouTuber (13k+ subs) at Innoskrit
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Pune
AAKASH VERMA
Mulesoft Consultant @ Infosys | Mulesoft Certified Developer |  Immediate Joiner | Open to Work
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Delhi, India
Aakash Verma
Team Lead: Automation & Technology at TP Central Odisha Distribution Limited
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Manesar
Aakash Verma
Sr.Engineer at skh metals ltd
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Bengaluru
Aakash Verma
Java Backend Developer | SDE I at Joyride Games | 2.5 YOE | Ex Subexian | Online Gaming | Telecom | NITCian at core
H1B Jobs
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VLSI ASIC  - Verification, Physical Designing - Bangalore
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USC - Silicon Valley
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VLSI Front End Job Vacancies
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The Semiconductor Jobs Network - Jobs in the Semiconductor Industry
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ASIC Integration, Verification & Validation
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Semiconductor Professional's Group
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ASIC, FPGA, SoC - Southern Cal and Southwest
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L.D.C.E. Alumni Association
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CISCO
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ASIC and FPGA Design and Verification Contract  Openings
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Semiconductor Startup
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Jobs In California
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Computer & Software Engineering Professionals
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