Adrian Patrascu
Verification and Validation Engineer at Qualcomm
Validation and Verification Engineer at Qualcomm
Qualcomm
https://www.linkedin.com/company/qualcomm
Centriq server SOC: Pre and Post Silicon Test Generation for ARM ISA 
• Developed and maintained a variety of ARM assembly level tests primarily used in Pre-SI simulation targeting multi-processor cache coherency, ordering, barriers, utilizing applications processors and DMA engine
• Co-developed a C language tool that incorporated multiple coherency tests and randomized core and memory usage, ran on pre-SI accelerators and emulators, and on post-SI bare metal hardware and on Linux.
• Wrote several randomized directed tests for cache coherency, ordering, and general cpu test using a proprietary test language developed in-house
• Contributed to pseudo-random instruction test generators
• Developed a bare metal test utilizing a random ISA test generator combined with cache-stressing tests to be run as a manufacturing test for cpu-cache interface and system bus
• Developed various python scripts used to support debug and test randomization
Austin, Texas Area
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Verification and Validation Engineer
IBM
https://www.linkedin.com/company/ibm
PPC Server Verification and Bringup Tool Lead 2008 - 2013
• Co-designed and developed a new test tool for power management, cache, and memory
• Lead 2 other remote developers in receiving specs, designing, executing,debugging tests
• Found 76% of exerciser “chip” level bugs on last processor, including power management,
pervasive, bus logic
• Included tests for cache coherency, bus bandwidth, powervirus, performance
• The tool was also used for chip characterization and manufacturing power sort
• Ran on pre-silicon AWAN accelerators, bare metal hardware, and OS-level (AIX/Linux)

PPC Server Architecture Validation Tool Lead 2005 - 2008
• Led a remote team of 7 for an existing test tool which used a built-in PPC architecture
reference model to intelligently generate pseudo-random instruction streams and check
results against the model.
• Applied architecture and micro-architecture knowledge to design tests to target processor,
cache, and memory
a) Processor focus included floating point number line, access ordering, address translation, multiprocessor and multi-thread interraction
b) Cache and memory focus included cache coherency, cache attributes, and storage model
• Ran on pre-silicon simulation models and on bare metal hardware

Test Development Engineer 2000 - 2005
• Designed and implemented several hardware exercisers focused on branch and data
prefetch units of the processor. Exercisers used a bare metal OS with no firmware to
interact directly with the hardware.
• Worked on a team to update an architecture model in a validation tool for new instructions
and processor features.
• Developed a Linux device driver to enable full machine state control under Linux for testing
Austin, Texas Area
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Test Development Engineer
Bachelor of Science (BS)
Electrical/Computer Engineering
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The University of Texas at Austin
https://www.linkedin.com/school/theuniversityoftexasataustin-/
https://www.linkedin.com/in/jayamcgee
Austin, TX
Jay McGee
Signal Integrity Engineer at IBM
https://www.linkedin.com/in/guillermosilva
Cedar Park, TX
Guillermo J Silva
Firmware Engineer at IBM | Power and Thermal Control Systems Specialist  | Research and Development
https://www.linkedin.com/in/rbgass
Austin, TX
Robert (Ben) Gass
Engineer at IBM
https://www.linkedin.com/in/allen-hall-74905680
Cedar Park, TX
Allen Hall
Microprocessor Design and Characterization at IBM
https://www.linkedin.com/in/joeldavidsonaustin
Austin, Texas Metropolitan Area
Joel Davidson
Senior Hardware Design Engineer
https://www.linkedin.com/in/connor-smith-51b0a2a4
Dallas, TX
Connor Smith
Staff Hardware Engineer at IBM
https://www.linkedin.com/in/hilary-ricky-69b86248
Austin, TX
Hilary Ricky
Functional Analysis Engineer at IBM
https://www.linkedin.com/in/jyoti-gupta-5b69b8163
Austin, Texas Metropolitan Area
Jyoti Gupta
CPU Design Verification Engineer at ARM
https://www.linkedin.com/in/justin-henspeter-01837b55
Rochester, MN
Justin Henspeter
Lead Senior Power Development Engineer
https://www.linkedin.com/in/sam-kirchhoff-19bb3672
Austin, TX
Sam Kirchhoff
POWER10 Core Post-silicon Functional Bringup Lead at IBM
https://www.linkedin.com/in/anabel-hernandez-75115519b
Austin, Texas Metropolitan Area
Anabel Hernandez
Manager - Power Series Hardware Development
https://www.linkedin.com/in/bryan-lloyd-6262b858
Austin, TX
Bryan Lloyd
CPU micro-architecture and RTL design
https://www.linkedin.com/in/inaquidelgado
Austin, TX
Iñaqui Delgado
.
https://www.linkedin.com/in/nathaniel-jarpa-87949b8
Wilsonville, OR
Nathaniel Jarpa
Software, Hardware QA Engineer, Project Manager
https://www.linkedin.com/in/lopezjorgej
Portland, Oregon Metropolitan Area
Jorge Lopez
System Validation Engineer | Non-Volatile Memory Solutions | Pre and Post-Silicon | Scrum Master | ATE Testing
https://www.linkedin.com/in/anandvignesh
Folsom, CA
Anand Vignesh Venkataraman
System Validation Engineer
https://www.linkedin.com/in/nidhi-sharma-5789a117
Chelmsford, MA
Nidhi Sharma
Principal Product Validation Engineer at Cadence Design Systems
https://www.linkedin.com/in/saimohan-kammila
Folsom, CA
Venkata saimohan Kammila
Senior Xeon Platform Validation Engineer at Intel Corporation
https://www.linkedin.com/in/vinaymarutimelgiri
Austin, Texas Metropolitan Area
Vinay Maruti Melgiri
CPU Core verification Engineer at Apple
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Neuschwanstein Castle in the SnowHohenschwangau, Southwest Bavaria.
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I'm thrilled to announce that I've joined McKool Smith's market-leading intellectual property practice as a Principal in its Houston office. The…
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https://uk.linkedin.com/in/adrianpatrascu
London
Adrian Patrascu
Project Manager, BA (Hons) Business Studies, MCIOB, MCMI
https://ro.linkedin.com/in/adrian-patrascu-221b16138
Bucharest, Romania
Adrian Patrascu
Freelancer
https://ca.linkedin.com/in/adrian-patrascu-4b7b1a41
Greater Edmonton Metropolitan Area
Adrian Patrascu
Director of Operations
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Bucharest
Adrian Pătraşcu
Global MarTech B2B Lead
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Bucharest
Adrian Patrascu
Enterprise Mobility Management Engineer at PwC
ARM Based Group
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Door64: High Tech Professionals
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Cockrell School of Engineering, UT Austin - Alumni and Current Students
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