aanchal sharma
Product Manager at Astera Labs
product manager astera lab
Astera Labs
https://www.linkedin.com/company/astera-labs
San Francisco Bay Area
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Product Manager
Intel Corporation
https://www.linkedin.com/company/intel-corporation
•	Strategic partner to VP/GM responsible for developing, managing, and evangelizing holistic business unit strategy
•	Managed Business Unit’s yearly Goals – Revenue, P&L, Product Margin, LRP
•	Lead business development for Platform security, responsible for growth and long/short term strategy of the market segment 
•	Built BU-wide view of the state of the business with narratives for executive consumption for the quarterly business reviews
•	Drove low-end product definition to successful scheduled roll out in alignment with Intel Xeon Platforms roadmap
•	Managed technical marketing & customer requirements (new features & devices) to support segment growth
•	Led prioritization and tradeoff decisions for Cloud Business product requirements (Silicon and IP)
•	Drove execution efforts to resolve supply shortages at CSPs by creating short term & long-term mitigation strategy
San Francisco Bay Area
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Strategic Business Development Manager | Chief of Staff & TA to VP/GM (Datacenter Business Division)
Intel Corporation
https://www.linkedin.com/company/intel-corporation
•	Delivered 15+ key design wins ($$$M) for a diverse set of customer accounts (Cloud, Enterprise, Embedded)
•	Trained customers in FPGA chip design, tools (Quartus Prime), Code Optimizations, Configuration, PCIe and EMIF
•	Developed system level reference designs for Intel’s FPGAs and Ips
•	Specialized in PCIe based acceleration cards – lead successful qualification efforts for OEMs and SIs
San Jose, California
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Senior Field Application Engineer
Intel Corporation
https://www.linkedin.com/company/intel-corporation
•	Trained Neural nets on GPUs and ran inference on FPGA, GPU and CPU to evaluate competitor’s inference solution
•	Provided feedback to the strategy office for decision making
•	Resolved customer issues in the areas of timing Closure, RTL -Optimizations, Configuration and Flash Interface
•	Created a configuration tool using TCL (add on to Quartus) to enable sales debug in the field
San Jose, California
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Applications Engineer
University of Florida
https://www.linkedin.com/company/uflorida
•	Explored applications to suit reconfigurable aspects of NOVO-G (FPGA based supercomputer) for National Science foundation funded CRI project 
•	Developed Lattice Boltzmann Kernel using VHDL and Verilog, data streaming through DMA interfacing

• Performed Simulations using modelsim and Signaltap to study behavioral flow of fluids
Gainesville, Florida Area
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Graduate Research Assistant
POWERGRID
https://www.linkedin.com/company/powergrid
Worked on substation automation system (SAS).
Gurgaon, India
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Intern
Metso
https://www.linkedin.com/company/metso
Gurgaon, India
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Intern
Master’s Degree
Electrical and Computer Engineering
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University of Florida
https://www.linkedin.com/school/uflorida/
Bachelor’s Degree
Electrical and Electronics Engineering
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PES University
https://www.linkedin.com/school/pesuniversity/
High School
85.2%
Delhi public school
IEEE
Student Member
University of Florida
Achievement Award Scholarship for New Engineering Graduate Student
PES Institute of Technology
Achievement Award of First Class with Distinction in the Coursework.
Central Board of Secondary Examination(CBSE)
Ranked amongst the top 0.1% of successful candidates in English Core at the national level
Advanced Analog Electronic Circuits
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Advanced Power Electronics
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Analog Electronic Circuits
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Digital System Design
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Embedded Systems
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Microprocessers and Micro-controller
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Power Electronics
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Advanced vlsi circuits and design
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Computer Architecture
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Computer vision
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Digital Image Processing
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Embedded Systems Seminar
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Mixed Signal IC test 1
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Parallel Computer Architecture
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Reconfigurable Computing
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VLSI Circuits and Design
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Wireless Communications
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Independent Study
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-￼Design and implementation of a low-power five stage pipelined MIPS-8 architecture using Verilog.
-Specialized 16 bit Instruction set architecture (ISA) Design
-Power Optimization done using Dual ALUs and clock gating up to 46%
-Synthesis and APR done using Design Vision and Encounter.
-LVS and DRC matched
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Low Power MIPS Processor
-Pedestrian detection application for the using HoG descriptor 
-Contrast improvement done using Contrast Limited Adaptive Histogram Equalisation (CLAHE)
-Pre-trained the SVM classifier used to identify the objects extracted by the descriptor
-implemented using Cuda and OpenMP
Pedestrian Detection using Parallel HoG on Tegra TXI SoC
•	Realized a customized circuit for 1D Time Domain Convolution.
•	Including DRAM DMA Interface, Convolution pipeline, Signal Buffer and Kernel Buffer.
•	with synchronization of data in different clock domains using Xilinx Vivado.
1D Time Domain Convolution on a Zynq processor based FPGA (ZedBoard) using VHDL.
•	Minimum transistor sizing was achieved by adjusting cell ratio(CR) and pull up ratio(PR).
•	The schematics, layouts and simulations were analyzed and evaluated.
•	Hold Stability, Read Stability and Write Stability (static noise margins), gate and diffusion capacitances, SRAM Cell and Core Area, read and write access time were recorded within desired and expected limits.
•	Layout design in Virtuoso, and meeting DRC and LVS constraints.
Design of a Synchronous 8x4 SRAM Core based on 0.25um TSMC Technology using Cadence Virtuoso.
•	The aim of this technique is to enhance the performance of Cache lines based on both frequency as well as the time based use.
•	The Cache line with the least score is evicted.
•	Scores are determined using an algorithm, currently used for ranking web traffic, which is based on exponential decay. 
•	The dynamic initial weights were determined by monitoring the zero reuse lines.
•	Outstood traditional policies (LRU,FIFO,RANDOM) in 12 out of 18 benchmarks that were run using Simplescalar.
Cache replacement using Adaptive Scoring Technique
•	Real time project designed to do the toll collection automatically.
•	Worked on interfacing of the arm controller and the RFID system.
•	Spontaneous error detection and formulation of the turbine.
Automation of toll system using non-conventional energy resources:
•	This project offers a solution to short range distance sensing by using a proximity sensor.
•	 Implemented using an Arduino uno.
Distance Range Sensor using ultrasound
•	Used for recording underwater movements.
•	Implemented using a 8051 micro controller, ESC, RC SET, battery and an AC motor.
•	Excellent maneuverability and speed of 2m/sec.
•	Presented it on a national level competition.
Designed and Fabricated an RC Airboat
https://www.linkedin.com/in/ecehan-uludag-750104112
San Jose, CA
Ecehan Uludag
Chief of Staff/Technical Assistant to VP Embedded Acceleration Division at Intel Corporation
https://www.linkedin.com/in/shreyamehrotra
Austin, Texas Metropolitan Area
Shreya Mehrotra
Product Marketing Manager at Intel Corporation
https://www.linkedin.com/in/justinefig
San Francisco Bay Area
Justine Figuerres
Field Sales Engineer at Intel Corporation
https://www.linkedin.com/in/rishab-goel
San Francisco Bay Area
Rishab Goel
Machine learning | Deep Learning | Computer Vision for Edge , AR/VR, Self-Driving and other devices / applications.
https://www.linkedin.com/in/benjamin-reynolds-666a28b7
San Jose, CA
Benjamin Reynolds
Application Engineer at Intel Corporation - Programmable Solutions Group
https://www.linkedin.com/in/deepalic
San Francisco Bay Area
Deepali Trehan
Vice President & General Manager at Intel Corporation | Visionary | Turnaround | Innovation
https://www.linkedin.com/in/jake-bosset-a76971113
San Jose, CA
Jake Bosset
Field Sales Engineer at Intel Corporation
https://www.linkedin.com/in/christopher--george
Portland, OR
Christopher George
Chief of Staff to the CEO at Intel Corporation
https://www.linkedin.com/in/poojatyagi09
San Jose, CA
Pooja Tyagi
Technical Program Manager at Amazon Web Services (AWS)
https://www.linkedin.com/in/prasad-reddy-5197553
San Jose, CA
Prasad Reddy
Field Applications Engineering Management - Intel Corporation
https://www.linkedin.com/in/dhvanic1993
Hillsboro, OR
Dhvani Chheda
Software development engineer at Intel Corporation
https://www.linkedin.com/in/nga178
San Francisco Bay Area
Nga deGrassi
Business Management at Intel Corporation
https://www.linkedin.com/in/jimdworkin
San Jose, CA
Jim Dworkin
Vice President & General Manager, Cloud Business Unit at Intel PSG
https://www.linkedin.com/in/shweta-malik-4a812423
Hillsboro, OR
Shweta Malik
Platform PnP Architect | Innovator | People Connector | NFT Nerd
https://www.linkedin.com/in/meenakshi-bhatia-6781565a
Austin, TX
Meenakshi Bhatia
Senior ASIC Design Engineer at Nvidia
https://www.linkedin.com/in/ankur-vora-aa39b9a0
San Francisco Bay Area
Ankur Vora
Strategic Wireless Business Developer at Intel Corporation
https://www.linkedin.com/in/bassamdourassi
San Francisco, CA
Bassam Dourassi (He/Him)
Serving the best way I can
https://www.linkedin.com/in/ukorat
Folsom, CA
Uday Korat
Design Engineer at Microsoft
https://www.linkedin.com/in/afsyaw
Greater Sacramento
Samuel Amoako-Frimpong
System Development Engineer at Amazon Web Services
https://www.linkedin.com/in/simranjuneja
Bellevue, WA
Simran Juneja
Lead- Business Development Representative at Click2Cloud | Former Program Manager at Microsoft
Liked by Aanchal Sharma
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Every master was once a novice. You have to start somewhere. Right?Be okay with being terrible in the beginning. Be okay with being mediocre in…
https://in.linkedin.com/in/aanchal-sharma-81b0591bb
Bengaluru
Aanchal Sharma
Pre -sales Associate at BYJU'S
https://in.linkedin.com/in/aanchal-sharma-b38b041a
Greater Delhi Area
aanchal sharma
Human Resource  at Greenrock Enterprises
https://in.linkedin.com/in/aanchal-sharma-aa300b26
India
Aanchal Sharma
Human Resource
https://in.linkedin.com/in/aanchal-sharma-6273a7221
New Delhi
Aanchal Sharma
Key Account Manager at Grayquest
https://in.linkedin.com/in/aanchal-sharma-0a990b84
Delhi, India
Aanchal Sharma
SharePoint Lead at Tata Consultancy Services
PRSSA - University of Florida
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FPGA - Field Programmable Gate Array
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ASIC, FPGA, SoC Engineers
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The University of Florida (Gator) Alumni
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UF Postdocs
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Hardware Engineers - Bringup, Validation, Unit Testing, Debugging, Firmware
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VLSI open position
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VLSI
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PESIT Alumni Network
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ECE Florida
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