Aakanksha Patil
GPU Compiler Engineer at AMD
GPU Compiler Engineer at AMD
AMD
https://www.linkedin.com/company/amd
Greater Boston Area
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GPU Compiler Engineer
CycleSCP
San Francisco Bay Area
Embedded Systems Intern
KPMG India
https://www.linkedin.com/company/kpmgindia
Mumbai Area, India
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Associate Consultant
KPMG
https://www.linkedin.com/company/kpmg
Mumbai Area, India
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Forensic Analyst
Master’s Degree
Electrical and Computer Engineering (Computer Engineering)
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North Carolina State University
https://www.linkedin.com/school/north-carolina-state-university/
Bachelor’s Degree
Electronics Engineering
Sardar Patel Institute Of Technology
ASIC Design
ECE 564
Advanced Computer Architecture
ECE 786
Architecture of Parallel Computers
ECE 506
Code Generation and Optimization
ECE 566
Computer Design and Technology
ECE 521
Embedded System Architecture
ECE 560
Embedded System Design
ECE 561
Internet Protocols
ECE 573
Operating Systems
ECE 592
Python in Engineering
ECE 592
Designed an ASIC to compute 2-layer Convolutional Neural Network in hardware to achieve maximum performance per unit area. Implemented the design in Verilog HDL, simulated the hardware using ModelSim and synthesized using Synopsys Design Vision to achieve a performance of 4.636×109 results per second per um2.
Design of 2-layer Convolutional Neural Network ASIC
Explored different control techniques such as bang-bang, proportional and PID control for a buck converter driving a high brightness LED to find the ideal CPU load and responsiveness. Optimizations to eliminate ADC busy waiting and boosting the control loop and switching frequencies results in average CPU utilization of about 85%.
Digital Control for lighting
Added Virtual Memory and demand paging support to the x86 based Xinu OS. 
This involved studying the x86 virtual memory system documentation and adding support to the existing codebase for a two-level page table with LRU based demand paging. 
In addition, virtual memory management functions (malloc/free) were implemented. Finally, a series of simple microbenchmarks were devised to test the newly added virtual memory system and memory management.
Implementation of virtual memory management and demand paging in Xinu
Implemented Shortest Time-to-Completion First and Multi-Level Feedback Queue scheduling policies in Xinu and verified their correct operation with representative test cases. 
Augmented various lock primitives in Xinu and added support for deadlock detection and prevention of deadlocks. 
Also, implemented Priority Inheritance Protocol to avoid the problem of Priority Inversion.
Implementation of synchronization mechanisms and scheduling algorithms in Xinu
Implemented alternative thread block scheduling techniques like LCA (Lazy CTA scheduling) by leveraging a greedy warp scheduler and BCS (Block CTA scheduling) by assigning consecutive thread blocks to the same core on GPGPU-Sim and achieved maximized resource utilization and improved overall performance.
Alternative Thread Block Scheduling for improved GPGPU Resource Utilization
Built a P2P-CI system in which peers who wish to download an RFC that they do not have in their hard drive download it from another active peer who does. 
All communication among peers or between a peer and the server is over TCP.
Peer-to-Peer with Centralized Index (P2P-CI) System for Downloading RFCs
Worked on optimizing an embedded I2C driver running on Cortex-M0+ by implementing interrupt handling to decrease the turnaround time for processing the I2C payload. 
Further optimizations were implemented by taking advantage of the thread features of CMSIS-RTOS RTX to make about 81.55% of the total time available as idle time during I2C message transmission.
Latency optimization for Real Time Systems
Implemented different scalar code optimization strategies using LLVM. 
Wrote the following Optimization Passes:
-CSE (Common Sub-Expression Elimination)
-LICM (Loop Invariant Code Motion)
-SLP (Superword Level Parallelism)
Code Optimization using LLVM IR
Developed a trace based simulator for a 9 stage out-of-order 4-way (configurable) superscalar CPU pipeline for a simple ISA.
This included a Reorder buffer, Instruction Queue (Reservation Station) and full renaming support for dynamic instruction scheduling.
 A simple hardware prefetching mechanism and different types of branch predictors were also modeled.
Language Used: C++
Dynamic Instruction Scheduling for an Out-of-order Superscalar Processor
•Modeled a Branch Predictor Simulator and used it to calculate the branch misprediction rate for different Branch Predictors
•Branch Predictors: Bimodal, Gshare, Hybrid, Yeh/Patt
•A set associative Branch Target Buffer (BTB) 
•Language used: C++
Branch Predictor Simulator
Designed a trace driven simulator to model MSI, MOSI and MOESI coherence protocols with both bus based and directory based implementations.
Cache Coherence Protocol Simulator
•Implemented a cache hierarchy simulator to estimate the cache miss rates for different cache configurations when running different workloads.
•The multilevel Cache Simulator could be used with a combination of different replacement policies and inclusion policies as given below:
•Replacement policies: LRU, FIFO, Pseudo LRU
•Inclusion policies: Inclusive, Exclusive, NINE
•Language used: C++
Cache Hierarchy Design Simulator
Programmed an LLVM Bit Code Generator for features of the C language.
Defined tokens using Flex as the parser generator. 
Implemented support for if-then-else, while, for loop and expression statements.
LLVM Bit Code Generator for a Subset of the C language
Prototyped a portable device to sense patient vitals (heart rate and temperature) using real time controls on ATMega64. 
Wirelessly transmitted this data using RF transceivers and uploaded to a webpage. 
In case of an emergent situation, the patient’s doctor and emergency contacts were alerted via an email and SMS notifications.
Wireless Transmission and Online Monitoring of Patient Vitals
https://ca.linkedin.com/in/cgmillette
Calgary, AB
Chris Millette
MTS Software Development Engineer at AMD
https://www.linkedin.com/in/alexander-freij
Raleigh, NC
Alexander Freij
PhD Candidate at NC State University
https://ca.linkedin.com/in/oak-zeng-443b4322
Toronto, ON
Oak Zeng
GPU driver engineer at AMD
https://www.linkedin.com/in/srividya-karumuri-8959063b
San Jose, CA
Srividya Karumuri
GPU Compiler Engineer at Apple
https://www.linkedin.com/in/hyundokcho
San Francisco Bay Area
Hyun Dok Cho
Compiler Software Engineer at NVIDIA
https://www.linkedin.com/in/rishisurendran
San Francisco Bay Area
Rishi Surendran
Deep Learning Compiler Engineer at NVIDIA
https://www.linkedin.com/in/rishkul-kulkarni-3b77482a
Austin, TX
Rishkul Kulkarni
Compiler Software Engineer at NVIDIA
https://www.linkedin.com/in/samyukthagiriswamy
San Jose, CA
Samyuktha Giriswamy
Software Engineer 2 at Cisco
https://www.linkedin.com/in/kashish-shah
San Francisco Bay Area
Kashish Shah
Engineer at NXP Semiconductors
https://www.linkedin.com/in/shivashankargurumurthy
San Francisco Bay Area
Shiva Gurumurthy
Senior Product Marketing Manager at AMD
https://in.linkedin.com/in/sameerds
Bengaluru
Sameer Sahasrabuddhe
Principal Member Of Technical Staff at AMD
https://www.linkedin.com/in/namratakedia
Redmond, WA
Namrata Kedia
Product Manager @ Identity, Microsoft
https://www.linkedin.com/in/priyankapashte
Redmond, WA
Priyanka Pashte
Software Engineer II at Microsoft
https://www.linkedin.com/in/afsana-chowdhury
Raleigh-Durham-Chapel Hill Area
Afsana Chowdhury
MS-ECE Student at Duke University
https://www.linkedin.com/in/emine-fidan-a4a199b9
Raleigh-Durham-Chapel Hill Area
Emine Fidan
Ph.D. Candidate at North Carolina State University
https://www.linkedin.com/in/sagarupadhyay212
Sacramento, CA
Sagar Upadhyay
Engineer at Intel Corporation
https://www.linkedin.com/in/prashant-joshi
Washington DC-Baltimore Area
Prashant Joshi
DevOps Engineer at SkyCreek Corporation
https://www.linkedin.com/in/arutikasood
Chandler, AZ
Arutika Sood
Senior Design Verification Engineer at Arm | Computer Engineer | Hardware Design and Verification
https://www.linkedin.com/in/ankitaharmalkar
San Francisco Bay Area
Ankita Harmalkar
Senior Digital Design Engineer at Intel Corporation
https://www.linkedin.com/in/harshpreetkaursondh
Austin, Texas Metropolitan Area
Harshpreet Kaur Sondh
Senior Silicon Design Engineer at AMD
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While we are at it, just a shout out to my amazing friend & senior from college, Saurabh Naresh Netravalkar who is currently the captain of (no…
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Rochester, NY
Aakanksha Patil
Master of Science in Data Science,  Actively seeking Internship opportunities for Summer '22| Data Science | Data Analysis | Machine Learning
https://in.linkedin.com/in/aakankshapatiljadhav
Pune
Aakanksha Patil
Associate Analyst BI at Eaton | Data Enthusiast | Business Analytics | MBA | Ex-GE India | COEP
https://in.linkedin.com/in/aakanksha-patil-9084a219b
Maharashtra, India
Aakanksha Patil
SAP MM CONSULTANT
https://in.linkedin.com/in/aakanksha-patil-0907a9190
Mumbai
Aakanksha Patil
Research Analyst - Technical Content Developer at AI Probably
https://www.linkedin.com/in/patilaakanksha
Duluth, GA
Aakanksha P.
Technology Sr. Analyst at Accenture