aaron cook
Principal Design Engineer at Eta Wireless, Inc.
principal design engineer - team lead - analog mixed signal
electrical ic design engineer extensive success semiconductor industry . expertise integrated circuit design , revision control , model based design requirement management . guru git , matlab , simulink , scripting cadence . creating robust innovative new product passion .
Eta Wireless, Inc.
https://www.linkedin.com/company/eta-wireless
Cambridge, Massachusetts, United States
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Principal Design Engineer
Allegro MicroSystems, Inc.
https://www.linkedin.com/company/allegro-microsystems
• Lead team development of first 3D linear sensor ALS313131 and several flagship Allegro current sensors, ACS724 and ACS722. All are highly successful products and further spawned into a larger product family.
• Lead development of early GMR product
• Supported early development of corporate IP blocks found at the core of most Allegro products today. Designed early prototypes of charge pump system for EEPROM programming
• Designed, verified and synthesized complex speed and direction detecting Functional State Machines using Verilog code. These state machines are an integral piece of Allegro’s industry-leading speed and direction sensors
• Tuned and modified key analog signal processing circuitry
• Designed digital temperature compensation algorithms for world-class temperature-independent performance
• Performed automated verification and validation of silicon using MATLAB
• Simulated system-level silicon functionality in Cadence mixed-signal environment
• Wrote specification and designed simple single wire programming protocol for sensors
• Designed “LBIST” (Logic built-in self-test) controller widely used in Allegro Sensors for improving reliability.
Manchester, New Hampshire
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Senior Electrical Design Engineer
Allegro MicroSystems, Inc.
https://www.linkedin.com/company/allegro-microsystems
• Lead team development of automotive-grade 3D sensors
• Implemented design process changes that increased overall design process efficiency
• Designed and verified key digital algorithms and analog blocks
Manchester, New Hampshire
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Principal Design Engineer - Team Lead
Allegro MicroSystems
https://www.linkedin.com/company/allegro-microsystems
Allegro Microsystems: Internship	Manchester, NH Summer 2007

• Evaluated of test chip and Design of voltage regulator. Evaluated performance of a test chip for new process technology. Compared laboratory results with simulation results to determine the accuracy of the provided models. Blocks of the test chip evaluated included buffers, a delta-sigma A/D converter, and a bandgap reference. A follow was designing a voltage regulator in Cadence that supplied power for the digital portion of a future test chip. 

• Developed Rails website for Ocean Scripting. Designed a website using Ruby on Rails that generated ocean script templates for the Cadence design environment. The website’s purpose was to aid in PVT simulation, reducing the time by hours to run desired corner simulations. Required expertise of ocean scripts, the Cadence ADE, and Ruby.
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Intern
Linear Technology
https://www.linkedin.com/company/linear-technology
Linear Technology: Lab Internship Bedford, NH Summers 2005/2006

• Designed and created PCB Layout of Fast Active Load. Designed the active load’s power supply and an over-temperature protection circuit.  Used SwitcherCAD (LTSpice) to simulate and verify circuit operation. Designed PCB layout for the fast active load. Utilized PADS Logic and Layout to create a Gerber file for board manufacturing. After designing, populated PCB board and tested the operation of the fast active load.

• Created Inventory and Organization of Laboratory Supplies using Access Database. Designed an Access database and website that cataloged Linear Technology’s laboratory supplies and generated purchase orders when the supplies diminished.
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Intern
Bachelor of Science - BS
Electrical and Electronics Engineering
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University of Maine
https://www.linkedin.com/school/university-of-maine/
A ruby based register map generation tool.
RubyGen
https://github.com/cookacounty/rubyreg.git
Multiple Git Repository Package Manager
GitPack
https://github.com/GitPack/GitPackRuby
The ALS31300 is Allegro's first 3d linear hall effect sensor. As design lead I was challenged with implementing a complex mixed signal system while keeping power and area to a minimum. I was responsible for a majority of the analog design and for the signal processing portion of the digital design. I take great pride in this product as well as techniques myself and the design team employed during the device's inception.
Design Team Lead ALS31300
http://www.allegromicro.com/en/Products/Magnetic-Linear-And-Angular-Position-Sensor-ICs/Linear-Position-Sensor-ICs/ALS31300.aspx
The A1454 is an I2C based linear Hall effect sensor IC which provides a 12-bit digital output word that is proportional to the strength of the magnetic field that is present. The A1454 was my first opportunity to explore my own limitations as a designer and I am proud to say that it is one of the best works of my career.
Design Team Lead A1454
http://www.allegromicro.com/en/Products/Magnetic-Linear-And-Angular-Position-Sensor-ICs/Linear-Position-Sensor-ICs/A1454.aspx
The ACS724 is a Current Sensor IC With Common-Mode Field Rejection. The ACS724 was my second major design lead role at Allegro and involved major rework from existing products as well as translating from Cadence 5 to 6. Some of the key challenges in the design I was responsible for:
   - Writing scripts to reduce the manual effort of translating schematics between versions of software.
   - Analog design of several critical high performance blocks
   - Mixed signal verification of the top level IC
Design Lead ACS724
http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Zero-To-Fifty-Amp-Integrated-Conductor-Sensor-ICs/ACS724.aspx
The ACS722 current sensor IC is an economical and precise solution for AC or DC current sensing in industrial, commercial, and communications systems. The ACS722 was my first design lead role and I was responsible for:
   - Modifying and improving the performance of existing analog circuitry
   - Mixed signal verification of the top level IC
   - Coordinating with layout engineers
Design Lead ACS722
http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Zero-To-Fifty-Amp-Integrated-Conductor-Sensor-ICs/ACS722.aspx
CdsGit is a SKILL++ library written that allows a user to use Git to manage their cadence libraries. Unlike other Git clients, CdsGit is tailored to the cadence DFII infastructure and makes interfacing with Cadence cells easy.
CdsGit
https://github.com/cdsgit/cdsgit
https://www.linkedin.com/in/johnhoversten
Greater Boston
John Hoversten
Founder/CTO at Eta Wireless, Inc.
https://www.linkedin.com/in/gchen32
San Francisco Bay Area
George Chen
Sr. Automotive HW Product Manager/PMM at Monolithic Power Systems, Inc.
https://in.linkedin.com/in/shyam-narayan-gupta-482b596a
Hyderabad
SHYAM NARAYAN GUPTA
Engineer -II, DEG Design at Micron Technology,Inc. Stdcell Design || Charecterization || Validation || DRAM ||DDR4,5 ||LPDDR4,5
https://in.linkedin.com/in/dr-akhilesh-verma-65636720
Delhi, India
Dr. Akhilesh Verma
Sr. Engineer (R & D) at Bhumi Entech Equipments Private Limited|Mentor at University of California, San Diego
https://www.linkedin.com/in/athanasios-ramkaj
San Francisco, CA
Athanasios (Thanos) Ramkaj, Ph.D.
Postdoctoral Research Fellow at Stanford University | Visiting Researcher at Kilby Labs
https://www.linkedin.com/in/ajinkya-ambre
San Diego, CA
Ajinkya Ambre
Software Test Engineer at Qualcomm
https://www.linkedin.com/in/deborahbunting
Cedar Rapids, IA
Deborah Bunting, CIR
Senior Recruiter at Skyworks Solutions, Inc.
https://se.linkedin.com/in/christian-st%C3%A5hlberg-1271a527
Stockholm County, Sweden
Christian Ståhlberg
Senior Software Developer
https://www.linkedin.com/in/suresh-kariyadan-8300813
San Jose, CA
Suresh Kariyadan
Engineering Manager/Principal Power Architect at Apple
https://www.linkedin.com/in/abhorkar
Cupertino, CA
Abhay Bhorkar
Product@Amazon | Smart Home | Alexa | CX | Day 1
https://www.linkedin.com/in/tim-comer-b2a249139
Princeton, WV
Tim Comer
Mechanical / Manufacturing / Facilities Engineering
https://www.linkedin.com/in/sanchezleo
El Paso, TX
Leo Sanchez
Purpose driven investment leader passionate about helping people achieve their fullest potential! @mynd | ex-Zillow | #proptech #sfr #b2r
https://in.linkedin.com/in/nithin-kamath-81136242
Bengaluru
Nithin Kamath
Founder & CEO at Zerodha
https://www.linkedin.com/in/analogjedi
Concord, NH
D. Jamie Haas
VP, Global Design Engineering, AIStorm
https://www.linkedin.com/in/adam-lawrence-598b7b3
Goffstown, NH
Adam Lawrence
Design Manager at Allegro MicroSystems
https://www.linkedin.com/in/hong-xiao-55160332
Greater Boston
HONG XIAO
Principal IC Design Engineer at Allegro MicroSystems
https://www.linkedin.com/in/srujansj
Greater Boston
Srujan Shivanakere
Electronic Design Engineer
https://www.linkedin.com/in/loren-mclaury-16379311
Hillsboro, OR
Loren McLaury
Principal Design Engineer at Lattice Semiconductor
https://www.linkedin.com/in/jacob-w-reese
Portland, OR
Jacob Reese
Principal Design Engineer at MACOM
https://www.linkedin.com/in/gregwardle
San Jose, CA
Gregory Wardle
Principal Design Engineer at Maxim Integrated
D. Jamie Haas
      
          



            
              
        
              
  

    
        Simply stated, Aaron far exceeding my expectations during his internship at Allegro. Aaron is very talented and picked up technical concepts extremely fast. He was able to quickly understand complex problems presented to him. During his internship, Aaron developed a Web2.0 simulation worst casing tool for writing/modifying Cadence Ocean scripts for analog IC design. My group still uses this tool exclusively for design worst casing!
Liked by Aaron Cook
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The dawn of a new era! Perhaps a 14 year old designing a chip is a bit of a stretch unless we are talking about connecting IP’s or logic gates…
Liked by Aaron Cook
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View my verified achievement from Cadence Design Systems.
Liked by Aaron Cook
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I have recently discovered Chisel. Think Object Oriented abstracted Verilog/VHDL. It is a hardware design language that facilitates advanced circuit…
https://www.linkedin.com/in/aaron-cook-696b5626
Columbia, TN
Aaron Cook
Owner, Prestige Marble & Granite Inc.
https://au.linkedin.com/in/aaron-cook-73428061
Nerang, QL
Aaron Cook
WHS&E Coordinator
https://www.linkedin.com/in/aaron-cook-72633a33
Greater Sacramento
Aaron Cook
Media Technician at Judicial Council of California
https://au.linkedin.com/in/aaron-cook-5b820383
Greater Sydney Area
Aaron Cook
Director at Cie-Elle Digital Imaging
https://www.linkedin.com/in/aaron-cook-934a1aab
Greater Reno Area
Aaron Cook
Head Football Coach at Galena HS
Analog Mixed-Signal and RF (AMS/RF) IC Design and Development Group
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ANALOG MIXED SIGNAL
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Analog & Mixed Signal Society
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Rubyists
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MATLAB Users and Integrators
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