Aakash Khanna
SoC Physical Design Verification Engineer at Apple
SoC Physical Design Verification Engineer at Apple
TECHNICAL SKILLS
•Programming/Scripting Languages: Verilog, System Verilog, MIPS Assembly, C, Python,  VHDL 
•EDA/Software Tools: Cadence 6, Cadence 5, Cadence Virtuoso ADE, Cadence Spectre, HSpice, Cadence ICFB, QuestaSim, Xilinx ISE, Optsim, Keil µvision v5, Flash Magic, CollabCAD, Matlab, Oracle SQL plus
•Simulators : Gem5 Processor Simulator (for Alpha Processor), MARS,  NS2, NS3
•Hardware Platforms: Arduino Uno, Raspberry Pi
•Operating Systems: Comfortable with Windows, Linux
Apple
https://www.linkedin.com/company/apple
Santa Clara, California, United States
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SoC Physical Design Verification Engineer
Intel Corporation
https://www.linkedin.com/company/intel-corporation
Arizona, United States
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Graduate Technical Intern
Master's degree
Electrical and Electronics Engineering  (Electronic and mixed-signal circuit design)
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Arizona State University
https://www.linkedin.com/school/arizona-state-university/
Bachelor of Technology - BTech
Electronics and Communications Engineering
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Guru Gobind Singh Indraprastha University
https://www.linkedin.com/school/guru-gobind-singh-indraprastha-university/
Advanced Analog Integrated Circuits
EEE 523
Analog Integrated Circuits
EEE 591
Computer Architecture 1
CSE 420
Digital Systems and Circuits
EEE 591
Low-Power Bioelectronics
EEE 521
VLSI Design
EEE 525
Analog Electronics - I
ETEC-203
Analog Electronics - II
ETEC 204
Computer Organization and Architecture
ETCS 204
Digital System Design
ETEC 309
Embedded Systems
ETEC 401
Microprocessors and Microcontrollers
ETEC 305
Switching Theory and Logic Design
ETEC 205
Designed a regulator with Vref = 1.15V delivering load current of 0.1mA-50mA that regulates the battery voltage and provides a well-specified and stable regulated output voltage of 2.3 V with Vripple < 5% going to the portable system (e.g. mobile phone, tablet, portable PC, etc.)
Design of Low-Dropout Regulator (LDO)
Designed a high performance 4-to-1 Integrate-and-Fire (IF) Neuron that maximizes the speed comprising of 4-bit Carry Save Adders, C2MOS D-Flipflops, OR gate (comparator), and various other logic gates. The Performance metrics viz; Area, Power and Delay fulfilled all the constraints. The design was verified for DRC & LVS checks and the functionality was verified by extracting parasitic netlist using Starrc tool and running the testbench with “hspice” command
Design of a 4-to-1 Integrate-and-Fire (IF) Neuron
Built a multithreaded matrix multiplication benchmark using pthreads and evaluated the performance of the benchmark by calculating the runtime for varying number of threads. Parallel execution took place and the runtime decreased on increasing number of threads as execution was divided in multiple number of threads
Multithreaded Matrix Multiplication Benchmark
Implemented  a new LRU-IPV Cache Replacement Policy on Gem5 Processor Simulator and ran benchmarks (Dijkstra and Basicmath) for 2 configurations of L1 cache and L2 cache. It increased the efficiency and performance of the cache as compared to the LRU Cache Replacement Policy which slows down the cache
Implementation of a new cache replacement policy in gem5
Implemented Gshare branch predictor on Gem5 Processor Simulator and ran benchmarks (Dijkstra and Qsort) for 2 configurations of Gshare branch predictor viz; Gshare8KBP and Gshare32KBP. The accuracy of this branch predictor came out to be equal to 90.12%
Implementation of a new Branch Prediction scheme in gem5
Worked on Gem5 Processor Simulator to simulate the ALPHA processor and analyze impact of increasing L1 cache size (keeping L2 AND L3 cache size as constant) and cache associativity on performance metrics, miss rate and execution time for various benchmarks viz; Dijkstra, Qsort
Imp
Performance Analysis of Cache using gem5
Simulated various routing protocols for maximizing throughput, QoS, minimizing end to end delay and jitter. Worked on NS3 in Ubuntu (linux). Assessed performance (throughput) in different mobility speed for MANET’s through the simulation method. Variation of throughput due to change in mobility speed of nodes was observed & results were plotted
‘Bandwidth Satisfied On Demand Routing Approach for QoS Provision in Mobile ADHOC Networks(MANET’s)’
Completed training at Defence Research and Development Organization (DRDO), New Delhi. Worked on working & application of sensors at Solid State Physics Laboratory. Reviewed on Terahertz Non-Destructive Evaluation; Terahertz Imaging, Rotational Spectroscopy, Terahertz Wave Radar, Terahertz Tomography, Passive/Active Imaging Techniques
Terahertz Non-Destructive Evaluation
Submitted a Research Paper in college which provides an analysis of using Augmented Reality, Virtual Reality & Mixed Reality for delivering Health Care
Simulating Health care
Completed training on ‘Internet of Things (IoT) using Raspberry Pi’. Prepared project using Raspberry Pi, comprising of temperature and humidity sensing circuit, followed by text alerts when the temperature or humidity is raised to a particular pre-defined level
Alerts through Cellular Networks using Twilio
https://in.linkedin.com/in/aakashkh
West Delhi
Aakash Khanna
AWS Certified Solutions Architect | Project Engineer at Blackstone COE | AWS Academy Cloud Architecting Graduate
https://in.linkedin.com/in/aakash-khanna11
Bengaluru
Aakash Khanna
Senior Director-Sales, Global & Large Enterprises - Gartner, India at Gartner
https://in.linkedin.com/in/aakash-khanna-general-manager
Mumbai
Aakash Khanna
General Manager
https://in.linkedin.com/in/aakash-khanna-23884586
India
Aakash Khanna
Assistant Manager at Clarivate Analytics
PHYSICAL DESIGN GROUP
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Arizona State University - the official ASU Alumni community
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