aarathy soundararajan
Product Development Engineer at Intel Corporation
product development engineer intel corporation
experienced design verification engineer . strong research professional mse focused electrical electronics engineering arizona state university .
Intel Corporation
https://www.linkedin.com/company/intel-corporation
San Francisco Bay Area
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Product Development Engineer
Cirrus Logic
https://www.linkedin.com/company/cirrus-logic
•	Verification of the Functionality of the speaker model - Generation of the ramp signal and the sine wave signal to generate the PWM signal for the speaker model (RTL System Verilog coding), generating the stimulus code and setting up the testbench in Cadence. Analysis of the functionality waveforms, exporting values and performing FFT for further in-depth analysis.

•	Integration of EEnet Models for AMS/DMS Test flow. Aided in the implementation of the DMS Testbench Architecture for verifying the functionality of the design. Connecting models through interface, creating test harnesses vip and verifying through DMS and AMS testbench flow.
Austin, Texas Area
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Design Verification Engineer- Intern/Co-op
Arizona State University
https://www.linkedin.com/company/arizona-state-university
Tempe, Arizona, United States
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Graduate Teaching Associate
Arizona State University
https://www.linkedin.com/company/arizona-state-university
Under Dr. Olin Hartin and Dr. Marnie Wong for HDL Digital Design using Verilog and system verilog and also Digital/Analog Design class.

Assisting Undergraduate students with their lab assignments, Verilog coding and their projects in labs
Tempe, Arizona
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Graduate Assistant
Decreasing the Size, Improving performance andI mprovement of Battery in Electronical devices with the help of Super-capacitors by 37%.
Nanotechnology in Flexible Electronics
HDL
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Advanced Analog Integrated Circuits
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Analog Integrated Circuits
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Circuit Theory
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Computer Architecture
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Computer Networks
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Constructionist Approach to Microprocessor Design
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Data structures and Algorithms
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Digital Logic circuits
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Digital Signal processing
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Digital Systems and Circuits
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Electromagnetic Theory
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Electronic Devices and circuits
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Fundamentals of Computing and programming
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Hardware Acceleration and FPGA
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Hardware Descriptive Language
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High Voltage Engineering
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Introduction to Electric and Autonomous Vehicles
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Linear Integrated Circuits
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Microprocessor and Microcontroller
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Object oriented programming
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Operating Systems
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Power Electronics
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Semiconductor Device Theory
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VLSI Design
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Implemented a Microcode Engine which executes 14 Instructions and this led me to the understanding of RISC-V Processor and also Built blocks of Priority Encoder, Sorting network with pipelined, ALU, Sequential Multiplier with Booth Encoding etc.,
Microcode Engine
•	Designed OTA designs ranging from basic to enhanced output impedance OTA to produce output current with differential input pair and op amp designs such as Telescopic cascode amplifier, folded cascode amplifier to meet the specified requirements across PVT corners. Also Designed Biasing Circuitry and used Beta Multiplier as a source.
•	Developed Layout for the designs based on symmetry techniques like common centroid, inter-digitization for increased accuracy of post layout results
•	Designed folded cascode OTA with class AB buffer stage and optimized the OTA with 10MHz gain bandwidth, PSRR and CMRR of 80dB and 10nV/sq(Hz) of input referred thermal noise.
Amplifiers and Optimization
Designed a convolution Neural Network in system Verilog(Image Processing Algorithm) and average-pooling module, using FINFET 7nm technology where the module input consists of three 4x4 pixel images (R, G, B) and three 3x3 convolution kernels, and module output is the average-pooling output value. Using the Automatic place and Route tool to map the following design and execute area and power optimization. Achieved the power consumption to be around 2.09mW with a gate count of 351369 and the area to be 0.2576 mm^2. Pipelined the design and improved the performance by 40%. 

Implemented a LeNet5 architecture for Convolutional Neural Networks (CNN) using an FPGA based hardware accelerator using Xilinx Virtex7 FPGA VC707  and achieved a Throughput of 9.94GOPS and a peak performance of 646 images/sec was achieved with a design which utilizes highly pipelined and data interleaving.
Convolution Neural Networks Implementation in VLSI and FPGA
Anna University
Top 10% Students
https://www.linkedin.com/in/kaustubhgudekar
San Jose, CA
Kaustubh Gudekar
Product Development Engineer at Intel Corporation
https://www.linkedin.com/in/swagath-subramanian-67676a9
Cupertino, CA
Swagath Subramanian
Product Development @ Intel Corporation
https://www.linkedin.com/in/ryosuke-shibano-40326b11
San Jose, CA
Ryosuke Shibano
Product Development Engineer at Intel Corporation
https://www.linkedin.com/in/saishmakandukuri
San Jose, CA
Saishma Kandukuri
Product Engineer at Intel Corporation
https://www.linkedin.com/in/harrini-sree-vandavasi-srinivasan-29586695
Santa Clara, CA
Harrini Sree Vandavasi Srinivasan
Product Development Engineer at Intel Corporation
https://www.linkedin.com/in/goverdhan-reddy-p-45174849
Cupertino, CA
Goverdhan Reddy P
Hardware Test Engineering at Apple
https://www.linkedin.com/in/manju-arora-4860b01
Santa Clara, CA
Manju Arora
Sr. Engineering Manager at Intel Corporation
https://www.linkedin.com/in/yuanshu-liu-49564a82
Cupertino, CA
Yuanshu Liu
Design Verification Engineer at Apple
https://www.linkedin.com/in/justin-law-75a90222b
San Diego, CA
Justin Law
MS ECE (Computer Engineering) at UCSD
https://www.linkedin.com/in/rahul-kashyap-b712aa18
San Diego, CA
Rahul Kashyap
Sr. Staff Engineer CPU Power
https://www.linkedin.com/in/vasundhara-kakda
Manchester, NH
Vasundhara Kakda
Digital Verification Engineer at Allegro MicroSystems
https://www.linkedin.com/in/liwei-ding-9a567355
San Jose, CA
Liwei Ding
FPGA & ASIC Design Verification Manager at ScaleFlux
https://www.linkedin.com/in/pirzadmotafram1982
San Jose, CA
Pirzad Motafram
Product Manager at Siemens Digital Industries Software
https://www.linkedin.com/in/shobana-atmaraman-051b3546
San Francisco Bay Area
Shobana Atmaraman
Test Engineer at Google
https://www.linkedin.com/in/pouriamtehran
Hillsboro, OR
Pouria Tehran
Product Manager at Intel Corporation
https://www.linkedin.com/in/gottipatis
Folsom, CA
Surendra Gottipati
Product Development Engineer at Intel Corporation | Post Silicon Validation
https://www.linkedin.com/in/afsyaw
Greater Sacramento
Samuel Amoako-Frimpong
System Development Engineer at Amazon Web Services
https://www.linkedin.com/in/shweta-malik-4a812423
Hillsboro, OR
Shweta Malik
Platform PnP Architect | Innovator | People Connector | NFT Nerd
https://www.linkedin.com/in/badritiwari
Chandler, AZ
Badri Tiwari
Power Thermal Product Development Engineer at Intel Corporation