aakash patel
Software Engineer at Qualcomm
software engineer qualcomm
* reliable computer engineer 5+ year academic 2 year industrial experience field vlsi technology embedded system . * comprehensive fundament knowledge analog circuit ( cmos , filter , op-amps ) digital circuit ( flip flop , latch , counter , shift register , combinational sequential circuit ) . * deeper understanding computer architecture good knowledge harward architecture , von numen architecture , memory ( dram , sram , eeprom , nand flash , flash ) * cmos design experience using low power design methodology , mix-signal design technique , transistor sizing , transistor analysis ( static/dynamic power dissipation , leakage current , delay ) , logic design method knowledge ic fabrication method ( lithography , cvd , pvd ) * working experience c , c++ , verilog , vhdl , systemc , systemverilog , python , assembly language . * extensive experience soc , vlsi design ( asic/fpga ) verification embedded system development . * hands-on experience debugging circuit using lab tool ( o-scope , dmm , labview ) referring schematic & layout .
Qualcomm
https://www.linkedin.com/company/qualcomm
San Diego, California, United States
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Software Engineer
Legacy Inmate Communications
https://www.linkedin.com/company/legacy-inmate-communications
Cypress, California
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Telecommunications Engineer
Edovo
https://www.linkedin.com/company/edovo
Cypress, California
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Telecommunications Engineer
JK Products
•	Worked on PIC microcontroller based projects and programmed firmware of MCU’s through embedded C language.
•	Achieved excellent debugging skills through testing projects in software (MPLAB IDK) and hardware (Oscilloscope, DMM).
•	Familiar with UART, SPI, I2C, ADC, DAC, RS232, Timers, Interrupts and GPIOs.
•	Implemented CRC checksum module to secure data packets and achieved successful data communications.
•	Troubleshoot circuits with lab tools and solved bugs by reading schematic, datasheets, manuals and layouts.
•	Provided and implemented embedded solution as per client’s specifications and timing deadline.
Torrance, California
Electrical Engineer
Angel Industrial Instrumentation
https://www.linkedin.com/company/angel-industrial-instrumentation
• Designed various programs on ARM and PIC microcontrollers and debugged through IDEs, emulators and logic analyzers.
• Involved in development of project based on communication protocols such as SPI, I2C, and UART.
• Managed projects as per their budget and time limit and improved communication skill by working in a sales part of the company.
Surat, Gujarat, India
Service Engineer
Angel Industrial Instrumentation
https://www.linkedin.com/company/angel-industrial-instrumentation
• Part of a development team for the book issuing system based project. Learned about the functionality of components such as PIC microcontroller, RFID tag, and GSM modem.
• Developed leadership skills through working with other interns in the same project.
Surat, Gujarat, India
Engineering Student Intern
Master of Science (M.S.)
Computer Engineering
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California State University, Fullerton
https://www.linkedin.com/school/california-state-university-fullerton/
Bachelor of Engineering (B.E.)
Electronics and Communications Engineering
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Gujarat Technological University
https://www.linkedin.com/school/gtuuniversity/
Advanced Nanoelectronics
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Advanced Secure Hardware Design
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Computer Architecture
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Computer Design and Organization
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Digital design with FPGA
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Introduction to Digital Vlsi Logic Design and Computer Organization
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Introduction to Logic Design in Nanotechnology
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Low Power Digital IC Design
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Microprogramming and Embedded Microprocessors
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Mixed-Signal IC Design
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VLSI Testing and Design for Testability
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• Explored Python uses in FPGA testing by generating test cases in Python.
• Implemented all test cases in Verilog based digital circuits such as adder, multiplexer and many other circuits.
• Compared test results with referenced results and solved errors.
Digital Design Verification with Verilog and Python
* Worked on an embedded system based project and developed source code in embedded C and programmed on two microcontrollers.
* Generated APIs and driver files for SPI master and slave circuits. Achieved successful data transmission between master and slave SPI based microcontrollers. Keil MDK tool used for programming.
Driver Development of SPI Protocol
• Developed SystemC code for five stages of ARM processor.
• 32-bit ARM instruction decomposed through fetch, decode, execute, memory and write back stages.
• Compiled on Linux environment. Verified design by giving two different instructions which performed addition and subtraction
operation.
5 stage 32-bit pipelined processor
• Generated Verilog code for cache module through Icarus Verilog. Developed modules for memory, cache controller.
• Successfully tested code by generating test bench and analyzing hit and miss rate of inputs.
Cache Memory Controller
• Designed and implemented digital logic control in dual slope ADC in 180um process.
• Design and layout was done using cadence library.
Dual slop ADC design implementation in Cadence Virtuoso
• Compared XOR implementation of general CMOS technology with gate diffusion input (GDI) technique.
• Developed HSPICE code for XOR circuit based on GDI technique implementation.
• Observed propagation delay, static and dynamic power dissipation of 32nm and 22nm technology nodes through Cosmosscope. Achieved a less power dissipation and less delay in GDI technology based circuit.
XOR gate implementation using GDI technique and comparison with other technologies
Generated Verilog code for project based on the digital clock and implemented on Nexys4 FPGA board with using Xilinx Vivado Design Suite. Output was displayed on LCD of FPGA board.
Digital Clock
• Prepared Verilog code and simulated in Xilinx Vivado tool. Programmed project code on Nexys 4 FPGA board, working on 25 MHz clock frequency.
• Analyze output in the monitor by connecting it to FPGA board through a serial port.
VGA Display
• Designed layout for Digital Phase lock loop in Microwind CMOS Layout tool.
• Locked waveform and verified functionality at the 1GHZ frequency.
DPLL design and layout
• Built encryption code for the RC4 algorithm which is used in various cryptography process. Developed ciphertext by combining plain text and keystream. 
• Programmed in C language through turbo C tool.
RC4 Cryptographic Algorithm
LinkedIn
www.linkedin.com
IoT Foundations: Operating Systems Fundamentals
http://www.linkedin.com/learning/iot-foundations-operating-systems-fundamentals
Corelis Inc.
Boundary Scan Training
Udemy
www.udemy.com
UC-CTMJM60D
SOC Verification using SystemVerilog
https://www.udemy.com/certificate/UC-CTMJM60D/
https://www.linkedin.com/in/hem-metalia
Los Angeles Metropolitan Area
Hem Metalia
✔️ Open for full-time Software/Hardware opportunities
https://www.linkedin.com/in/edovo-admin-47375a177
Greater Chicago Area
Edovo Admin
Edovo Admin at Edovo
https://www.linkedin.com/in/molly-flesner-8282b838
Urbana, IL
Molly Flesner
Office Manager at University of Illinois at Urbana-Champaign
https://www.linkedin.com/in/maciej-szajnert-1a97ab45
Greater Chicago Area
Maciej Szajnert
Translator/interpreter
https://www.linkedin.com/in/daniel-diaz-2909441b2
Stanton, CA
Daniel Diaz
Field Operations Technician at Edovo
https://fr.linkedin.com/in/drisagrour
Paris
Dris Agrour
Embedded Systems Engineer
https://www.linkedin.com/in/francisco-flores-3247a4199
Los Angeles Metropolitan Area
Francisco Flores
Bridged Innovations
https://www.linkedin.com/in/jamilah-taylor-aa233a179
Dolton, IL
Jamilah Taylor
Machine operater at FLEX-N-GATE Chicago
https://www.linkedin.com/in/guliwem
Greater Chicago Area
Mbali G.
Program & Artistic Manager at Storycatchers Theatre.
https://www.linkedin.com/in/project-one-eleven-636105114
Greater Chicago Area
Project One Eleven
Illinois prison reform advocates
https://il.linkedin.com/in/zipi-shadmi-glazer-34753780
Israel
Zipi Shadmi Glazer
C++/SystemC engineer at Intel Corporation
https://in.linkedin.com/in/shabarish-s-37a05152
Bengaluru
Shabarish S
SystemC Modeling Engineer at CircuitSutra Technologies
https://www.linkedin.com/in/bryant-rollins-82690883
Chandler, AZ
Bryant Rollins
MTE at Intel Corp. at Intel Labs
https://kr.linkedin.com/in/sanghyong
Seoul, South Korea
Sanghyong Lee
Software Engineer at HP
https://www.linkedin.com/in/nicolasga
San Francisco Bay Area
Nicolas Gagnon M. Ing.
Silicon Software Engineer at Apple
https://kr.linkedin.com/in/daegeunlee-4142a6111
Gyeonggi, South Korea
Daegeun Lee
Engineer with 15 years of experience in Embedded system and Automation Control system
https://www.linkedin.com/in/jasmine-aguirre-8a3369b2
Long Beach, CA
Jasmine Aguirre
--
https://www.linkedin.com/in/margaret-glaspie-68b4a01a5
Forest Park, IL
Margaret Glaspie
Corporate Services Specialist at Not working
https://www.linkedin.com/in/david-kelly-a653b8167
Greater Chicago Area
David Kelly
Executive Director at PRECIOUS BLOOD MINISTRY OF RECONCILIATION NFP
Astha Parikh
      
          



            
              
        
              
  

    
        I know Aakash since his BE days and have also found Aakash to be an extremely motivated and helpful person. Aakash is very knowledgeable and eager to help. Aakash is very patient and unfazed by challenges. He is very perseverant, which I believe is his biggest skill. Combined with his pleasing personality I believe he'll be a great asset to any company he is a part of. I wish Aakash all the best and always hoping our paths cross again :) Natja Blomer-Vargas
      
          



            
              
        
              
  

    
        Aakash is someone that I can count on to not only finish the job, but also to finish it with quality.  His communication is outstanding as he provides frequent updates on his progress.  He finishes things quickly with a drive for excellence and a cheerful and helpful approach.  His technical knowledge and his willingness to explain to less technical people is commendable and creates a very open and trusting environment. I appreciate his diligent, supportive presence on our project team.  
https://au.linkedin.com/in/aakash-patel-93949b7a
Adelaide, SA
Aakash Patel
Electronics Software and Control Systems Engineer at Supashock
https://in.linkedin.com/in/aakash-patel-b69942101
Surat
Aakash patel
Mechanical Engineer at UNITED PHOSPHATE PRIVATE LIMITED
https://in.linkedin.com/in/aakash-patel-46210851
Surat
aakash patel
director at aakash group
https://ca.linkedin.com/in/aakashpatel0902
Cambridge, ON
Aakash Patel
Consultant at CGI
https://in.linkedin.com/in/aakash-patel-95b2923a
Surat
Aakash Patel
Event Managment
Cavium
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FPGA - Field Programmable Gate Array
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College Grad Recruiting
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ASIC & FPGA Experts Group
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Entry Level Engineers
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ASIC, FPGA, SoC Engineers
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ARM Based Group
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Semiconductor - VLSI
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FPGA — Design and Programmable Devices
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Penelope's Semiconductor Design Group (IC's, Mixed-signals, PMIC, Power Converters, ADC, DAC, etc.)
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ASIC-FPGA Design Verification Knowledge Sharing Group
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ASIC and FPGA Design and Verification Contract  Openings
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Intel Student Lounge
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SemiWiki.com The Open Forum for Semiconductor Professionals
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