Aalap Tripathy
Principal Research Engineer at Hewlett Packard Enterprise
Principal Research Engineer
I am currently working to advance the state of the art in Edge-to-Exascale workflows & Data Foundations for AI at Hewlett Packard Labs (AI Research Lab). Previously I worked at HPE's Moonshot, Hyperscale, HPC and Edge & IoT Systems R&D teams designing and evangelizing HPE's Moonshot micro-servers for software defined & workload optimized datacenter (https://www.hpe.com/us/en/servers/moonshot.html).,  invented a new "product category" Converged Edge Systems  - enabling hardware convergence of OT and IT technologies (https://www.hpe.com/us/en/servers/edgeline-iot-systems.html)

My prior work involved system design, prototyping, validation, data pipeline architecture, performance characterization/benchmarking, bringup, solution engineering with internal/external partners - promoting the best utilization of system capabilities in real-world use cases. In this I have to regularly straddle hardware & software - the worlds of High Performance Computing, Big Data Analytics, Embedded Systems and AI for best impact. I am equally at home busy dicing Board schematics, OS Kernels, Systems and/or component firmware or developing or analyzing an algorithm or its performance in a real-world deployments. 

I collaborate with HPE's Chief Technologists, R&D Engineers across BU’s & external partners for future architecture exploration and analysis, building Proof-of-Concept prototypes for Emerging Technologies (FPGAs & special-purpose ASIC workload accelerators).

I completed my Ph.D. in Computer Engineering at the Embedded Systems & Co-design Lab, Texas A&M University. I worked on designing and benchmarking novel many-core platforms for data-intensive computing applications (Search and Recommendation Engines in particular). I have also done a BE, EEE from BITS Pilani, India and subsequently held several leadership positions in its global alumni organization (BITSAA Int)
In Grad School, I worked with my colleagues in proposing and validating techniques to improve search engine latency while incorporating semantic disambiguation with systems designs encompassing  novel ASICs, GPU, FPGA, novel Intel many-core processors etc.). My interests subsequently moved to machine learning algorithms used in collaborative filtering/recommendation systems where I designed my own hybrid reconfigurable data intensive compute processor architecture.
Hewlett Packard Enterprise
https://www.linkedin.com/company/hewlett-packard-enterprise
Master Technologist in AI Research Lab (AIRL) @ Hewlett Packard Labs (http://labs.hpe.com)

- Pioneering Advanced Solutions and Technologies to make the emerging Edge-to-Exascale Platforms real and valuable for HPE's Federated Edge users. 
- Working towards a “common metadata foundation” for AI that is agnostic of workflow engines but can manage experiment configs, data and artifacts with the simplicity of Git.
- Architect data systems combining data acquisition from Operations Technology, advanced analytics involving AI/ML spanning multiple edges to the cloud that are easy to consume, service and scale.
Houston, Texas Area
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Principal Research Engineer
Hewlett Packard Enterprise
https://www.linkedin.com/company/hewlett-packard-enterprise
Expert Technology Evangelist &  edge-to-cloud solutions architect

- Pioneered end-to-end Industrial IoT  infrastructure and software solutions spanning  compute, storage and networking for HPE's inspiration manufacturing customers in FMCG industry. Saw project through multiple proofs-of-concept and multiple country deployment. 
-  Technically partnered with OT leadership companies such as National Instruments, PTC Thingworx, GE Predix and PLC vendor Rockwell-Collins, Siemens, Schneider. 
- Briefed key technology leaders at System Integrators such as Accenture, Capgemini, Deloitte etc. for digital transformation and real-world Industrial IoT projects. 
- Created AI Video Analytics appliance for world's largest retailers (code contribution). Also facilitated 3rd party partnerships with world's leading Independent Software Vendors. 
- Created real-world Edge-to-Core solutions for world's largest disk drive manufacturer, world's largest battery maker, USA's premier airline and world's largest electric car manufacturer through multiple projects, deployments.
- Contributed to Autonomous R&D design and development (OT data acquisition from cameras, radar, LIDAR, proprietary buses etc. and GPU accelerated AI inference) for a major aeronautical  manufacturer. Architected Edge and Core Dev-ops environment, data-logger system for real-time data capture and AI training. 
- Augmented a legacy video conferencing and collaboration software suite with AI enabled object detection, speech-to-text translation capabilities (at the edge) through presentations/papers/demos and prototypes. This lead to the introduction of a new service offering by HPE and its adoption by customers.
Houston, Texas Area
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Edge AI and Industrial IoT Solutions Architect
Hewlett Packard Enterprise
https://www.linkedin.com/company/hewlett-packard-enterprise
Specialist HPC/Big Data Engineer, HPC BU

- Architected a production ready "search appliance" using multi core ARM+DSP micro-blades in a multi-node/multi-chassis system (with a novel 2D toroidal RapidIO fabric). Contributed key algorithms from prior research experience leading to 300% speedup
- Evolved methods to rapidly mass-configure hundreds of chassis's (with thousands of nodes) with production code (pre-Kubernetes world).
- Designed Production-grade FPGA micro-blade hardware. Created OpenCL Board Support Packages  for prototype FPGA based micro-blade. (PCIe core, DDR3 controller etc.) 
- Demonstrated performance gains with CPU, FPGA hybrid architectures for streaming analytics in a real scalable micro-blade based multi-chassis system. Presented paper + live demo at Supercomputing '16
- Briefed key Service Provider CTO on performance impact of Hadoop, NoSQL database applications with HPE's Moonshot cluster-in-a-box (and value of novel accelerators such as FPGAs on their app)
 - Created and presented performance benchmark analysis to HPE's key high performance computing applications at internal and external forums (HP-CAST, Supercomputing). 
- Contributed to and evangelized HPE's Elastic Platform for Analytics (EPA).  This included separation of compute and storage planes in Hadoop to separate specialized and highly optimized systems.
-  Championed the Web/Analytics use-cases such as NoSQL databases (Cassandra, Vertica etc.) and real-time streaming analytics with Apache Kafka, Storm and Flink with HPE's Moonshot micro-blades. Led briefings and performance analysis for key strategic customers leading to wins and scaleout deployments
Houston, Texas Area
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Hyperscale Big-data & HPC Solutions Engineer
Hewlett Packard Enterprise
https://www.linkedin.com/company/hewlett-packard-enterprise
Specialist Hardware Engineer - Moonshot R&D. HPE Moonshot is a massively parallel, heterogeneous compute cluster (multitude of x86, ARM, FPGA compute blades) - built for hyperscale and HPC market

- Team that engineered the HPE ProLiant m400 - World’s first 64-bit ARM server
- Team that engineered the HPE ProLiant m800 - World’s first commercially available ARM+DSP server
- Pioneered Disruptive System architectures using  FPGA’s and Microblades. Delivered systems to Top US National Labs and Research Institutions and corporates.
- Performance Analysis, Systems architecture & positioning of modular micro-blades for High Performance Computing, High Performance Data Analytics (HPDA) and recently ML/AI workloads (x86, GPU, FPGA, VPU, ASICS) such as Video Analytics, Autonomous Drive Systems etc. 
- Member of Technical Staff in the team that invented a new industry product category – Converged OT/IT Edge Systems (High Performance & Modular Edge Compute with AI Accelerators, Edge to Core Secure Manageability, Convergence of Operations Technology into IT Systems)
- Work with HPE’s strategic customers/partners to evangelize system capabilities and help “deliver outcomes” that matter in their businesses. I help connect systems to solutions rationally.
- Authored and coauthored technical papers/presentations  with my colleagues across HPE multiple at HPE TechCon leading to Patent disclosures/filings that have also found their way into HPE products and/or customer facing solutions. (18 so far and keeping at it.)
- Represent HPE at peer Industry groups (SPEC), represent technology offerings for my business unit at internal/external trade shows (HP-CAST Consortium for High Performance Computing, Supercomputing/ISC etc.)
- Serve as Technology Advisor / Internal Lobbyist for product directions to Product Managers & executives.  
- Worker, Troubleshooter, Engineer, Tinkerer, Team player
Houston, Texas
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Senior Design Engineer
Hewlett Packard Enterprise
https://www.linkedin.com/company/hewlett-packard-enterprise
- Productizing world's first ARM32 Server Blade from Calxeda in HPE Moonshot for Hyperscale applications (www.hpe.com/info/moonshot) together with HPE senior architects, ARM/Calxeda/HP Labs researchers. 
- Required an end-to-end system design mindset. Involved schematic reviews, PCB layout reviews, RAS/CAS features, interaction of firmware with on-SoC controllers, qualification of peripherals (storage, networking), Uboot/BIOS tweaks, OS Kernel qualification and end-to-end trouble-shooting
- Required updating design specifications to evolving silicon roadmap (availability of newer socket compatible SKUs) during the release process.
- Required adaption of ARM features (on-SoC controllers) into HPE-designed common chassis infrastructure (Chassis controller, on-blade satellite controller etc.) - inspired by X86 features. Key innovations were required in offering both x86 and ARM architectures micro-blades in a common chassis infrastructure - hardware compatibility, isolation and firmware based command/control had to be addressed in a complex system
Houston, Texas Area
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Systems Engineering Intern
Texas A&M University
https://www.linkedin.com/company/texas-a&m-university
Teaching Assistant for: 
CSCE 481/483 - Senior Capstone Design
(Prof. Ricardo Gutierrez, Prof. Dezhen Song, Prof. Dylan Shell) 
CSCE 315 - Programming Studio (Prof. Yoonsuck Choe) 
CSCE 617 - HW-SW Codesign of Embedded Systems (Prof. Rabi Mahapatra) - (Graduate Class)
Contributed to course material, designed and evaluated assignments, stood in for undergraduate/graduate lectures as needed. Responsible for grading undergraduate students over 11 semesters. Adjudged Best Teaching Assistant/Mentor by Department of Computer Science in 2012.
College Station, Texas
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Teaching Assistant, Computer Science Department
BITSAA Int.
https://www.linkedin.com/company/bitsaa
Aalap served as the CEO and Trustee of BITSAA International, the global all-volunteer alumni organization of BITS Pilani University from 2010 - 2012. Aalap joined BITSAA International as a volunteer in 2008 and served as Team Leader, Manager, Director in its Technology Team before being appointed as CEO by BITSAA’s Global Board of Trustees. BITSAA is organized as a 501(C)(3) non profit (registered in NJ), manages and fundraises endowments for gifts, scholarships, awards for students, staff and alumni of BITS Pilani, India.

During Aalap's tenure at BITSAA International, BITS alumni conducted their first-ever BITS Global Meet (BGM2011), raised $300k for BITS Pilani, created five new scholarships, disbursed several faculty and student grants at the BITS Pilani campuses in India. Under Aalap's leadership a Global Chapter Leadership & Batch Ambassadors Council to unite BITSAA's activities worldwide was created. BITSAA Volunteer community grew from 80 to 200 at the height of projects. Flagship projects  which demonstrate BITS alumni's passionate, forward-thinking nature for its alma-mater were created. BITSConnect2.0 (a multi-campus, multi-platform video conferencing and telepresence solutions benefiting 10,000 students & faculty @ $1.5 Mi in subsequent years) & BITSSparks (creating an eco-system to promote BITSian entrepreneurship) are some examples.
Sunnyvale, CA
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CEO & Trustee
BITSAA Int.
https://www.linkedin.com/company/bitsaa
In this role, I was responsible for setting the short-term and long-term goals for the global BITS Alumni organization. This involved consultations with a global distributed volunteer alumni community, distinguished alumnus, leadership of our alma-mater and other well-wishers. In a volunteer not-for-profit setting, it is generally easy to generate excellent ideas to benefit a large community, the trick is in creating a enthusiastic and passionate team who is suitable equipped to run after set goals. In addition, I was creating bridges and relationships with a wide cross-section of BITS Alumni (from the 1950's to current students). These activities were over and above those expected from the COO - ensuring that several of BITSAA's existing projects and specific initiatives run successfully without hiccups. This was a transitional position following my appointment as the CEO & Trustee by the BITSAA International Board of Trustees.
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COO
BITSAA Int.
https://www.linkedin.com/company/bitsaa
BITSAA International Inc. is a not-for-profit organization registered in New Jersey, USA with a mission to maximize the potential of BITSians and BITS Pilani. We work to make BITSAA the best and most well networked alumni community in the world and positively enhance your professional and personal lives. BITSAA International engages in charitable and educational activities by raising funds for setting up endowments, creating scholarships, rewarding teaching and research and generally promoting the development of resources at Birla Institute of Technology and Science at Pilani, Dubai, Goa & Hyderabad campuses. BITSAA Technology Team spans throughout all BITSAA Activities, Chapters and with all the initiatives. We are currently focusing our activities for 2009-2010 on enhancing Alumni Membership and further developing value added Apps for the website in addition to supporting our already comprehensive Portal.
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Director, Technology
BITSAA Int.
https://www.linkedin.com/company/bitsaa
BITSAA Technology Team works to create and deploy various web-based technology applications to support all BITSAA International's initiatives. One of the key elements in this is the BITSAA.org website itself. This was comprehensively redesigned and deployed based on a framework from Yourmembership.com. We support not only an Alumni Directory but provide an integrated platforms for an India/US Estore, Donation/Pledge Administration, Bulk Emailing, customizable sites for over 50 worldwide chapters. We also deployed an international teleconferencing solution, built a new membership approval application and provided value added services for the BITS Alumni Community. Our greatest achievement has been to bring over 6500+ alumni and students under one platform and enabled the collection of over $50,000 in alumni contributions within one year of launch.
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Manager, Technology
Cypress Semiconductor
https://www.linkedin.com/company/cypress-semiconductor
• Drove a Cross-functional team to take Cypress’s new System Management Solution prototype kits (power and thermal management) into production
• Created 16-bit USB digital audio reference design on PSoC3. Firmware involved programmable clock generation with adaptive synchronization
• Created Training material for USB digital audio reference design for FAE’s in consultation with domain experts
San Jose, CA
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Ph.D. Co-Op
Cypress Semiconductor
https://www.linkedin.com/company/cypress-semiconductor
Comprehensive competitive/teardown analysis of low bandwidth Power line Communication technologies. 
Authored the Advance Datasheet and User’s Guide for Cypress's Power line Communication Solution.
Created internal Cypress University (CYU) Course on Power Electronics. 
Additional laboratory work included system validation of a high efficiency DC-DC Converter for a solar battery charging application.
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Applications Engineer
Birla Institute of Technology and Science, Pilani
https://www.linkedin.com/company/birla-institute-of-technology-and-science-pilani
Conducted Practical Sessions for 600 students every week for assignments in Assembly Programming, C/C++. Assisted in designing question papers and evaluated responses during biweekly online examinations
Goa Campus
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Teaching Assistant, Computer Science Group
Birla Institute of Technology and Science, Pilani
https://www.linkedin.com/company/birla-institute-of-technology-and-science-pilani
Created and led a team of 10 to Create and maintain the BITS Pilani Goa Website. Developed Student Welfare Services (BITSZone®) – Online Railway Reservation, Insurance Data Collection, Centralized Hostel Allotment System, Scholarship Module, ID Card Generation, Fee Collection, Vacation Monitoring, Course Management Tool. Saved Rs 10 lakh in software procurement.

Also worked as Campus Server Manager -Setup and Maintained Proxy, DNS, Email, Web, FTP, LDAP, VOIP, DHCP Servers for Campus Network

Coordinated with Deans of Student Welfare, Administration to develop test plans, analyze deployment flaws for all software systems deployed.

Conducted First Online General Election for the Council for Student’s Affairs – 2005.

Led a team of 10 to create content and make 2000 copies of Glimpses 2006 – A Multimedia presentation CD containing a Year-in-review of activities at BITS Pilani.
Center for Software Development, Goa Campus
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Co-Founder and Project Leader
Bhabha Atomic Research Centre (Div Of Department Of Atomic Energy, Governm
Backup Planning and Implementation for the ANUPAM-AMEYA Supercomputer. Developed a PHP/postgreSQL/Shell Script based "incremental backup" management suite for 4Tb data. This mirrors functionality of commercial packages like AMANDA and BACULA but was developed from the ground up and customized for use on the ANUPAM-AMEYA cluster at the Supercomputing Research Facility at BARC. I did this project under the supervision of Mr K Rajesh and Mr Kislay Bhatt, Senior Scientific Officers at SRF
Supercomputing Research Facility, Anushakti Nagar, Mumbai
Engineering Trainee
Ph.D.
• Dissertation: “High Performance Information Filtering on Many-Core Processors”
• Designed algorithms for content-based & collaborative information filtering on Intel SCC, Nvidia GPU’s (~90x speedup, ~85% energy saving) in ICSC ’11, ICSC’12. 
• Developed techniques for highly parallel, power efficient ASIC for semantic comparison (~10^5 speedup, ~74% energy saving) in IPDPS’10, IPDPS ’11.
• Designed & validated a novel CGRA(Coarse Grained Reconfigurable Array) processor for data-intensive applications using Transaction-level modeling of custom-IP blocks, on-chip interconnects in BigData ’13.  
• Designed an advanced Natural Processing Pipeline combining ontology mapping, entity extraction and semantic role labeling.
• Proposed immunological (inspired) security model for Network-on-chip based many-core System-on-Chip in SAW-1 (HPCA -16 ’10)
• Mentored a team that designed and validated a natural user interface for Google Earth using a Microsoft Kinect in IJHG ’11 (most highly accessed)
Computer Engineering
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Texas A&M University
https://www.linkedin.com/school/texas-a&m-university/
B.E.
Founder and Lead for the Center for Software Development, President of the Electrical and Electronics Engineering Student's Association, Student Alumni Representative for the Class of 2008. Received the University Merit Scholarship for three years (2004-2006 for top 1% of class)
Published papers in the following topics - “Server Implementations for Campus Wide Networks – DNS, Proxy, LDAP, VOIP”, “Video Conferencing over low bandwidth networks” with Microsoft Research for Conference® XP and “Neural Networks in Production Functions for Steady State Macroeconomic Modeling”
Electrical & Electronics Engineering
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Birla Institute of Technology and Science, Pilani
https://www.linkedin.com/school/birla-institute-of-technology-and-science-pilani/
Higher Secondary
State Topper (3rd Rank) - Council for Higher Secondary Examinations (CHSE) 2002 (amongst over 100,000 students.)
Mathematics, Electronics, Basic Sciences
BJB Junior College, Bhubaneshwar
High School
Mathematics, English, Physics, Chemistry, Biology, Social Studies, Computer Science
St. Joseph's High School
Middle School
Stewart School, Cuttack, Orissa
acceptance rate 20%
The increasing amount of information accessible to a user digitally makes information retrieval & filtering difficult, time consuming and ineffective. New meaning representation techniques proposed in literature help to improve accuracy but increase problem size exponentially. In this paper, we present a novel reconfigurable computing architecture that addresses this issue, outperforms contemporary many-core processors such as Intel's Single Chip Cloud computer and Nvidia's GPU's by ~20x for semantic information filtering. We validate our design using industry standard System-on-chip virtual prototyping and synthesis tools. Such a high performance reconfigurable architecture can form a template for a wide range of content-based and collaborative filtering engines used for big-data analytics.
A Reconfigurable Computing Architecture for Semantic Information Filtering
2013 IEEE International Conference on Big Data
http://ieeexplore.ieee.org/abstract/document/6691577/
Acceptance Rate: 28%
Many-cores on chip have now become a reality. They necessitate the revisit of several layers of a cloud infrastructure. For this to happen, parallel programming runtimes need to be designed for many-cores on chip as the target architecture. In this paper, we show that Map Reduce programming paradigm can be adapted to run on Intel's experimental single chip cloud computer (SCC) with 48-cores on chip. We demonstrate this using a Collaborative Filtering (CF) recommender system as an application. CF is widely used in e-commerce deployments to predict user's preference towards an unknown item from their past ratings. We address scalability with data partitioning, combining and sorting algorithms, maximize data locality to minimize communication cost within the SCC cores. We demonstrate ~2x speedup, ~94% lower power consumption for benchmark workloads as compared to a distributed cluster multi-processor nodes in use today.
Distributed Collaborative Filtering on a Single Chip Cloud Computer
IEEE International Conference on Cloud Engineering (IC2E), 2013
http://ieeexplore.ieee.org/document/6529278/
(3rd Intl. workshop on Petascale data analytics: challenges & opportunities (PDAC ’12), Nov. 12, 2012, Salt Lake City, UT, USA)
Fast response requirements for big-data applications on cloud infrastructures continues to grow. At the same time, many cores on-chip have now become a reality. These developments are set to redefine infrastructure nodes of cloud data centers in the future. For this to happen, parallel programming runtimes need to be designed for many-cores on chip as the target architecture. In this paper, we show that the commonly used MapReduce programming paradigm can be adapted to run on Intel's experimental single chip cloud computer (SCC) with 48-cores on chip. We demonstrate this using a Collaborative Filtering (CF) recommender system as an application. This is a widely used technique for information filtering to predict user's preference towards an unknown item from their past ratings. These systems are typically deployed in distributed clusters and operate on large apriori datasets. We address scalability with data partitioning, combining and sorting algorithms, maximize data locality to minimize communication cost within the SCC cores. We demonstrate ~2x speedup, ~94% lower energy consumption for benchmark workloads as compared to a distributed cluster of single and multi-processor nodes.
Designing a Collaborative Filtering Recommender on the Single Chip Cloud Computer
IEEE Conference on High Performance Computing, Networking, Storage and Analysis (SC 2012)
http://ieeexplore.ieee.org/document/6495900/
Acceptance Rate 25%
The web is moving from an era of "search" to that of "discovery". Collaborative filtering (CF) recommender systems are now commonly used to predict user's preference towards an unknown item from past ratings. To be scalable or effective, they are typically deployed in distributed clusters and operate on extremely large apriori datasets. Improvement of the efficiency of these systems is increasingly recognized important and challenging. Meanwhile, emerging many-core processors present an opportunity to optimize these systems on a per-node basis. We identify and address challenges in fast computation of correlations by maximizing data locality and minimizing communication cost between individual cores. We experiment run-time, power and energy consumed on: (1) Intel's experimental single chip cloud computer (SCC), (2) NVIDIA's CUDA-enabled GPGPU co-processor and (3) traditional server class x86 processor. We achieve super linear speedups (~30x), reduction in energy consumption (~90%) for benchmark workloads. Introduction of this design in CF systems can significantly reduce the number of servers required in a data center, energy consumption, operation costs and floor area bringing in significant savings.
Optimizing a Collaborative Filtering Recommender for Many-Core Processors
6th IEEE Intl. Conf. on Semantic Computing (ICSC ‘12), Sept. 19-21, 2012, Palermo, Italy
http://ieeexplore.ieee.org/document/6337114/
Acceptance Rate: 21%
Emerging semantic search techniques require fast comparison of large "concept trees". This paper addresses the challenges involved in fast computation of similarity between two large concept trees using a CUDA-enabled GPGPU co-processor. We propose efficient techniques for the same using fast hash computations, membership tests using Bloom Filters and parallel reduction. We show how a CUDA-enabled mass produced GPU can form the core of a semantic comparator for better semantic search. We experiment run-time, power and energy consumed for similarity computation on two platforms: (1) traditional sever class Intel x86 processor (2) CUDA enabled graphics hardware. Results show 4x speedup with 78% overall energy reduction over sequential processing approaches. Our design can significantly reduce the number of servers required in a distributed search engine data center and can bring an order of magnitude reduction in energy consumption, operational costs and floor area.
Optimizing a Semantic Comparator Using CUDA-enabled Graphics Hardware
IEEE International Conference on Semantic Computing (ICSC), 2011
http://ieeexplore.ieee.org/document/6061421/
Superior and fast semantic comparison improves the quality of web-search. Semantic comparison involves dot product computation of large sparse tensors which is time consuming and expensive. In this paper we present a low power parallel architecture that consumes only 15 Watts and demonstrates a speed-up in the order of 10^5 compared to a contemporary hardware design, and in the order of 10^4 compared to a purely software approach. Such high performance low power architecture can be used in semantic routers to elegantly implement energy efficient distributed search engines.
Parallel Processor Core for Semantic Search Engines
IEEE International Symposium on Parallel and Distributed Systems Workshops and Phd Forum (IPDPS, 2011)
http://ieeexplore.ieee.org/document/6009044/
Most highly accessed (40k Accesses), 150+ citations
This paper covers the use of depth sensors such as Microsoft Kinect and ASUS Xtion to provide a natural user interface (NUI) for controlling 3-D (three-dimensional) virtual globes such as Google Earth (including its Street View mode), Bing Maps 3D, and NASA World Wind. The paper introduces the Microsoft Kinect device, briefly describing how it works (the underlying technology by PrimeSense), as well as its market uptake and application potential beyond its original intended purpose as a home entertainment and video game controller. The different software drivers available for connecting the Kinect device to a PC (Personal Computer) are also covered, and their comparative pros and cons briefly discussed. We survey a number of approaches and application examples for controlling 3-D virtual globes using the Kinect sensor, then describe Kinoogle, a Kinect interface for natural interaction with Google Earth, developed by students at Texas A&M University. Readers interested in trying out the application on their own hardware can download a Zip archive (included with the manuscript as additional files 1, 2, & 3) that contains a 'Kinnogle installation package for Windows PCs'. Finally, we discuss some usability aspects of Kinoogle and similar NUIs for controlling 3-D virtual globes (including possible future improvements), and propose a number of unique, practical 'use scenarios' where such NUIs could prove useful in navigating a 3-D virtual globe, compared to conventional mouse/3-D mouse and keyboard-based interfaces.
Web GIS in practice X: a Microsoft Kinect natural user interface for Google Earth navigation
International Journal of Health Geographic’s 2011, 10:45
https://ij-healthgeographics.biomedcentral.com/articles/10.1186/1476-072X-10-45
An organized lab manual  introducing students to mixed signal (analog/digital design) design using Cypress's Programmable Sytem on Chip (PSoC - 1,2,3)/ It starts with a series of fundamentals for GPIO control, LCD interfacing, Serial Communication, I2C communication, SPI communication, PWM Motor control fundamentals, Verilog coding, USB interfacing etc. a combination of which lead to the successful inclusion to create three real-life projects. Each experiment includes a Bill of Materials for a minimum viable set of laboratory experiments. Document was current as of 2011. Document and derivatives thereof were used in practice in US and Indian Universities. 

1. Gesture Controlled Robot Tank Implementation Using Cypress PRoC
2. Weather Monitoring System using PSoC-1
3. RFID Attendance Monitoring System using PSoC-3
4.  Gesture Based Car using Cypress PSoC-3
Introduction to Mixed-Signal, Embedded Design using a Programmable System on Chip (1,3,5)
Department of Computer Science & Engineering, Texas A&M University
http://www.aalap.info/pubs/PSoC_Lab_Book_2010_TAMU-2.1.pdf
In this paper we present a fine grained parallel architecture that performs meaning comparison using vector cosine similarity (dot product). Meaning comparison assigns a similarity value to two objects (e.g. text documents) based on how similar their meanings (represented as two vectors) are to each other. The novelty of our design is the fine grained parallelism which is not exploited in available hardware based dot product processor designs and can not be achieved in traditional server class processors like the Intel Xeon. We compare the performance of our design against that of available hardware based dot product processors as well a server class processor using optimum software code performing the same computation. We show that our hardware design can achieve a speedup of 62,000 times compared to an available hardware design and a speedup of 8866 times with 33% (1.5 times) less power consumption, compared to software code running on Intel Xeon processor for 1024 basis vectors. Our design can significantly reduce the amount of servers required for similarity comparison in a distributed search engine. Thus it can enable reduction in energy consumption, investment, operational costs and floor area in search engine data centers. This design can also be deployed for other applications which require fast dot product computation.
A parallel architecture for meaning comparison
IEEE International Symposium on Parallel & Distributed Processing (IPDPS 2010)
http://ieeexplore.ieee.org/document/5470371/
In this paper we propose a bio-inspired security framework for 
Network-on-Chip based many-core system-on-chip (SoC). The 
proposed framework is intended to provide an infrastructure 
suitable for handling security at chip level during potential system 
level attack. A hardware security core is introduced on-chip to 
manage SoC security challenges using a dedicated communication 
network. A signal communication model has also been proposed 
to develop various safety related protocols to address some of the
safety concerns. The proposed framework is capable of detecting 
and isolating a compromised core from the rest of the system on 
chip so as to prevent it from further exploitation. A simulation 
based experimental set up has been proposed to demonstrate the 
security infrastructure. It has been shown that the program 
execution overhead due to build in security infrastructure ranges
3-6 %. Finally the area and power overhead due to the security 
core is also given
A Bio-Inspired Framework for Secure System on Chip
Workshop on SoC Architecture, Accelerators and Workloads
http://www.aalap.info/pubs/saw2010_bioinspired_security.pdf
Acceptance Rate 30%
To enable meaning based search, computers have to store and compare meaning of user’s search intentions and objects being searched. To address the key requirement of meaning compositionality, we present: design rationale; an algebraic theory; and a technique to represent composite meaning as a tensor which is amenable to efficient similarity computation
Semantic Key for Meaning Based Searching
IEEE International Conference on Semantic Computing (ICSC 2009)
http://ieeexplore.ieee.org/document/5298618/
Semantic Routed Network (SRN) can provide a scalable distributed solution for searching data in a large grid. In SRN, messages are routed in a overlay network based on the meaning of the message key. If the message key describes the desired data, then SRN nodes can be addressed and accessed by the description of their data content. The key challenges of materializing a SRN are: (1) designing a data structure which will represent complex descriptions of data objects; (2) computing similarity of descriptors; and (3) constructing a small world network topology that minimize the routing response time and maximize routing success, which depends on solving the first two problems. We present a design of a descriptor data structure and a technique to compare their similarity to address the first two problems.
Representation of complex concepts for semantic routed network
IEEE/ACM International Conference on Distributed Computing and Networking (ICDCN 2009)
http://dl.acm.org/citation.cfm?id=1532619
HPE Servers RockStars award (every Half Year) for employees who have gone way beyond the call of duty to make a huge impact on the success of HPE Servers in 2H’16. Awarded by Division to recognize and congratulate our RockStars on their exceptional work and accomplishments every half year!
Hewlett Packard Enterprise
HPE Servers RockStar - 2'H 2016
Advanced Computer Architecture
ECEN 676
Computer Architecture
CSCE 614
Computer Communications and Networking
ELEN 602
Theory of Algorithms
CSCE 629
•	Be responsible to implement the computing platform (the execute unit and the AMBA AXI protocol) in Verilog.
•	Launch the simulation in SoC Designer. The simulating components are created in Carbon Model Studio.
A Reconfigurable computing approach for efficient and scalable semantic information filtering
NVIDIA
courses.nvidia.com
88faedf0b9db488daf85f50ef5e18758
Building Intelligent Recommender Systems
https://courses.nvidia.com/certificates/88faedf0b9db488daf85f50ef5e18758
Coursera
www.coursera.org
7SGB5TP5LAYB
AI for everyone
https://www.coursera.org/account/accomplishments/certificate/7SGB5TP5LAYB
Coursera
www.coursera.org
39794BYYX6GW
Neural Networks and Deep Learning
https://www.coursera.org/account/accomplishments/verify/39794BYYX6GW
NVIDIA
courses.nvidia.com
0a22fcb5558f4636aee02d232e018d68
Deep Learning For Intelligent Video Analytics
https://courses.nvidia.com/certificates/0a22fcb5558f4636aee02d232e018d68
Rob Zedaker
      
          



            
              
        
              
  

    
        Over the past 2 years I've had the opportunity to work with Dr. Tripathy on a designing and building a cutting edge architecture to support the next generation of converged systems for the aerospace industry.  I found his extraordinary way of approaching a challenge, innovative thinking and hard work to be contagious.  Aalap "run's toward the fire" to help his colleagues and customers come up with alternatives that will change the way Information Technology and Operations Technology work together. I'm proud and fortunate to be a colleague of Dr. Tripathy and look forward seeing what he will engineer next, as we shoot stars. David Joy
      
          



            
              
        
              
  

    
        After working with Dr. Aalap for a while now, he has earned my utmost respect for possessing a true R&D mindset.  While his focus is on technology, he goes beyond a strict engineering thought process and considers customer requirements and desires, and financial aspects of the new products and solutions he helps to design.  I have noticed that, when he speaks, people listen.  He also listens, and asks plenty of questions so as to try to completely grasp all avenues of the situation.  A great person to have on the team.