aaditya chaudhary
Design Engineer 2 at Ampere
design engineer 2 ampere computing
- > graduate student north carolina state university majoring computer engineering specialization asic / soc / fpga / rtl / cpu design/verification cpu / gpu architecture - > technical skill : verilog , system verilog ( uvm / ovm ) , c++ , c , python , embedded c , cuda , opencl - > tools/environment : synopsys design compiler , mentor graphic questasim / modelsim , xilinx vivado , xilinx ise latex - > hardware interfacing : virtex 6 fpga , spartan 3an fpga , artix-7 fpga , zynq z7010 soc , raspberry pi 3 , msp430 , msp 432 , gpgpusim - > operating system : window - 98 / xp / 7 / 8 / 10 linux - ubuntu / manjaro / centos / raspbian - > graduate course : ece 564 - asic fpga design ece 506 - architecture parallel computer ece 563 - microprocessor architecture ece 745 - asic verification ece 748 - advanced functional verification uvm ece 786 - advanced computer architecture : data parallel processor ( gpu architecture ) ece 542 - neural network udemy - learn build ovm & uvm testbenches scratch , soc verification using systemverilog - > project : 1 ) verification i2c multiple bus controller 2 ) functional verification lc3 controller using uvm framework 3 ) convolution neural network - asic implementation lstm cell 4 ) light runtime system opencl fpga gpu , providing configurable scheduling 5 ) mips-like 5-stage pipeline processor simulator 6 ) l1 l2 cache simulator 7 ) bus based cache coherence simulator 8 ) 2-d convolution tiling coarsening 9 ) radix sort openmp please contact achaudh9 @ ncsu.edu find might contribute add value organization .
Ampere
https://www.linkedin.com/company/amperecomp
Portland, Oregon, United States
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Design Engineer 2
North Carolina State University
https://www.linkedin.com/company/north-carolina-state-university
NPS Lab (Dr. Michela Becchi):
Designed a light runtime system for OpenCL applications running on FPGA and GPU, providing configurable scheduling mechanisms.
Raleigh, North Carolina, United States
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Graduate Student Researcher
North Carolina State University
https://www.linkedin.com/company/north-carolina-state-university
MBA555 - Product Design and Development
Raleigh, North Carolina, United States
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Graduate Teaching Assistant
Indian Institute of Management Bangalore
https://www.linkedin.com/company/indian-institute-of-management-bangalore
Bangalore, India
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Incubatee
Soil
Bengaluru Area, India
Co-Founder
Indian Institute of Technology, Kanpur
https://www.linkedin.com/company/indian-institute-of-technology-kanpur
Hardware-software coprocessor design: Designed Co-processor using AXI bus interface and custom IP cores. Implemented AXI Uartlite, AXI Timer, Block Ram and System Cache IPs.
Kanpur Area, India
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Winter Research Intern
Bhabha Atomic Research Centre
https://www.linkedin.com/company/bhabha-atomic-research-centre
Evaluated an AES module implemented on FPGA and compared its correctness and performance with OpenSSL cryptographic library on linux platform. It involved the study and development of test benches and host interface modules using a python based hardware description language(MYHDL) and an in-house developed FHPClib framework.
Mumbai Area, India
Summer Research Intern
Telcoma Technologies
https://www.linkedin.com/company/telcoma-technologies
During this internship, I did RF survey, 2G ARFCN planning for Mohali(using MCOM software and Ericsson engineering tool), 3G planning for Mohali, 4G backbone planning(TEMS 17.x software used for drive testing and network optimization) and 4G network simulation(using Cisco Packet Tracer software).
Chandigarh Area, India
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Summer Intern
Robosapiens Technologies(P) Ltd.
In this training, I learned the basic image processing tools in MATLAB, color detection technique, Object tracking and the GUIDE tool.
Noida Area, India
Trainee
Master of Science - MS
Computer Engineering
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North Carolina State University
https://www.linkedin.com/school/north-carolina-state-university/
Bachelor of Technology (B.Tech.)
Electronics and Telecommunication Engineering
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National Institute of Technology Raipur
https://www.linkedin.com/school/national-institute-of-technology-raipur/
D.A.V Public School Bilaspur
It was the photography club of NIT Raipur.
Click Club
Head Coordinator
Unnat Bharat Abhiyan
Committee member
It was NIT Raipur's official committee for electronics enthusiasts.
Electronics Engineering Association (ASSETS)
Committee member
Among top 10 winners of Texas Instruments Inc. India Innovation Challenge Design Contest 2016 with over 11000 participants from 624 colleges of India. Got incubation for 1 year at IIM Bangalore and a funding of INR2500000/- from Texas Instruments, IIM Banglore and DST for this project.
Texas Instruments
Winner of Texas Instrument Innovation Challenge - India Design Contest 2016
ASIC Verification
ECE 745
ASIC and FPGA Design
ECE 564
Advanced Computer Architecture - Data Parallel Processors (GPGPU)
ECE 786
Advanced Verification with UVM
ECE 748
Architecture of Parallel Computers
ECE 506
Microprocessor Architecture
ECE 563
Neural Networks
ECE 542
Strategy Management
BUS 501
Designed a light runtime system for OpenCL applications running on FPGA and GPU, providing configurable scheduling mechanisms.
Light Runtime for OpenCL applications on FPGA and GPU
Generated discrete frequencies pertaining to 64 musical notes over 5 octaves using a binary counter to toggle a GPIO pin connected to a speaker.
Musical Notes Generation with FPGA
Developed a vertically and horizontally reusable layered testbench to verify block to chip level functionality. Functional coverage was achieved using a regression of directed and random testing with different seeds. Block level as well as propagated bugs were found by the predictor-scoreboard functionality. The simulation was speeded up by making the testbench emulatable and running it on an veloce emulator.
Functional Verification of LC3 Controller using UVM Framework
Constructed a layered test bench using System Verilog to verify I2C and Wishbone protocol functionality of the DUT. Implemented verification plan, test with constrained randomization, generator, env_configuration, environment, predictor, scoreboard, coverage and Agent(Driver + Monitor). Analyzed functional coverage for closing holes.
Verification of I2C multiple bus controller
kernel function with parallelized 2-D convolution algorithm tested on NVIDIA GT740M. Benchmarked the performance with different grid and block size.
2-D Convolution using CUDA
Implemented a bus-based cache coherent simulator supporting 4 protocols - MSI, MESI, MOSI and MOESI and analyzed performance for varying cache configurations and protocols.
Bus Based Cache Coherence Protocol Simulator
LSTM cell is used in convolution neural networks. Fetched data from SRAM and performed mathematical operations - matrix multiplication, addition and truncation. Optimized the design by adding pipelines to it. Performance: Area - 7243 um2 and Clock Period -9.1 ns.
Convolution Neural Network - ASIC implementation of LSTM Cell
Data path and control path with support for integer and floating point unit. Handled
Structural, control and data hazards.
MIPS-like 5-Stage Pipeline Processor Simulator
Deployed a two-level cache hierarchy exhibiting LRU and LFU policies with
write-back and write-allocate.
L1 and L2 Cache Simulator
Parallelized the radix sort algorithm with openMP and compared its performance with non-parallel radix sort algorithm.
Radix Sort in openMP
A 3x3 non-blocking virtual cut-through switching router has been designed and simulated on Xilinx Vivado.
Design and Simulation of a router on FPGA
It was part of a freelancing project. In this project, I used the beautiful soup and scrapy library of python to scrape text from various national newspaper websites and save it in a database, which was used by the local newspaper agency to get its content automatically.
Web crawlers for newspaper agency
https://github.com/adi-007/webCrawler
In this project, we have developed an architectural design of the Zigbee Transmitter through Verilog HDL. As the transmitter is an integration of various blocks, so each block has been individually simulated. The architecture has been simulated using post route simulations.
Design and Simulation of Physical Layer Blocks of ZigBee Transmitter
Detects the correct box using RFID and pick and place it at the desired location. Locomotion of vehicle is controlled using an android application which uses Bluetooth as a means of communication. The purpose of this project is automation of industry.
Pick & Place robot
The basic idea of the project was to create a single battery powered WIFI module of the size of our fist which would transfer data from normal USB stick to any WIFI enabled device and act as a data sharing hub. This device can also be configured for sharing wireless Internet connection.
Wireless USB Data Transfer Module using Raspberry pi 3
https://github.com/adi-007/Wireless-USB-transfer-module
It’s a basic project using 555 timer IC and IR sensor. The 555 IC is used in bistable
mode so whenever the voltage drops at the trigger pin(which is connected to IR
sensors), the output becomes high and a musical bell starts.
Automatic door bell and light system
Education
Unnat Bharat Abhiyan, NIT Raipur
Unnat Bharat Abhiyan is inspired by the vision of transformational change in rural development processes by leveraging technical institutions to help build the architecture of an inclusive India. Under this organization, I used to visit Guma village to teach Mathematics and English to higher secondary students in a government school.
Teacher
North Carolina State University
ASIC Design Project - Summer Camp (2020)
LinkedIn
www.linkedin.com
Programming Foundations: Data Structures
http://www.linkedin.com/learning/programming-foundations-data-structures-2
Udemy
www.udemy.com
UC-9437c10e-9cb4-414e-8b19-7907047ea68c
Learn to build OVM & UVM Testbenches from scratch
https://www.udemy.com/certificate/UC-9437c10e-9cb4-414e-8b19-7907047ea68c/
Udemy
www.udemy.com
UC-e89f182f-d89f-4b68-805f-9b655abaae64
SOC Verification using SystemVerilog
https://www.udemy.com/certificate/UC-e89f182f-d89f-4b68-805f-9b655abaae64/
Amazon Web Services (AWS)
www.qwiklabs.com
Compute and Networking
https://www.qwiklabs.com/public_profiles/71af4ab2-9096-45fe-af2a-80b1e65ce6cd
Coursera Course Certificates
www.coursera.org
2J2VXPMR3E7L
The Raspberry Pi Platform and Python Programming for the Raspberry Pi
https://www.coursera.org/account/accomplishments/verify/2J2VXPMR3E7L
Udemy
www.udemy.com
UC-0V2FEK8U
Automate the Boring Stuff with Python Programming
https://www.udemy.com/certificate/UC-0V2FEK8U/
Udemy
www.udemy.com
UC-X2PVKQ1L
Github introduction to version control and remote files
https://www.udemy.com/certificate/UC-X2PVKQ1L/
Udemy
www.udemy.com
UC-AGYCPX2V
Mastering Microcontroller with Embedded Driver Development
https://www.udemy.com/certificate/UC-AGYCPX2V/
https://www.linkedin.com/in/pranav-bhave
Sunnyvale, CA
Pranav Bhave
Architectural Design Verification Engineer at Ampere Computing
https://www.linkedin.com/in/aravind-sampathkumar
Raleigh, NC
Aravind Sampathkumar
CPU Verification Engineer at Ampere
https://www.linkedin.com/in/shrihari-sundararaj-407704145
Austin, TX
Shrihari Sundararaj
Silicon Design Engineer 2 at AMD
https://www.linkedin.com/in/akshata-maltare
Portland, OR
Akshata Maltare
CPU Verification Engineer at Ampere
https://www.linkedin.com/in/girish-george-46884051
San Jose, CA
Girish George
Senior CPU Verification Engineer at Nvidia
https://www.linkedin.com/in/ankith-muralidhar
Orlando, FL
Ankith Muralidhar
Silicon Design Engineer 2 at AMD
https://www.linkedin.com/in/chaitrali-joshi-539ab742
Santa Clara, CA
Chaitrali Joshi
Emulation Engineer at Ampere
https://www.linkedin.com/in/mysorena
Santa Clara, CA
Praveen Mysore
Physical Design Engineer at Ampere
https://www.linkedin.com/in/anjanapadmanabhan98
Raleigh, NC
Anjana Padmanabhan
Masters Student at NCSU Computer Engineering| Looking for full time opportunities in digital VLSI and Comp Arch.
https://www.linkedin.com/in/jharupesh
Portland, OR
Rupesh Jha
Graduate Student at Portland State University | Physical Design Intern at Ampere Computing
https://www.linkedin.com/in/noufalputhukkudi
Austin, TX
Noufal Puthukkudi
RTL Design Engineer at Amazon
https://www.linkedin.com/in/atharva-dole
Portland, OR
Atharva Dole
Actively seeking Co-op/Internship in Digital Design/Verification
https://www.linkedin.com/in/sriram-sundararaj-93a84a12b
Raleigh, NC
Sriram Sundararaj
Silicon Design Engineer 2 at AMD
https://www.linkedin.com/in/rsindhu
Austin, TX
Sindhu Ramamurthy
Design Verification Engineer at Cirrus Logic
https://www.linkedin.com/in/madhuranadgouda
United States
Madhura Nadgouda
Design Engineer at Analog Devices
https://www.linkedin.com/in/hari-priya-vankineni-2ba963bb
Austin, TX
Hari Priya Vankineni
CPU Design Engineer at Intel Corporation
https://www.linkedin.com/in/suresh-natarajan-a5756abb
San Francisco Bay Area
Suresh Natarajan
CPU Design Verification Engineer at AMD
https://www.linkedin.com/in/mandar-nevpurkar-415b6363
San Francisco Bay Area
Mandar Nevpurkar
Design Verification Engineer at Apple
Sathish Pathakota
      
          



            
              
        
              
  

    
        I was a business mentor for a startup co-founded by Aaditya at IIMB NSRCEL, Bangalore and had regular interactions with him in formal and informal settings. In addition to his technical prowess, Aaditya attitude and behavior impressed the most. He was always positive, smiling and took any feedback well. I would hire Aaditya without any hesitation based on his technical and personal skills and behavior. I am positive that he will succeed in any venture or activity he is involved in. I wish him the best . Dr. Shubhankar Majumdar
      
          



            
              
        
              
  

    
        Aaditya worked under me for more than a year, during which I was impressed by his verilog & python programming skills and his ability to quickly grab new concepts. His commitment to the project was highly appreciable, and the significant contribution he gave to meet the objectives even when they were over the team capacity made the success of the whole team happen. Despite the high pressure, he consistently delivered top quality work and always used to pick the most challenging tasks. Also, it's worth mentioning that he was considered as a reference by other project mates. Thus, I would be delighted to recommend him to anybody.
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We now have more than 30 #CloudNative software packages supported by Ampere A1 instance on #OracleCloud! Visit this link to learn more.…
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Gujarat, India
AadiTya ChauDhary
Owner at THE NEXT CERAMIC HOUSE
https://in.linkedin.com/in/aaditya-chaudhary-862a5a98
Ahmedabad
Aaditya Chaudhary
Senior Engineer at Montecarlo Limited
https://ca.linkedin.com/in/aaditya-chaudhary-a79134187
Greater Toronto Area, Canada
Aaditya Chaudhary
Cloud Software Infrastructure Intern At Nvidia
https://in.linkedin.com/in/aaditya-chaudhary-18770a21
Mumbai
Aaditya Chaudhary
Manager HR at Bajaj Consumer Care
RTL Verification Professionals
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College Grad Recruiting
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ASIC & FPGA Experts Group
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Microsoft University Recruiting Team
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FPGA — Design and Programmable Devices
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UVM Verification Professionals Group
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Semiconductor Professional's Group
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Exascale Computing
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ASIC and FPGA Design and Verification Contract  Openings
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RTL to GDSII
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OpenACC Developers
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Verification Academy
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Student Conferences, Opportunities & Connections
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Entry Level Jobs and Internships: College Recruiter
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